mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-26 00:24:03 +02:00
14ec28a2a3
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29001 3c298f89-4303-0410-b956-a3cf2f4a3e73
13634 lines
564 KiB
Diff
13634 lines
564 KiB
Diff
--- /dev/null
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+++ b/arch/mips/include/asm/mach-lantiq/falcon/gpon_reg_base.h
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@@ -0,0 +1,376 @@
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+/******************************************************************************
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+
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+ Copyright (c) 2010
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+ Lantiq Deutschland GmbH
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+
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+ For licensing information, see the file 'LICENSE' in the root folder of
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+ this software module.
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+
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+******************************************************************************/
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+
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+#ifndef _gpon_reg_base_h
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+#define _gpon_reg_base_h
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+
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+/** \addtogroup GPON_BASE
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+ @{
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+*/
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+
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+#ifndef KSEG1
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+#define KSEG1 0xA0000000
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+#endif
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+
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+/** address range for ebu
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+ 0x18000000--0x180000FF */
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+#define GPON_EBU_BASE (KSEG1 | 0x18000000)
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+#define GPON_EBU_END (KSEG1 | 0x180000FF)
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+#define GPON_EBU_SIZE 0x00000100
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+/** address range for gpearb
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+ 0x1D400100--0x1D4001FF */
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+#define GPON_GPEARB_BASE (KSEG1 | 0x1D400100)
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+#define GPON_GPEARB_END (KSEG1 | 0x1D4001FF)
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+#define GPON_GPEARB_SIZE 0x00000100
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+/** address range for tmu
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+ 0x1D404000--0x1D404FFF */
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+#define GPON_TMU_BASE (KSEG1 | 0x1D404000)
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+#define GPON_TMU_END (KSEG1 | 0x1D404FFF)
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+#define GPON_TMU_SIZE 0x00001000
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+/** address range for iqm
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+ 0x1D410000--0x1D41FFFF */
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+#define GPON_IQM_BASE (KSEG1 | 0x1D410000)
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+#define GPON_IQM_END (KSEG1 | 0x1D41FFFF)
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+#define GPON_IQM_SIZE 0x00010000
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+/** address range for octrlg
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+ 0x1D420000--0x1D42FFFF */
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+#define GPON_OCTRLG_BASE (KSEG1 | 0x1D420000)
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+#define GPON_OCTRLG_END (KSEG1 | 0x1D42FFFF)
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+#define GPON_OCTRLG_SIZE 0x00010000
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+/** address range for octrll0
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+ 0x1D440000--0x1D4400FF */
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+#define GPON_OCTRLL0_BASE (KSEG1 | 0x1D440000)
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+#define GPON_OCTRLL0_END (KSEG1 | 0x1D4400FF)
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+#define GPON_OCTRLL0_SIZE 0x00000100
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+/** address range for octrll1
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+ 0x1D440100--0x1D4401FF */
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+#define GPON_OCTRLL1_BASE (KSEG1 | 0x1D440100)
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+#define GPON_OCTRLL1_END (KSEG1 | 0x1D4401FF)
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+#define GPON_OCTRLL1_SIZE 0x00000100
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+/** address range for octrll2
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+ 0x1D440200--0x1D4402FF */
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+#define GPON_OCTRLL2_BASE (KSEG1 | 0x1D440200)
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+#define GPON_OCTRLL2_END (KSEG1 | 0x1D4402FF)
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+#define GPON_OCTRLL2_SIZE 0x00000100
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+/** address range for octrll3
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+ 0x1D440300--0x1D4403FF */
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+#define GPON_OCTRLL3_BASE (KSEG1 | 0x1D440300)
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+#define GPON_OCTRLL3_END (KSEG1 | 0x1D4403FF)
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+#define GPON_OCTRLL3_SIZE 0x00000100
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+/** address range for octrlc
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+ 0x1D441000--0x1D4410FF */
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+#define GPON_OCTRLC_BASE (KSEG1 | 0x1D441000)
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+#define GPON_OCTRLC_END (KSEG1 | 0x1D4410FF)
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+#define GPON_OCTRLC_SIZE 0x00000100
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+/** address range for ictrlg
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+ 0x1D450000--0x1D45FFFF */
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+#define GPON_ICTRLG_BASE (KSEG1 | 0x1D450000)
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+#define GPON_ICTRLG_END (KSEG1 | 0x1D45FFFF)
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+#define GPON_ICTRLG_SIZE 0x00010000
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+/** address range for ictrll0
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+ 0x1D460000--0x1D4601FF */
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+#define GPON_ICTRLL0_BASE (KSEG1 | 0x1D460000)
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+#define GPON_ICTRLL0_END (KSEG1 | 0x1D4601FF)
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+#define GPON_ICTRLL0_SIZE 0x00000200
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+/** address range for ictrll1
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+ 0x1D460200--0x1D4603FF */
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+#define GPON_ICTRLL1_BASE (KSEG1 | 0x1D460200)
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+#define GPON_ICTRLL1_END (KSEG1 | 0x1D4603FF)
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+#define GPON_ICTRLL1_SIZE 0x00000200
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+/** address range for ictrll2
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+ 0x1D460400--0x1D4605FF */
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+#define GPON_ICTRLL2_BASE (KSEG1 | 0x1D460400)
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+#define GPON_ICTRLL2_END (KSEG1 | 0x1D4605FF)
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+#define GPON_ICTRLL2_SIZE 0x00000200
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+/** address range for ictrll3
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+ 0x1D460600--0x1D4607FF */
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+#define GPON_ICTRLL3_BASE (KSEG1 | 0x1D460600)
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+#define GPON_ICTRLL3_END (KSEG1 | 0x1D4607FF)
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+#define GPON_ICTRLL3_SIZE 0x00000200
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+/** address range for ictrlc0
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+ 0x1D461000--0x1D4610FF */
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+#define GPON_ICTRLC0_BASE (KSEG1 | 0x1D461000)
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+#define GPON_ICTRLC0_END (KSEG1 | 0x1D4610FF)
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+#define GPON_ICTRLC0_SIZE 0x00000100
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+/** address range for ictrlc1
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+ 0x1D461100--0x1D4611FF */
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+#define GPON_ICTRLC1_BASE (KSEG1 | 0x1D461100)
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+#define GPON_ICTRLC1_END (KSEG1 | 0x1D4611FF)
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+#define GPON_ICTRLC1_SIZE 0x00000100
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+/** address range for fsqm
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+ 0x1D500000--0x1D5FFFFF */
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+#define GPON_FSQM_BASE (KSEG1 | 0x1D500000)
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+#define GPON_FSQM_END (KSEG1 | 0x1D5FFFFF)
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+#define GPON_FSQM_SIZE 0x00100000
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+/** address range for pctrl
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+ 0x1D600000--0x1D6001FF */
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+#define GPON_PCTRL_BASE (KSEG1 | 0x1D600000)
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+#define GPON_PCTRL_END (KSEG1 | 0x1D6001FF)
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+#define GPON_PCTRL_SIZE 0x00000200
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+/** address range for link0
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+ 0x1D600200--0x1D6002FF */
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+#define GPON_LINK0_BASE (KSEG1 | 0x1D600200)
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+#define GPON_LINK0_END (KSEG1 | 0x1D6002FF)
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+#define GPON_LINK0_SIZE 0x00000100
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+/** address range for link1
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+ 0x1D600300--0x1D6003FF */
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+#define GPON_LINK1_BASE (KSEG1 | 0x1D600300)
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+#define GPON_LINK1_END (KSEG1 | 0x1D6003FF)
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+#define GPON_LINK1_SIZE 0x00000100
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+/** address range for link2
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+ 0x1D600400--0x1D6004FF */
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+#define GPON_LINK2_BASE (KSEG1 | 0x1D600400)
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+#define GPON_LINK2_END (KSEG1 | 0x1D6004FF)
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+#define GPON_LINK2_SIZE 0x00000100
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+/** address range for disp
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+ 0x1D600500--0x1D6005FF */
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+#define GPON_DISP_BASE (KSEG1 | 0x1D600500)
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+#define GPON_DISP_END (KSEG1 | 0x1D6005FF)
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+#define GPON_DISP_SIZE 0x00000100
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+/** address range for merge
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+ 0x1D600600--0x1D6006FF */
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+#define GPON_MERGE_BASE (KSEG1 | 0x1D600600)
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+#define GPON_MERGE_END (KSEG1 | 0x1D6006FF)
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+#define GPON_MERGE_SIZE 0x00000100
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+/** address range for tbm
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+ 0x1D600700--0x1D6007FF */
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+#define GPON_TBM_BASE (KSEG1 | 0x1D600700)
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+#define GPON_TBM_END (KSEG1 | 0x1D6007FF)
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+#define GPON_TBM_SIZE 0x00000100
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+/** address range for pe0
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+ 0x1D610000--0x1D61FFFF */
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+#define GPON_PE0_BASE (KSEG1 | 0x1D610000)
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+#define GPON_PE0_END (KSEG1 | 0x1D61FFFF)
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+#define GPON_PE0_SIZE 0x00010000
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+/** address range for pe1
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+ 0x1D620000--0x1D62FFFF */
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+#define GPON_PE1_BASE (KSEG1 | 0x1D620000)
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+#define GPON_PE1_END (KSEG1 | 0x1D62FFFF)
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+#define GPON_PE1_SIZE 0x00010000
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+/** address range for pe2
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+ 0x1D630000--0x1D63FFFF */
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+#define GPON_PE2_BASE (KSEG1 | 0x1D630000)
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+#define GPON_PE2_END (KSEG1 | 0x1D63FFFF)
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+#define GPON_PE2_SIZE 0x00010000
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+/** address range for pe3
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+ 0x1D640000--0x1D64FFFF */
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+#define GPON_PE3_BASE (KSEG1 | 0x1D640000)
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+#define GPON_PE3_END (KSEG1 | 0x1D64FFFF)
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+#define GPON_PE3_SIZE 0x00010000
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+/** address range for pe4
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+ 0x1D650000--0x1D65FFFF */
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+#define GPON_PE4_BASE (KSEG1 | 0x1D650000)
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+#define GPON_PE4_END (KSEG1 | 0x1D65FFFF)
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+#define GPON_PE4_SIZE 0x00010000
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+/** address range for pe5
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+ 0x1D660000--0x1D66FFFF */
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+#define GPON_PE5_BASE (KSEG1 | 0x1D660000)
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+#define GPON_PE5_END (KSEG1 | 0x1D66FFFF)
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+#define GPON_PE5_SIZE 0x00010000
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+/** address range for sys_gpe
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+ 0x1D700000--0x1D7000FF */
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+#define GPON_SYS_GPE_BASE (KSEG1 | 0x1D700000)
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+#define GPON_SYS_GPE_END (KSEG1 | 0x1D7000FF)
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+#define GPON_SYS_GPE_SIZE 0x00000100
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+/** address range for eim
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+ 0x1D800000--0x1D800FFF */
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+#define GPON_EIM_BASE (KSEG1 | 0x1D800000)
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+#define GPON_EIM_END (KSEG1 | 0x1D800FFF)
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+#define GPON_EIM_SIZE 0x00001000
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+/** address range for sxgmii
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+ 0x1D808800--0x1D8088FF */
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+#define GPON_SXGMII_BASE (KSEG1 | 0x1D808800)
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+#define GPON_SXGMII_END (KSEG1 | 0x1D8088FF)
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+#define GPON_SXGMII_SIZE 0x00000100
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+/** address range for sgmii
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+ 0x1D808C00--0x1D808CFF */
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+#define GPON_SGMII_BASE (KSEG1 | 0x1D808C00)
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+#define GPON_SGMII_END (KSEG1 | 0x1D808CFF)
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+#define GPON_SGMII_SIZE 0x00000100
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+/** address range for gpio0
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+ 0x1D810000--0x1D81007F */
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+#define GPON_GPIO0_BASE (KSEG1 | 0x1D810000)
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+#define GPON_GPIO0_END (KSEG1 | 0x1D81007F)
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+#define GPON_GPIO0_SIZE 0x00000080
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+/** address range for gpio2
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+ 0x1D810100--0x1D81017F */
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+#define GPON_GPIO2_BASE (KSEG1 | 0x1D810100)
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+#define GPON_GPIO2_END (KSEG1 | 0x1D81017F)
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+#define GPON_GPIO2_SIZE 0x00000080
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+/** address range for sys_eth
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+ 0x1DB00000--0x1DB000FF */
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+#define GPON_SYS_ETH_BASE (KSEG1 | 0x1DB00000)
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+#define GPON_SYS_ETH_END (KSEG1 | 0x1DB000FF)
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+#define GPON_SYS_ETH_SIZE 0x00000100
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+/** address range for padctrl0
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+ 0x1DB01000--0x1DB010FF */
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+#define GPON_PADCTRL0_BASE (KSEG1 | 0x1DB01000)
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+#define GPON_PADCTRL0_END (KSEG1 | 0x1DB010FF)
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+#define GPON_PADCTRL0_SIZE 0x00000100
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+/** address range for padctrl2
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+ 0x1DB02000--0x1DB020FF */
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+#define GPON_PADCTRL2_BASE (KSEG1 | 0x1DB02000)
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+#define GPON_PADCTRL2_END (KSEG1 | 0x1DB020FF)
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+#define GPON_PADCTRL2_SIZE 0x00000100
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+/** address range for gtc
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+ 0x1DC05000--0x1DC052D4 */
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+#define GPON_GTC_BASE (KSEG1 | 0x1DC05000)
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+#define GPON_GTC_END (KSEG1 | 0x1DC052D4)
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+#define GPON_GTC_SIZE 0x000002D5
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+/** address range for pma
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+ 0x1DD00000--0x1DD003FF */
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+#define GPON_PMA_BASE (KSEG1 | 0x1DD00000)
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+#define GPON_PMA_END (KSEG1 | 0x1DD003FF)
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+#define GPON_PMA_SIZE 0x00000400
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+/** address range for fcsic
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+ 0x1DD00600--0x1DD0061F */
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+#define GPON_FCSIC_BASE (KSEG1 | 0x1DD00600)
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+#define GPON_FCSIC_END (KSEG1 | 0x1DD0061F)
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+#define GPON_FCSIC_SIZE 0x00000020
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+/** address range for pma_int200
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+ 0x1DD00700--0x1DD0070F */
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+#define GPON_PMA_INT200_BASE (KSEG1 | 0x1DD00700)
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+#define GPON_PMA_INT200_END (KSEG1 | 0x1DD0070F)
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+#define GPON_PMA_INT200_SIZE 0x00000010
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+/** address range for pma_inttx
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+ 0x1DD00720--0x1DD0072F */
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+#define GPON_PMA_INTTX_BASE (KSEG1 | 0x1DD00720)
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+#define GPON_PMA_INTTX_END (KSEG1 | 0x1DD0072F)
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+#define GPON_PMA_INTTX_SIZE 0x00000010
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+/** address range for pma_intrx
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+ 0x1DD00740--0x1DD0074F */
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+#define GPON_PMA_INTRX_BASE (KSEG1 | 0x1DD00740)
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+#define GPON_PMA_INTRX_END (KSEG1 | 0x1DD0074F)
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+#define GPON_PMA_INTRX_SIZE 0x00000010
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+/** address range for gtc_pma
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+ 0x1DEFFF00--0x1DEFFFFF */
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+#define GPON_GTC_PMA_BASE (KSEG1 | 0x1DEFFF00)
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+#define GPON_GTC_PMA_END (KSEG1 | 0x1DEFFFFF)
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+#define GPON_GTC_PMA_SIZE 0x00000100
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+/** address range for sys
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+ 0x1DF00000--0x1DF000FF */
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+#define GPON_SYS_BASE (KSEG1 | 0x1DF00000)
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+#define GPON_SYS_END (KSEG1 | 0x1DF000FF)
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+#define GPON_SYS_SIZE 0x00000100
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+/** address range for asc1
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+ 0x1E100B00--0x1E100BFF */
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+#define GPON_ASC1_BASE (KSEG1 | 0x1E100B00)
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+#define GPON_ASC1_END (KSEG1 | 0x1E100BFF)
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+#define GPON_ASC1_SIZE 0x00000100
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+/** address range for asc0
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+ 0x1E100C00--0x1E100CFF */
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+#define GPON_ASC0_BASE (KSEG1 | 0x1E100C00)
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+#define GPON_ASC0_END (KSEG1 | 0x1E100CFF)
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+#define GPON_ASC0_SIZE 0x00000100
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+/** address range for i2c
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+ 0x1E200000--0x1E20FFFF */
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+#define GPON_I2C_BASE (KSEG1 | 0x1E200000)
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+#define GPON_I2C_END (KSEG1 | 0x1E20FFFF)
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+#define GPON_I2C_SIZE 0x00010000
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+/** address range for gpio1
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+ 0x1E800100--0x1E80017F */
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+#define GPON_GPIO1_BASE (KSEG1 | 0x1E800100)
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+#define GPON_GPIO1_END (KSEG1 | 0x1E80017F)
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+#define GPON_GPIO1_SIZE 0x00000080
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+/** address range for gpio3
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+ 0x1E800200--0x1E80027F */
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+#define GPON_GPIO3_BASE (KSEG1 | 0x1E800200)
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+#define GPON_GPIO3_END (KSEG1 | 0x1E80027F)
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+#define GPON_GPIO3_SIZE 0x00000080
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+/** address range for gpio4
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+ 0x1E800300--0x1E80037F */
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+#define GPON_GPIO4_BASE (KSEG1 | 0x1E800300)
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+#define GPON_GPIO4_END (KSEG1 | 0x1E80037F)
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+#define GPON_GPIO4_SIZE 0x00000080
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+/** address range for padctrl1
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+ 0x1E800400--0x1E8004FF */
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+#define GPON_PADCTRL1_BASE (KSEG1 | 0x1E800400)
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+#define GPON_PADCTRL1_END (KSEG1 | 0x1E8004FF)
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+#define GPON_PADCTRL1_SIZE 0x00000100
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+/** address range for padctrl3
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+ 0x1E800500--0x1E8005FF */
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+#define GPON_PADCTRL3_BASE (KSEG1 | 0x1E800500)
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+#define GPON_PADCTRL3_END (KSEG1 | 0x1E8005FF)
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+#define GPON_PADCTRL3_SIZE 0x00000100
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+/** address range for padctrl4
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+ 0x1E800600--0x1E8006FF */
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+#define GPON_PADCTRL4_BASE (KSEG1 | 0x1E800600)
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+#define GPON_PADCTRL4_END (KSEG1 | 0x1E8006FF)
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+#define GPON_PADCTRL4_SIZE 0x00000100
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+/** address range for status
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+ 0x1E802000--0x1E80207F */
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+#define GPON_STATUS_BASE (KSEG1 | 0x1E802000)
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+#define GPON_STATUS_END (KSEG1 | 0x1E80207F)
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+#define GPON_STATUS_SIZE 0x00000080
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+/** address range for dcdc_1v0
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+ 0x1E803000--0x1E8033FF */
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+#define GPON_DCDC_1V0_BASE (KSEG1 | 0x1E803000)
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+#define GPON_DCDC_1V0_END (KSEG1 | 0x1E8033FF)
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+#define GPON_DCDC_1V0_SIZE 0x00000400
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+/** address range for dcdc_ddr
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+ 0x1E804000--0x1E8043FF */
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+#define GPON_DCDC_DDR_BASE (KSEG1 | 0x1E804000)
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+#define GPON_DCDC_DDR_END (KSEG1 | 0x1E8043FF)
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+#define GPON_DCDC_DDR_SIZE 0x00000400
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+/** address range for dcdc_apd
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+ 0x1E805000--0x1E8053FF */
|
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+#define GPON_DCDC_APD_BASE (KSEG1 | 0x1E805000)
|
|
+#define GPON_DCDC_APD_END (KSEG1 | 0x1E8053FF)
|
|
+#define GPON_DCDC_APD_SIZE 0x00000400
|
|
+/** address range for sys1
|
|
+ 0x1EF00000--0x1EF000FF */
|
|
+#define GPON_SYS1_BASE (KSEG1 | 0x1EF00000)
|
|
+#define GPON_SYS1_END (KSEG1 | 0x1EF000FF)
|
|
+#define GPON_SYS1_SIZE 0x00000100
|
|
+/** address range for sbs0ctrl
|
|
+ 0x1F080000--0x1F0801FF */
|
|
+#define GPON_SBS0CTRL_BASE (KSEG1 | 0x1F080000)
|
|
+#define GPON_SBS0CTRL_END (KSEG1 | 0x1F0801FF)
|
|
+#define GPON_SBS0CTRL_SIZE 0x00000200
|
|
+/** address range for sbs0red
|
|
+ 0x1F080200--0x1F08027F */
|
|
+#define GPON_SBS0RED_BASE (KSEG1 | 0x1F080200)
|
|
+#define GPON_SBS0RED_END (KSEG1 | 0x1F08027F)
|
|
+#define GPON_SBS0RED_SIZE 0x00000080
|
|
+/** address range for sbs0ram
|
|
+ 0x1F200000--0x1F32FFFF */
|
|
+#define GPON_SBS0RAM_BASE (KSEG1 | 0x1F200000)
|
|
+#define GPON_SBS0RAM_END (KSEG1 | 0x1F32FFFF)
|
|
+#define GPON_SBS0RAM_SIZE 0x00130000
|
|
+/** address range for ddrdb
|
|
+ 0x1F701000--0x1F701FFF */
|
|
+#define GPON_DDRDB_BASE (KSEG1 | 0x1F701000)
|
|
+#define GPON_DDRDB_END (KSEG1 | 0x1F701FFF)
|
|
+#define GPON_DDRDB_SIZE 0x00001000
|
|
+/** address range for sbiu
|
|
+ 0x1F880000--0x1F8800FF */
|
|
+#define GPON_SBIU_BASE (KSEG1 | 0x1F880000)
|
|
+#define GPON_SBIU_END (KSEG1 | 0x1F8800FF)
|
|
+#define GPON_SBIU_SIZE 0x00000100
|
|
+/** address range for icu0
|
|
+ 0x1F880200--0x1F8802DF */
|
|
+#define GPON_ICU0_BASE (KSEG1 | 0x1F880200)
|
|
+#define GPON_ICU0_END (KSEG1 | 0x1F8802DF)
|
|
+#define GPON_ICU0_SIZE 0x000000E0
|
|
+/** address range for icu1
|
|
+ 0x1F880300--0x1F8803DF */
|
|
+#define GPON_ICU1_BASE (KSEG1 | 0x1F880300)
|
|
+#define GPON_ICU1_END (KSEG1 | 0x1F8803DF)
|
|
+#define GPON_ICU1_SIZE 0x000000E0
|
|
+/** address range for wdt
|
|
+ 0x1F8803F0--0x1F8803FF */
|
|
+#define GPON_WDT_BASE (KSEG1 | 0x1F8803F0)
|
|
+#define GPON_WDT_END (KSEG1 | 0x1F8803FF)
|
|
+#define GPON_WDT_SIZE 0x00000010
|
|
+
|
|
+/*! @} */ /* GPON_BASE */
|
|
+
|
|
+#endif /* _gpon_reg_base_h */
|
|
+
|
|
--- /dev/null
|
|
+++ b/arch/mips/include/asm/mach-lantiq/falcon/i2c_reg.h
|
|
@@ -0,0 +1,830 @@
|
|
+/******************************************************************************
|
|
+
|
|
+ Copyright (c) 2010
|
|
+ Lantiq Deutschland GmbH
|
|
+
|
|
+ For licensing information, see the file 'LICENSE' in the root folder of
|
|
+ this software module.
|
|
+
|
|
+******************************************************************************/
|
|
+
|
|
+#ifndef _i2c_reg_h
|
|
+#define _i2c_reg_h
|
|
+
|
|
+/** \addtogroup I2C_REGISTER
|
|
+ @{
|
|
+*/
|
|
+/* access macros */
|
|
+#define i2c_r32(reg) reg_r32(&i2c->reg)
|
|
+#define i2c_w32(val, reg) reg_w32(val, &i2c->reg)
|
|
+#define i2c_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &i2c->reg)
|
|
+#define i2c_r32_table(reg, idx) reg_r32_table(i2c->reg, idx)
|
|
+#define i2c_w32_table(val, reg, idx) reg_w32_table(val, i2c->reg, idx)
|
|
+#define i2c_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, i2c->reg, idx)
|
|
+#define i2c_adr_table(reg, idx) adr_table(i2c->reg, idx)
|
|
+
|
|
+
|
|
+/** I2C register structure */
|
|
+struct gpon_reg_i2c
|
|
+{
|
|
+ /** I2C Kernel Clock Control Register */
|
|
+ unsigned int clc; /* 0x00000000 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_0; /* 0x00000004 */
|
|
+ /** I2C Identification Register */
|
|
+ unsigned int id; /* 0x00000008 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_1; /* 0x0000000C */
|
|
+ /** I2C RUN Control Register
|
|
+ This register enables and disables the I2C peripheral. Before enabling, the I2C has to be configured properly. After enabling no configuration is possible */
|
|
+ unsigned int run_ctrl; /* 0x00000010 */
|
|
+ /** I2C End Data Control Register
|
|
+ This register is used to either turn around the data transmission direction or to address another slave without sending a stop condition. Also the software can stop the slave-transmitter by sending a not-accolade when working as master-receiver or even stop data transmission immediately when operating as master-transmitter. The writing to the bits of this control register is only effective when in MASTER RECEIVES BYTES, MASTER TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state */
|
|
+ unsigned int endd_ctrl; /* 0x00000014 */
|
|
+ /** I2C Fractional Divider Configuration Register
|
|
+ These register is used to program the fractional divider of the I2C bus. Before the peripheral is switched on by setting the RUN-bit the two (fixed) values for the two operating frequencies are programmed into these (configuration) registers. The Register FDIV_HIGH_CFG has the same layout as I2C_FDIV_CFG. */
|
|
+ unsigned int fdiv_cfg; /* 0x00000018 */
|
|
+ /** I2C Fractional Divider (highspeed mode) Configuration Register
|
|
+ These register is used to program the fractional divider of the I2C bus. Before the peripheral is switched on by setting the RUN-bit the two (fixed) values for the two operating frequencies are programmed into these (configuration) registers. The Register FDIV_CFG has the same layout as I2C_FDIV_CFG. */
|
|
+ unsigned int fdiv_high_cfg; /* 0x0000001C */
|
|
+ /** I2C Address Configuration Register */
|
|
+ unsigned int addr_cfg; /* 0x00000020 */
|
|
+ /** I2C Bus Status Register
|
|
+ This register gives a status information of the I2C. This additional information can be used by the software to start proper actions. */
|
|
+ unsigned int bus_stat; /* 0x00000024 */
|
|
+ /** I2C FIFO Configuration Register */
|
|
+ unsigned int fifo_cfg; /* 0x00000028 */
|
|
+ /** I2C Maximum Received Packet Size Register */
|
|
+ unsigned int mrps_ctrl; /* 0x0000002C */
|
|
+ /** I2C Received Packet Size Status Register */
|
|
+ unsigned int rps_stat; /* 0x00000030 */
|
|
+ /** I2C Transmit Packet Size Register */
|
|
+ unsigned int tps_ctrl; /* 0x00000034 */
|
|
+ /** I2C Filled FIFO Stages Status Register */
|
|
+ unsigned int ffs_stat; /* 0x00000038 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_2; /* 0x0000003C */
|
|
+ /** I2C Timing Configuration Register */
|
|
+ unsigned int tim_cfg; /* 0x00000040 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_3[7]; /* 0x00000044 */
|
|
+ /** I2C Error Interrupt Request Source Mask Register */
|
|
+ unsigned int err_irqsm; /* 0x00000060 */
|
|
+ /** I2C Error Interrupt Request Source Status Register */
|
|
+ unsigned int err_irqss; /* 0x00000064 */
|
|
+ /** I2C Error Interrupt Request Source Clear Register */
|
|
+ unsigned int err_irqsc; /* 0x00000068 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_4; /* 0x0000006C */
|
|
+ /** I2C Protocol Interrupt Request Source Mask Register */
|
|
+ unsigned int p_irqsm; /* 0x00000070 */
|
|
+ /** I2C Protocol Interrupt Request Source Status Register */
|
|
+ unsigned int p_irqss; /* 0x00000074 */
|
|
+ /** I2C Protocol Interrupt Request Source Clear Register */
|
|
+ unsigned int p_irqsc; /* 0x00000078 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_5; /* 0x0000007C */
|
|
+ /** I2C Raw Interrupt Status Register */
|
|
+ unsigned int ris; /* 0x00000080 */
|
|
+ /** I2C Interrupt Mask Control Register */
|
|
+ unsigned int imsc; /* 0x00000084 */
|
|
+ /** I2C Masked Interrupt Status Register */
|
|
+ unsigned int mis; /* 0x00000088 */
|
|
+ /** I2C Interrupt Clear Register */
|
|
+ unsigned int icr; /* 0x0000008C */
|
|
+ /** I2C Interrupt Set Register */
|
|
+ unsigned int isr; /* 0x00000090 */
|
|
+ /** I2C DMA Enable Register */
|
|
+ unsigned int dmae; /* 0x00000094 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_6[8154]; /* 0x00000098 */
|
|
+ /** I2C Transmit Data Register */
|
|
+ unsigned int txd; /* 0x00008000 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_7[4095]; /* 0x00008004 */
|
|
+ /** I2C Receive Data Register */
|
|
+ unsigned int rxd; /* 0x0000C000 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_8[4095]; /* 0x0000C004 */
|
|
+};
|
|
+
|
|
+
|
|
+/* Fields of "I2C Kernel Clock Control Register" */
|
|
+/** Clock Divider for Optional Run Mode (AHB peripherals)
|
|
+ Max 8-bit divider value. Note: As long as the new divider value ORMC is not valid, the register returns 0x0000 00xx on reading. */
|
|
+#define I2C_CLC_ORMC_MASK 0x00FF0000
|
|
+/** field offset */
|
|
+#define I2C_CLC_ORMC_OFFSET 16
|
|
+/** Clock Divider for Normal Run Mode
|
|
+ Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long as the new divider value RMC is not valid, the register returns 0x0000 00xx on reading. */
|
|
+#define I2C_CLC_RMC_MASK 0x0000FF00
|
|
+/** field offset */
|
|
+#define I2C_CLC_RMC_OFFSET 8
|
|
+/** Fast Shut-Off Enable Bit */
|
|
+#define I2C_CLC_FSOE 0x00000020
|
|
+/* Disable
|
|
+#define I2C_CLC_FSOE_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_CLC_FSOE_EN 0x00000020
|
|
+/** Suspend Bit Write Enable for OCDS */
|
|
+#define I2C_CLC_SBWE 0x00000010
|
|
+/* Disable
|
|
+#define I2C_CLC_SBWE_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_CLC_SBWE_EN 0x00000010
|
|
+/** Disable External Request Disable */
|
|
+#define I2C_CLC_EDIS 0x00000008
|
|
+/* Enable
|
|
+#define I2C_CLC_EDIS_EN 0x00000000 */
|
|
+/** Disable */
|
|
+#define I2C_CLC_EDIS_DIS 0x00000008
|
|
+/** Suspend Enable Bit for OCDS */
|
|
+#define I2C_CLC_SPEN 0x00000004
|
|
+/* Disable
|
|
+#define I2C_CLC_SPEN_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_CLC_SPEN_EN 0x00000004
|
|
+/** Disable Status Bit
|
|
+ Bit DISS can be modified only by writing to bit DISR */
|
|
+#define I2C_CLC_DISS 0x00000002
|
|
+/* Enable
|
|
+#define I2C_CLC_DISS_EN 0x00000000 */
|
|
+/** Disable */
|
|
+#define I2C_CLC_DISS_DIS 0x00000002
|
|
+/** Disable Request Bit */
|
|
+#define I2C_CLC_DISR 0x00000001
|
|
+/* Module disable not requested
|
|
+#define I2C_CLC_DISR_OFF 0x00000000 */
|
|
+/** Module disable requested */
|
|
+#define I2C_CLC_DISR_ON 0x00000001
|
|
+
|
|
+/* Fields of "I2C Identification Register" */
|
|
+/** Module ID */
|
|
+#define I2C_ID_ID_MASK 0x0000FF00
|
|
+/** field offset */
|
|
+#define I2C_ID_ID_OFFSET 8
|
|
+/** Revision */
|
|
+#define I2C_ID_REV_MASK 0x000000FF
|
|
+/** field offset */
|
|
+#define I2C_ID_REV_OFFSET 0
|
|
+
|
|
+/* Fields of "I2C RUN Control Register" */
|
|
+/** Enabling I2C Interface
|
|
+ Only when this bit is set to zero, the configuration registers of the I2C peripheral are writable by SW. */
|
|
+#define I2C_RUN_CTRL_RUN 0x00000001
|
|
+/* Disable
|
|
+#define I2C_RUN_CTRL_RUN_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_RUN_CTRL_RUN_EN 0x00000001
|
|
+
|
|
+/* Fields of "I2C End Data Control Register" */
|
|
+/** Set End of Transmission
|
|
+ Note:Do not write '1' to this bit when bus is free. This will cause an abort after the first byte when a new transfer is started. */
|
|
+#define I2C_ENDD_CTRL_SETEND 0x00000002
|
|
+/* No-Operation
|
|
+#define I2C_ENDD_CTRL_SETEND_NOP 0x00000000 */
|
|
+/** Master Receives Bytes */
|
|
+#define I2C_ENDD_CTRL_SETEND_MRB 0x00000002
|
|
+/** Set Restart Condition */
|
|
+#define I2C_ENDD_CTRL_SETRSC 0x00000001
|
|
+/* No-Operation
|
|
+#define I2C_ENDD_CTRL_SETRSC_NOP 0x00000000 */
|
|
+/** Master Restart */
|
|
+#define I2C_ENDD_CTRL_SETRSC_RESTART 0x00000001
|
|
+
|
|
+/* Fields of "I2C Fractional Divider Configuration Register" */
|
|
+/** Decrement Value of fractional divider */
|
|
+#define I2C_FDIV_CFG_INC_MASK 0x00FF0000
|
|
+/** field offset */
|
|
+#define I2C_FDIV_CFG_INC_OFFSET 16
|
|
+/** Increment Value of fractional divider */
|
|
+#define I2C_FDIV_CFG_DEC_MASK 0x000007FF
|
|
+/** field offset */
|
|
+#define I2C_FDIV_CFG_DEC_OFFSET 0
|
|
+
|
|
+/* Fields of "I2C Fractional Divider (highspeed mode) Configuration Register" */
|
|
+/** Decrement Value of fractional divider */
|
|
+#define I2C_FDIV_HIGH_CFG_INC_MASK 0x00FF0000
|
|
+/** field offset */
|
|
+#define I2C_FDIV_HIGH_CFG_INC_OFFSET 16
|
|
+/** Increment Value of fractional divider */
|
|
+#define I2C_FDIV_HIGH_CFG_DEC_MASK 0x000007FF
|
|
+/** field offset */
|
|
+#define I2C_FDIV_HIGH_CFG_DEC_OFFSET 0
|
|
+
|
|
+/* Fields of "I2C Address Configuration Register" */
|
|
+/** Stop on Packet End
|
|
+ If device works as receiver a not acknowledge is generated in both cases. After successful transmission of a master code (during high speed mode) SOPE is not considered till a stop condition is manually generated by SETEND. */
|
|
+#define I2C_ADDR_CFG_SOPE 0x00200000
|
|
+/* Disable
|
|
+#define I2C_ADDR_CFG_SOPE_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_ADDR_CFG_SOPE_EN 0x00200000
|
|
+/** Stop on Not Acknowledge
|
|
+ After successful transmission of a master code (during high speed mode) SONA is not considered till a stop condition is manually generated by SETEND. */
|
|
+#define I2C_ADDR_CFG_SONA 0x00100000
|
|
+/* Disable
|
|
+#define I2C_ADDR_CFG_SONA_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_ADDR_CFG_SONA_EN 0x00100000
|
|
+/** Master Enable */
|
|
+#define I2C_ADDR_CFG_MnS 0x00080000
|
|
+/* Disable
|
|
+#define I2C_ADDR_CFG_MnS_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_ADDR_CFG_MnS_EN 0x00080000
|
|
+/** Master Code Enable */
|
|
+#define I2C_ADDR_CFG_MCE 0x00040000
|
|
+/* Disable
|
|
+#define I2C_ADDR_CFG_MCE_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_ADDR_CFG_MCE_EN 0x00040000
|
|
+/** General Call Enable */
|
|
+#define I2C_ADDR_CFG_GCE 0x00020000
|
|
+/* Disable
|
|
+#define I2C_ADDR_CFG_GCE_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_ADDR_CFG_GCE_EN 0x00020000
|
|
+/** Ten Bit Address Mode */
|
|
+#define I2C_ADDR_CFG_TBAM 0x00010000
|
|
+/* 7-bit address mode enabled.
|
|
+#define I2C_ADDR_CFG_TBAM_7bit 0x00000000 */
|
|
+/** 10-bit address mode enabled. */
|
|
+#define I2C_ADDR_CFG_TBAM_10bit 0x00010000
|
|
+/** I2C Bus device address
|
|
+ This is the address of this device. (Watch out for reserved addresses by referring to Phillips Spec V2.1) This could either be a 7bit- address (bits [7:1]) or a 10bit- address (bits [9:0]). Note:The validity of the bits are in accordance with the TBAM bit. Bit-1 (Bit-0) is the LSB of the device address. */
|
|
+#define I2C_ADDR_CFG_ADR_MASK 0x000003FF
|
|
+/** field offset */
|
|
+#define I2C_ADDR_CFG_ADR_OFFSET 0
|
|
+
|
|
+/* Fields of "I2C Bus Status Register" */
|
|
+/** Read / not Write */
|
|
+#define I2C_BUS_STAT_RNW 0x00000004
|
|
+/* Write to I2C Bus.
|
|
+#define I2C_BUS_STAT_RNW_WRITE 0x00000000 */
|
|
+/** Read from I2C Bus. */
|
|
+#define I2C_BUS_STAT_RNW_READ 0x00000004
|
|
+/** Bus Status */
|
|
+#define I2C_BUS_STAT_BS_MASK 0x00000003
|
|
+/** field offset */
|
|
+#define I2C_BUS_STAT_BS_OFFSET 0
|
|
+/** I2C Bus is free. */
|
|
+#define I2C_BUS_STAT_BS_FREE 0x00000000
|
|
+/** A start condition has been detected on the bus (bus busy). */
|
|
+#define I2C_BUS_STAT_BS_SC 0x00000001
|
|
+/** The device is working as master and has claimed the control on the I2C-bus (busy master). */
|
|
+#define I2C_BUS_STAT_BS_BM 0x00000002
|
|
+/** A remote master has accessed this device as slave. */
|
|
+#define I2C_BUS_STAT_BS_RM 0x00000003
|
|
+
|
|
+/* Fields of "I2C FIFO Configuration Register" */
|
|
+/** TX FIFO Flow Control */
|
|
+#define I2C_FIFO_CFG_TXFC 0x00020000
|
|
+/* TX FIFO not as Flow Controller
|
|
+#define I2C_FIFO_CFG_TXFC_TXNFC 0x00000000 */
|
|
+/** RX FIFO Flow Control */
|
|
+#define I2C_FIFO_CFG_RXFC 0x00010000
|
|
+/* RX FIFO not as Flow Controller
|
|
+#define I2C_FIFO_CFG_RXFC_RXNFC 0x00000000 */
|
|
+/** The reset value depends on the used character sizes of the peripheral. The maximum selectable alignment depends on the maximum number of characters per stage. */
|
|
+#define I2C_FIFO_CFG_TXFA_MASK 0x00003000
|
|
+/** field offset */
|
|
+#define I2C_FIFO_CFG_TXFA_OFFSET 12
|
|
+/** Byte aligned (character alignment) */
|
|
+#define I2C_FIFO_CFG_TXFA_TXFA0 0x00000000
|
|
+/** Half word aligned (character alignment of two characters) */
|
|
+#define I2C_FIFO_CFG_TXFA_TXFA1 0x00001000
|
|
+/** Word aligned (character alignment of four characters) */
|
|
+#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000
|
|
+/** Double word aligned (character alignment of eight */
|
|
+#define I2C_FIFO_CFG_TXFA_TXFA3 0x00003000
|
|
+/** The reset value depends on the used character sizes of the peripheral. The maximum selectable alignment depends on the maximum number of characters per stage. */
|
|
+#define I2C_FIFO_CFG_RXFA_MASK 0x00000300
|
|
+/** field offset */
|
|
+#define I2C_FIFO_CFG_RXFA_OFFSET 8
|
|
+/** Byte aligned (character alignment) */
|
|
+#define I2C_FIFO_CFG_RXFA_RXFA0 0x00000000
|
|
+/** Half word aligned (character alignment of two characters) */
|
|
+#define I2C_FIFO_CFG_RXFA_RXFA1 0x00000100
|
|
+/** Word aligned (character alignment of four characters) */
|
|
+#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200
|
|
+/** Double word aligned (character alignment of eight */
|
|
+#define I2C_FIFO_CFG_RXFA_RXFA3 0x00000300
|
|
+/** DMA controller does not support a burst size of 2 words. The reset value is the half of the FIFO size. The maximum selectable burst size is smaller than the FIFO size. */
|
|
+#define I2C_FIFO_CFG_TXBS_MASK 0x00000030
|
|
+/** field offset */
|
|
+#define I2C_FIFO_CFG_TXBS_OFFSET 4
|
|
+/** 1 word */
|
|
+#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000
|
|
+/** 2 words */
|
|
+#define I2C_FIFO_CFG_TXBS_TXBS1 0x00000010
|
|
+/** 4 words */
|
|
+#define I2C_FIFO_CFG_TXBS_TXBS2 0x00000020
|
|
+/** 8 words */
|
|
+#define I2C_FIFO_CFG_TXBS_TXBS3 0x00000030
|
|
+/** DMA controller does not support a burst size of 2 words. The reset value is the half of the FIFO size. The maximum selectable burst size is smaller than the FIFO size. */
|
|
+#define I2C_FIFO_CFG_RXBS_MASK 0x00000003
|
|
+/** field offset */
|
|
+#define I2C_FIFO_CFG_RXBS_OFFSET 0
|
|
+/** 1 word */
|
|
+#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000
|
|
+/** 2 words */
|
|
+#define I2C_FIFO_CFG_RXBS_RXBS1 0x00000001
|
|
+/** 4 words */
|
|
+#define I2C_FIFO_CFG_RXBS_RXBS2 0x00000002
|
|
+/** 8 words */
|
|
+#define I2C_FIFO_CFG_RXBS_RXBS3 0x00000003
|
|
+
|
|
+/* Fields of "I2C Maximum Received Packet Size Register" */
|
|
+/** MRPS */
|
|
+#define I2C_MRPS_CTRL_MRPS_MASK 0x00003FFF
|
|
+/** field offset */
|
|
+#define I2C_MRPS_CTRL_MRPS_OFFSET 0
|
|
+
|
|
+/* Fields of "I2C Received Packet Size Status Register" */
|
|
+/** RPS */
|
|
+#define I2C_RPS_STAT_RPS_MASK 0x00003FFF
|
|
+/** field offset */
|
|
+#define I2C_RPS_STAT_RPS_OFFSET 0
|
|
+
|
|
+/* Fields of "I2C Transmit Packet Size Register" */
|
|
+/** TPS */
|
|
+#define I2C_TPS_CTRL_TPS_MASK 0x00003FFF
|
|
+/** field offset */
|
|
+#define I2C_TPS_CTRL_TPS_OFFSET 0
|
|
+
|
|
+/* Fields of "I2C Filled FIFO Stages Status Register" */
|
|
+/** FFS */
|
|
+#define I2C_FFS_STAT_FFS_MASK 0x0000000F
|
|
+/** field offset */
|
|
+#define I2C_FFS_STAT_FFS_OFFSET 0
|
|
+
|
|
+/* Fields of "I2C Timing Configuration Register" */
|
|
+/** SDA Delay Stages for Start/Stop bit in High Speed Mode
|
|
+ The actual delay is calculated as the value of this field + 3 */
|
|
+#define I2C_TIM_CFG_HS_SDA_DEL_MASK 0x00070000
|
|
+/** field offset */
|
|
+#define I2C_TIM_CFG_HS_SDA_DEL_OFFSET 16
|
|
+/** Enable Fast Mode SCL Low period timing */
|
|
+#define I2C_TIM_CFG_FS_SCL_LOW 0x00008000
|
|
+/* Disable
|
|
+#define I2C_TIM_CFG_FS_SCL_LOW_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_TIM_CFG_FS_SCL_LOW_EN 0x00008000
|
|
+/** SCL Delay Stages for Hold Time Start (Restart) Bit.
|
|
+ The actual delay is calculated as the value of this field + 2 */
|
|
+#define I2C_TIM_CFG_SCL_DEL_HD_STA_MASK 0x00000E00
|
|
+/** field offset */
|
|
+#define I2C_TIM_CFG_SCL_DEL_HD_STA_OFFSET 9
|
|
+/** SDA Delay Stages for Start/Stop bit in High Speed Mode
|
|
+ The actual delay is calculated as the value of this field + 3 */
|
|
+#define I2C_TIM_CFG_HS_SDA_DEL_HD_DAT_MASK 0x000001C0
|
|
+/** field offset */
|
|
+#define I2C_TIM_CFG_HS_SDA_DEL_HD_DAT_OFFSET 6
|
|
+/** SDA Delay Stages for Start/Stop bit in High Speed Mode
|
|
+ The actual delay is calculated as the value of this field + 3 */
|
|
+#define I2C_TIM_CFG_SDA_DEL_HD_DAT_MASK 0x0000003F
|
|
+/** field offset */
|
|
+#define I2C_TIM_CFG_SDA_DEL_HD_DAT_OFFSET 0
|
|
+
|
|
+/* Fields of "I2C Error Interrupt Request Source Mask Register" */
|
|
+/** Enables the corresponding error interrupt. */
|
|
+#define I2C_ERR_IRQSM_TXF_OFL 0x00000008
|
|
+/* Disable
|
|
+#define I2C_ERR_IRQSM_TXF_OFL_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_ERR_IRQSM_TXF_OFL_EN 0x00000008
|
|
+/** Enables the corresponding error interrupt. */
|
|
+#define I2C_ERR_IRQSM_TXF_UFL 0x00000004
|
|
+/* Disable
|
|
+#define I2C_ERR_IRQSM_TXF_UFL_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_ERR_IRQSM_TXF_UFL_EN 0x00000004
|
|
+/** Enables the corresponding error interrupt. */
|
|
+#define I2C_ERR_IRQSM_RXF_OFL 0x00000002
|
|
+/* Disable
|
|
+#define I2C_ERR_IRQSM_RXF_OFL_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_ERR_IRQSM_RXF_OFL_EN 0x00000002
|
|
+/** Enables the corresponding error interrupt. */
|
|
+#define I2C_ERR_IRQSM_RXF_UFL 0x00000001
|
|
+/* Disable
|
|
+#define I2C_ERR_IRQSM_RXF_UFL_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_ERR_IRQSM_RXF_UFL_EN 0x00000001
|
|
+
|
|
+/* Fields of "I2C Error Interrupt Request Source Status Register" */
|
|
+/** TXF_OFL */
|
|
+#define I2C_ERR_IRQSS_TXF_OFL 0x00000008
|
|
+/* Nothing
|
|
+#define I2C_ERR_IRQSS_TXF_OFL_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_ERR_IRQSS_TXF_OFL_INTOCC 0x00000008
|
|
+/** TXF_UFL */
|
|
+#define I2C_ERR_IRQSS_TXF_UFL 0x00000004
|
|
+/* Nothing
|
|
+#define I2C_ERR_IRQSS_TXF_UFL_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_ERR_IRQSS_TXF_UFL_INTOCC 0x00000004
|
|
+/** RXF_OFL */
|
|
+#define I2C_ERR_IRQSS_RXF_OFL 0x00000002
|
|
+/* Nothing
|
|
+#define I2C_ERR_IRQSS_RXF_OFL_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_ERR_IRQSS_RXF_OFL_INTOCC 0x00000002
|
|
+/** RXF_UFL */
|
|
+#define I2C_ERR_IRQSS_RXF_UFL 0x00000001
|
|
+/* Nothing
|
|
+#define I2C_ERR_IRQSS_RXF_UFL_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_ERR_IRQSS_RXF_UFL_INTOCC 0x00000001
|
|
+
|
|
+/* Fields of "I2C Error Interrupt Request Source Clear Register" */
|
|
+/** TXF_OFL */
|
|
+#define I2C_ERR_IRQSC_TXF_OFL 0x00000008
|
|
+/* No-Operation
|
|
+#define I2C_ERR_IRQSC_TXF_OFL_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define I2C_ERR_IRQSC_TXF_OFL_CLR 0x00000008
|
|
+/** TXF_UFL */
|
|
+#define I2C_ERR_IRQSC_TXF_UFL 0x00000004
|
|
+/* No-Operation
|
|
+#define I2C_ERR_IRQSC_TXF_UFL_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define I2C_ERR_IRQSC_TXF_UFL_CLR 0x00000004
|
|
+/** RXF_OFL */
|
|
+#define I2C_ERR_IRQSC_RXF_OFL 0x00000002
|
|
+/* No-Operation
|
|
+#define I2C_ERR_IRQSC_RXF_OFL_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define I2C_ERR_IRQSC_RXF_OFL_CLR 0x00000002
|
|
+/** RXF_UFL */
|
|
+#define I2C_ERR_IRQSC_RXF_UFL 0x00000001
|
|
+/* No-Operation
|
|
+#define I2C_ERR_IRQSC_RXF_UFL_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define I2C_ERR_IRQSC_RXF_UFL_CLR 0x00000001
|
|
+
|
|
+/* Fields of "I2C Protocol Interrupt Request Source Mask Register" */
|
|
+/** Enables the corresponding interrupt. */
|
|
+#define I2C_P_IRQSM_RX 0x00000040
|
|
+/* Disable
|
|
+#define I2C_P_IRQSM_RX_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_P_IRQSM_RX_EN 0x00000040
|
|
+/** Enables the corresponding interrupt. */
|
|
+#define I2C_P_IRQSM_TX_END 0x00000020
|
|
+/* Disable
|
|
+#define I2C_P_IRQSM_TX_END_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_P_IRQSM_TX_END_EN 0x00000020
|
|
+/** Enables the corresponding interrupt. */
|
|
+#define I2C_P_IRQSM_NACK 0x00000010
|
|
+/* Disable
|
|
+#define I2C_P_IRQSM_NACK_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_P_IRQSM_NACK_EN 0x00000010
|
|
+/** Enables the corresponding interrupt. */
|
|
+#define I2C_P_IRQSM_AL 0x00000008
|
|
+/* Disable
|
|
+#define I2C_P_IRQSM_AL_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_P_IRQSM_AL_EN 0x00000008
|
|
+/** Enables the corresponding interrupt. */
|
|
+#define I2C_P_IRQSM_MC 0x00000004
|
|
+/* Disable
|
|
+#define I2C_P_IRQSM_MC_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_P_IRQSM_MC_EN 0x00000004
|
|
+/** Enables the corresponding interrupt. */
|
|
+#define I2C_P_IRQSM_GC 0x00000002
|
|
+/* Disable
|
|
+#define I2C_P_IRQSM_GC_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_P_IRQSM_GC_EN 0x00000002
|
|
+/** Enables the corresponding interrupt. */
|
|
+#define I2C_P_IRQSM_AM 0x00000001
|
|
+/* Disable
|
|
+#define I2C_P_IRQSM_AM_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_P_IRQSM_AM_EN 0x00000001
|
|
+
|
|
+/* Fields of "I2C Protocol Interrupt Request Source Status Register" */
|
|
+/** RX */
|
|
+#define I2C_P_IRQSS_RX 0x00000040
|
|
+/* Nothing
|
|
+#define I2C_P_IRQSS_RX_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_P_IRQSS_RX_INTOCC 0x00000040
|
|
+/** TX_END */
|
|
+#define I2C_P_IRQSS_TX_END 0x00000020
|
|
+/* Nothing
|
|
+#define I2C_P_IRQSS_TX_END_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_P_IRQSS_TX_END_INTOCC 0x00000020
|
|
+/** NACK */
|
|
+#define I2C_P_IRQSS_NACK 0x00000010
|
|
+/* Nothing
|
|
+#define I2C_P_IRQSS_NACK_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_P_IRQSS_NACK_INTOCC 0x00000010
|
|
+/** AL */
|
|
+#define I2C_P_IRQSS_AL 0x00000008
|
|
+/* Nothing
|
|
+#define I2C_P_IRQSS_AL_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_P_IRQSS_AL_INTOCC 0x00000008
|
|
+/** MC */
|
|
+#define I2C_P_IRQSS_MC 0x00000004
|
|
+/* Nothing
|
|
+#define I2C_P_IRQSS_MC_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_P_IRQSS_MC_INTOCC 0x00000004
|
|
+/** GC */
|
|
+#define I2C_P_IRQSS_GC 0x00000002
|
|
+/* Nothing
|
|
+#define I2C_P_IRQSS_GC_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_P_IRQSS_GC_INTOCC 0x00000002
|
|
+/** AM */
|
|
+#define I2C_P_IRQSS_AM 0x00000001
|
|
+/* Nothing
|
|
+#define I2C_P_IRQSS_AM_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_P_IRQSS_AM_INTOCC 0x00000001
|
|
+
|
|
+/* Fields of "I2C Protocol Interrupt Request Source Clear Register" */
|
|
+/** RX */
|
|
+#define I2C_P_IRQSC_RX 0x00000040
|
|
+/* No-Operation
|
|
+#define I2C_P_IRQSC_RX_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define I2C_P_IRQSC_RX_CLR 0x00000040
|
|
+/** TX_END */
|
|
+#define I2C_P_IRQSC_TX_END 0x00000020
|
|
+/* No-Operation
|
|
+#define I2C_P_IRQSC_TX_END_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define I2C_P_IRQSC_TX_END_CLR 0x00000020
|
|
+/** NACK */
|
|
+#define I2C_P_IRQSC_NACK 0x00000010
|
|
+/* No-Operation
|
|
+#define I2C_P_IRQSC_NACK_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define I2C_P_IRQSC_NACK_CLR 0x00000010
|
|
+/** AL */
|
|
+#define I2C_P_IRQSC_AL 0x00000008
|
|
+/* No-Operation
|
|
+#define I2C_P_IRQSC_AL_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define I2C_P_IRQSC_AL_CLR 0x00000008
|
|
+/** MC */
|
|
+#define I2C_P_IRQSC_MC 0x00000004
|
|
+/* No-Operation
|
|
+#define I2C_P_IRQSC_MC_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define I2C_P_IRQSC_MC_CLR 0x00000004
|
|
+/** GC */
|
|
+#define I2C_P_IRQSC_GC 0x00000002
|
|
+/* No-Operation
|
|
+#define I2C_P_IRQSC_GC_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define I2C_P_IRQSC_GC_CLR 0x00000002
|
|
+/** AM */
|
|
+#define I2C_P_IRQSC_AM 0x00000001
|
|
+/* No-Operation
|
|
+#define I2C_P_IRQSC_AM_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define I2C_P_IRQSC_AM_CLR 0x00000001
|
|
+
|
|
+/* Fields of "I2C Raw Interrupt Status Register" */
|
|
+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
|
|
+#define I2C_RIS_I2C_P_INT 0x00000020
|
|
+/* Nothing
|
|
+#define I2C_RIS_I2C_P_INT_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020
|
|
+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
|
|
+#define I2C_RIS_I2C_ERR_INT 0x00000010
|
|
+/* Nothing
|
|
+#define I2C_RIS_I2C_ERR_INT_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010
|
|
+/** BREQ_INT */
|
|
+#define I2C_RIS_BREQ_INT 0x00000008
|
|
+/* Nothing
|
|
+#define I2C_RIS_BREQ_INT_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_RIS_BREQ_INT_INTOCC 0x00000008
|
|
+/** LBREQ_INT */
|
|
+#define I2C_RIS_LBREQ_INT 0x00000004
|
|
+/* Nothing
|
|
+#define I2C_RIS_LBREQ_INT_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_RIS_LBREQ_INT_INTOCC 0x00000004
|
|
+/** SREQ_INT */
|
|
+#define I2C_RIS_SREQ_INT 0x00000002
|
|
+/* Nothing
|
|
+#define I2C_RIS_SREQ_INT_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_RIS_SREQ_INT_INTOCC 0x00000002
|
|
+/** LSREQ_INT */
|
|
+#define I2C_RIS_LSREQ_INT 0x00000001
|
|
+/* Nothing
|
|
+#define I2C_RIS_LSREQ_INT_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_RIS_LSREQ_INT_INTOCC 0x00000001
|
|
+
|
|
+/* Fields of "I2C Interrupt Mask Control Register" */
|
|
+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
|
|
+#define I2C_IMSC_I2C_P_INT 0x00000020
|
|
+/* Disable
|
|
+#define I2C_IMSC_I2C_P_INT_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_IMSC_I2C_P_INT_EN 0x00000020
|
|
+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
|
|
+#define I2C_IMSC_I2C_ERR_INT 0x00000010
|
|
+/* Disable
|
|
+#define I2C_IMSC_I2C_ERR_INT_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010
|
|
+/** BREQ_INT */
|
|
+#define I2C_IMSC_BREQ_INT 0x00000008
|
|
+/* Disable
|
|
+#define I2C_IMSC_BREQ_INT_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_IMSC_BREQ_INT_EN 0x00000008
|
|
+/** LBREQ_INT */
|
|
+#define I2C_IMSC_LBREQ_INT 0x00000004
|
|
+/* Disable
|
|
+#define I2C_IMSC_LBREQ_INT_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_IMSC_LBREQ_INT_EN 0x00000004
|
|
+/** SREQ_INT */
|
|
+#define I2C_IMSC_SREQ_INT 0x00000002
|
|
+/* Disable
|
|
+#define I2C_IMSC_SREQ_INT_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_IMSC_SREQ_INT_EN 0x00000002
|
|
+/** LSREQ_INT */
|
|
+#define I2C_IMSC_LSREQ_INT 0x00000001
|
|
+/* Disable
|
|
+#define I2C_IMSC_LSREQ_INT_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_IMSC_LSREQ_INT_EN 0x00000001
|
|
+
|
|
+/* Fields of "I2C Masked Interrupt Status Register" */
|
|
+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
|
|
+#define I2C_MIS_I2C_P_INT 0x00000020
|
|
+/* Nothing
|
|
+#define I2C_MIS_I2C_P_INT_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_MIS_I2C_P_INT_INTOCC 0x00000020
|
|
+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
|
|
+#define I2C_MIS_I2C_ERR_INT 0x00000010
|
|
+/* Nothing
|
|
+#define I2C_MIS_I2C_ERR_INT_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_MIS_I2C_ERR_INT_INTOCC 0x00000010
|
|
+/** BREQ_INT */
|
|
+#define I2C_MIS_BREQ_INT 0x00000008
|
|
+/* Nothing
|
|
+#define I2C_MIS_BREQ_INT_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_MIS_BREQ_INT_INTOCC 0x00000008
|
|
+/** LBREQ_INT */
|
|
+#define I2C_MIS_LBREQ_INT 0x00000004
|
|
+/* Nothing
|
|
+#define I2C_MIS_LBREQ_INT_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_MIS_LBREQ_INT_INTOCC 0x00000004
|
|
+/** SREQ_INT */
|
|
+#define I2C_MIS_SREQ_INT 0x00000002
|
|
+/* Nothing
|
|
+#define I2C_MIS_SREQ_INT_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_MIS_SREQ_INT_INTOCC 0x00000002
|
|
+/** LSREQ_INT */
|
|
+#define I2C_MIS_LSREQ_INT 0x00000001
|
|
+/* Nothing
|
|
+#define I2C_MIS_LSREQ_INT_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define I2C_MIS_LSREQ_INT_INTOCC 0x00000001
|
|
+
|
|
+/* Fields of "I2C Interrupt Clear Register" */
|
|
+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
|
|
+#define I2C_ICR_I2C_P_INT 0x00000020
|
|
+/* No-Operation
|
|
+#define I2C_ICR_I2C_P_INT_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define I2C_ICR_I2C_P_INT_CLR 0x00000020
|
|
+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
|
|
+#define I2C_ICR_I2C_ERR_INT 0x00000010
|
|
+/* No-Operation
|
|
+#define I2C_ICR_I2C_ERR_INT_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define I2C_ICR_I2C_ERR_INT_CLR 0x00000010
|
|
+/** BREQ_INT */
|
|
+#define I2C_ICR_BREQ_INT 0x00000008
|
|
+/* No-Operation
|
|
+#define I2C_ICR_BREQ_INT_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define I2C_ICR_BREQ_INT_CLR 0x00000008
|
|
+/** LBREQ_INT */
|
|
+#define I2C_ICR_LBREQ_INT 0x00000004
|
|
+/* No-Operation
|
|
+#define I2C_ICR_LBREQ_INT_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define I2C_ICR_LBREQ_INT_CLR 0x00000004
|
|
+/** SREQ_INT */
|
|
+#define I2C_ICR_SREQ_INT 0x00000002
|
|
+/* No-Operation
|
|
+#define I2C_ICR_SREQ_INT_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define I2C_ICR_SREQ_INT_CLR 0x00000002
|
|
+/** LSREQ_INT */
|
|
+#define I2C_ICR_LSREQ_INT 0x00000001
|
|
+/* No-Operation
|
|
+#define I2C_ICR_LSREQ_INT_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define I2C_ICR_LSREQ_INT_CLR 0x00000001
|
|
+
|
|
+/* Fields of "I2C Interrupt Set Register" */
|
|
+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */
|
|
+#define I2C_ISR_I2C_P_INT 0x00000020
|
|
+/* No-Operation
|
|
+#define I2C_ISR_I2C_P_INT_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define I2C_ISR_I2C_P_INT_SET 0x00000020
|
|
+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */
|
|
+#define I2C_ISR_I2C_ERR_INT 0x00000010
|
|
+/* No-Operation
|
|
+#define I2C_ISR_I2C_ERR_INT_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define I2C_ISR_I2C_ERR_INT_SET 0x00000010
|
|
+/** BREQ_INT */
|
|
+#define I2C_ISR_BREQ_INT 0x00000008
|
|
+/* No-Operation
|
|
+#define I2C_ISR_BREQ_INT_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define I2C_ISR_BREQ_INT_SET 0x00000008
|
|
+/** LBREQ_INT */
|
|
+#define I2C_ISR_LBREQ_INT 0x00000004
|
|
+/* No-Operation
|
|
+#define I2C_ISR_LBREQ_INT_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define I2C_ISR_LBREQ_INT_SET 0x00000004
|
|
+/** SREQ_INT */
|
|
+#define I2C_ISR_SREQ_INT 0x00000002
|
|
+/* No-Operation
|
|
+#define I2C_ISR_SREQ_INT_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define I2C_ISR_SREQ_INT_SET 0x00000002
|
|
+/** LSREQ_INT */
|
|
+#define I2C_ISR_LSREQ_INT 0x00000001
|
|
+/* No-Operation
|
|
+#define I2C_ISR_LSREQ_INT_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define I2C_ISR_LSREQ_INT_SET 0x00000001
|
|
+
|
|
+/* Fields of "I2C DMA Enable Register" */
|
|
+/** BREQ_INT */
|
|
+#define I2C_DMAE_BREQ_INT 0x00000008
|
|
+/* Disable
|
|
+#define I2C_DMAE_BREQ_INT_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_DMAE_BREQ_INT_EN 0x00000008
|
|
+/** LBREQ_INT */
|
|
+#define I2C_DMAE_LBREQ_INT 0x00000004
|
|
+/* Disable
|
|
+#define I2C_DMAE_LBREQ_INT_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_DMAE_LBREQ_INT_EN 0x00000004
|
|
+/** SREQ_INT */
|
|
+#define I2C_DMAE_SREQ_INT 0x00000002
|
|
+/* Disable
|
|
+#define I2C_DMAE_SREQ_INT_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_DMAE_SREQ_INT_EN 0x00000002
|
|
+/** LSREQ_INT */
|
|
+#define I2C_DMAE_LSREQ_INT 0x00000001
|
|
+/* Disable
|
|
+#define I2C_DMAE_LSREQ_INT_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define I2C_DMAE_LSREQ_INT_EN 0x00000001
|
|
+
|
|
+/* Fields of "I2C Transmit Data Register" */
|
|
+/** Characters to be transmitted */
|
|
+#define I2C_TXD_TXD_MASK 0xFFFFFFFF
|
|
+/** field offset */
|
|
+#define I2C_TXD_TXD_OFFSET 0
|
|
+
|
|
+/* Fields of "I2C Receive Data Register" */
|
|
+/** Received characters */
|
|
+#define I2C_RXD_RXD_MASK 0xFFFFFFFF
|
|
+/** field offset */
|
|
+#define I2C_RXD_RXD_OFFSET 0
|
|
+
|
|
+/*! @} */ /* I2C_REGISTER */
|
|
+
|
|
+#endif /* _i2c_reg_h */
|
|
--- /dev/null
|
|
+++ b/arch/mips/include/asm/mach-lantiq/falcon/icu0_reg.h
|
|
@@ -0,0 +1,4324 @@
|
|
+/******************************************************************************
|
|
+
|
|
+ Copyright (c) 2010
|
|
+ Lantiq Deutschland GmbH
|
|
+
|
|
+ For licensing information, see the file 'LICENSE' in the root folder of
|
|
+ this software module.
|
|
+
|
|
+******************************************************************************/
|
|
+
|
|
+#ifndef _icu0_reg_h
|
|
+#define _icu0_reg_h
|
|
+
|
|
+/** \addtogroup ICU0_REGISTER
|
|
+ @{
|
|
+*/
|
|
+/* access macros */
|
|
+#define icu0_r32(reg) reg_r32(&icu0->reg)
|
|
+#define icu0_w32(val, reg) reg_w32(val, &icu0->reg)
|
|
+#define icu0_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &icu0->reg)
|
|
+#define icu0_r32_table(reg, idx) reg_r32_table(icu0->reg, idx)
|
|
+#define icu0_w32_table(val, reg, idx) reg_w32_table(val, icu0->reg, idx)
|
|
+#define icu0_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, icu0->reg, idx)
|
|
+#define icu0_adr_table(reg, idx) adr_table(icu0->reg, idx)
|
|
+
|
|
+
|
|
+/** ICU0 register structure */
|
|
+struct gpon_reg_icu0
|
|
+{
|
|
+ /** IM0 Interrupt Status Register
|
|
+ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
|
|
+ unsigned int im0_isr; /* 0x00000000 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_0; /* 0x00000004 */
|
|
+ /** IM0 Interrupt Enable Register
|
|
+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM0_IOSR register and are not signalled via the interrupt line towards the controller. */
|
|
+ unsigned int im0_ier; /* 0x00000008 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_1; /* 0x0000000C */
|
|
+ /** IM0 Interrupt Output Status Register
|
|
+ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM0_IER register. */
|
|
+ unsigned int im0_iosr; /* 0x00000010 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_2; /* 0x00000014 */
|
|
+ /** IM0 Interrupt Request Set Register
|
|
+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
|
|
+ unsigned int im0_irsr; /* 0x00000018 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_3; /* 0x0000001C */
|
|
+ /** IM0 Interrupt Mode Register
|
|
+ This register shows the type of interrupt for each bit. */
|
|
+ unsigned int im0_imr; /* 0x00000020 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_4; /* 0x00000024 */
|
|
+ /** IM1 Interrupt Status Register
|
|
+ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
|
|
+ unsigned int im1_isr; /* 0x00000028 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_5; /* 0x0000002C */
|
|
+ /** IM1 Interrupt Enable Register
|
|
+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM1_IOSR register and are not signalled via the interrupt line towards the controller. */
|
|
+ unsigned int im1_ier; /* 0x00000030 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_6; /* 0x00000034 */
|
|
+ /** IM1 Interrupt Output Status Register
|
|
+ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM1_IER register. */
|
|
+ unsigned int im1_iosr; /* 0x00000038 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_7; /* 0x0000003C */
|
|
+ /** IM1 Interrupt Request Set Register
|
|
+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
|
|
+ unsigned int im1_irsr; /* 0x00000040 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_8; /* 0x00000044 */
|
|
+ /** IM1 Interrupt Mode Register
|
|
+ This register shows the type of interrupt for each bit. */
|
|
+ unsigned int im1_imr; /* 0x00000048 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_9; /* 0x0000004C */
|
|
+ /** IM2 Interrupt Status Register
|
|
+ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
|
|
+ unsigned int im2_isr; /* 0x00000050 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_10; /* 0x00000054 */
|
|
+ /** IM2 Interrupt Enable Register
|
|
+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM2_IOSR register and are not signalled via the interrupt line towards the controller. */
|
|
+ unsigned int im2_ier; /* 0x00000058 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_11; /* 0x0000005C */
|
|
+ /** IM2 Interrupt Output Status Register
|
|
+ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM2_IER register. */
|
|
+ unsigned int im2_iosr; /* 0x00000060 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_12; /* 0x00000064 */
|
|
+ /** IM2 Interrupt Request Set Register
|
|
+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
|
|
+ unsigned int im2_irsr; /* 0x00000068 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_13; /* 0x0000006C */
|
|
+ /** IM2 Interrupt Mode Register
|
|
+ This register shows the type of interrupt for each bit. */
|
|
+ unsigned int im2_imr; /* 0x00000070 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_14; /* 0x00000074 */
|
|
+ /** IM3 Interrupt Status Register
|
|
+ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
|
|
+ unsigned int im3_isr; /* 0x00000078 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_15; /* 0x0000007C */
|
|
+ /** IM3 Interrupt Enable Register
|
|
+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM3_IOSR register and are not signalled via the interrupt line towards the controller. */
|
|
+ unsigned int im3_ier; /* 0x00000080 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_16; /* 0x00000084 */
|
|
+ /** IM3 Interrupt Output Status Register
|
|
+ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM3_IER register. */
|
|
+ unsigned int im3_iosr; /* 0x00000088 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_17; /* 0x0000008C */
|
|
+ /** IM3 Interrupt Request Set Register
|
|
+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
|
|
+ unsigned int im3_irsr; /* 0x00000090 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_18; /* 0x00000094 */
|
|
+ /** IM3 Interrupt Mode Register
|
|
+ This register shows the type of interrupt for each bit. */
|
|
+ unsigned int im3_imr; /* 0x00000098 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_19; /* 0x0000009C */
|
|
+ /** IM4 Interrupt Status Register
|
|
+ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */
|
|
+ unsigned int im4_isr; /* 0x000000A0 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_20; /* 0x000000A4 */
|
|
+ /** IM4 Interrupt Enable Register
|
|
+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM4_IOSR register and are not signalled via the interrupt line towards the controller. */
|
|
+ unsigned int im4_ier; /* 0x000000A8 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_21; /* 0x000000AC */
|
|
+ /** IM4 Interrupt Output Status Register
|
|
+ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM4_IER register. */
|
|
+ unsigned int im4_iosr; /* 0x000000B0 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_22; /* 0x000000B4 */
|
|
+ /** IM4 Interrupt Request Set Register
|
|
+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
|
|
+ unsigned int im4_irsr; /* 0x000000B8 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_23; /* 0x000000BC */
|
|
+ /** IM4 Interrupt Mode Register
|
|
+ This register shows the type of interrupt for each bit. */
|
|
+ unsigned int im4_imr; /* 0x000000C0 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_24; /* 0x000000C4 */
|
|
+ /** ICU Interrupt Vector Register (5 bit variant)
|
|
+ Shows the leftmost pending interrupt request. If e.g. bit 14 of the IOSR register is set, 15 is reported, because the 15th interrupt request is active. */
|
|
+ unsigned int icu_ivec; /* 0x000000C8 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_25; /* 0x000000CC */
|
|
+ /** ICU Interrupt Vector Register (6 bit variant)
|
|
+ Shows the leftmost pending interrupt request. If e.g. bit 14 of the IOSR register is set, 15 is reported, because the 15th interrupt request is active. */
|
|
+ unsigned int icu_ivec_6; /* 0x000000D0 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_26[3]; /* 0x000000D4 */
|
|
+};
|
|
+
|
|
+
|
|
+/* Fields of "IM0 Interrupt Status Register" */
|
|
+/** PCM Transmit Crash Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM0_ISR_PCM_HW2_CRASH 0x80000000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_PCM_HW2_CRASH_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_PCM_HW2_CRASH_INTACK 0x80000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_PCM_HW2_CRASH_INTOCC 0x80000000
|
|
+/** PCM Transmit Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM0_ISR_PCM_TX 0x40000000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_PCM_TX_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_PCM_TX_INTACK 0x40000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_PCM_TX_INTOCC 0x40000000
|
|
+/** PCM Receive Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM0_ISR_PCM_RX 0x20000000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_PCM_RX_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_PCM_RX_INTACK 0x20000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_PCM_RX_INTOCC 0x20000000
|
|
+/** Secure Hash Algorithm Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM0_ISR_SHA1_HASH 0x10000000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_SHA1_HASH_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_SHA1_HASH_INTACK 0x10000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_SHA1_HASH_INTOCC 0x10000000
|
|
+/** Advanced Encryption Standard Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM0_ISR_AES_AES 0x08000000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_AES_AES_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_AES_AES_INTACK 0x08000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_AES_AES_INTOCC 0x08000000
|
|
+/** SSC Frame Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM0_ISR_SSC0_F 0x00020000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_SSC0_F_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_SSC0_F_INTACK 0x00020000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_SSC0_F_INTOCC 0x00020000
|
|
+/** SSC Error Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM0_ISR_SSC0_E 0x00010000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_SSC0_E_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_SSC0_E_INTACK 0x00010000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_SSC0_E_INTOCC 0x00010000
|
|
+/** SSC Receive Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM0_ISR_SSC0_R 0x00008000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_SSC0_R_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_SSC0_R_INTACK 0x00008000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_SSC0_R_INTOCC 0x00008000
|
|
+/** SSC Transmit Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM0_ISR_SSC0_T 0x00004000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_SSC0_T_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_SSC0_T_INTACK 0x00004000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_SSC0_T_INTOCC 0x00004000
|
|
+/** I2C Peripheral Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM0_ISR_I2C_I2C_P_INT 0x00002000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_I2C_I2C_P_INT_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_I2C_I2C_P_INT_INTACK 0x00002000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_I2C_I2C_P_INT_INTOCC 0x00002000
|
|
+/** I2C Error Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM0_ISR_I2C_I2C_ERR_INT 0x00001000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_INTACK 0x00001000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_INTOCC 0x00001000
|
|
+/** I2C Burst Data Transfer Request
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM0_ISR_I2C_BREQ_INT 0x00000800
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_I2C_BREQ_INT_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_I2C_BREQ_INT_INTACK 0x00000800
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_I2C_BREQ_INT_INTOCC 0x00000800
|
|
+/** I2C Last Burst Data Transfer Request
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM0_ISR_I2C_LBREQ_INT 0x00000400
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_I2C_LBREQ_INT_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_I2C_LBREQ_INT_INTACK 0x00000400
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_I2C_LBREQ_INT_INTOCC 0x00000400
|
|
+/** I2C Single Data Transfer Request
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM0_ISR_I2C_SREQ_INT 0x00000200
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_I2C_SREQ_INT_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_I2C_SREQ_INT_INTACK 0x00000200
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_I2C_SREQ_INT_INTOCC 0x00000200
|
|
+/** I2C Last Single Data Transfer Request
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM0_ISR_I2C_LSREQ_INT 0x00000100
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_I2C_LSREQ_INT_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_I2C_LSREQ_INT_INTACK 0x00000100
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_I2C_LSREQ_INT_INTOCC 0x00000100
|
|
+/** HOST IF Mailbox1 Transmit Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM0_ISR_HOST_MB1_TIR 0x00000010
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_HOST_MB1_TIR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_HOST_MB1_TIR_INTACK 0x00000010
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_HOST_MB1_TIR_INTOCC 0x00000010
|
|
+/** HOST IF Mailbox1 Receive Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM0_ISR_HOST_MB1_RIR 0x00000008
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_HOST_MB1_RIR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_HOST_MB1_RIR_INTACK 0x00000008
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_HOST_MB1_RIR_INTOCC 0x00000008
|
|
+/** HOST IF Mailbox0 Transmit Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM0_ISR_HOST_MB0_TIR 0x00000004
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_HOST_MB0_TIR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_HOST_MB0_TIR_INTACK 0x00000004
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_HOST_MB0_TIR_INTOCC 0x00000004
|
|
+/** HOST IF Mailbox0 Receive Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM0_ISR_HOST_MB0_RIR 0x00000002
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_HOST_MB0_RIR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_HOST_MB0_RIR_INTACK 0x00000002
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_HOST_MB0_RIR_INTOCC 0x00000002
|
|
+/** HOST IF Event Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM0_ISR_HOST_EIR 0x00000001
|
|
+/* Nothing
|
|
+#define ICU0_IM0_ISR_HOST_EIR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM0_ISR_HOST_EIR_INTACK 0x00000001
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_ISR_HOST_EIR_INTOCC 0x00000001
|
|
+
|
|
+/* Fields of "IM0 Interrupt Enable Register" */
|
|
+/** PCM Transmit Crash Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_PCM_HW2_CRASH 0x80000000
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_PCM_HW2_CRASH_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_PCM_HW2_CRASH_EN 0x80000000
|
|
+/** PCM Transmit Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_PCM_TX 0x40000000
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_PCM_TX_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_PCM_TX_EN 0x40000000
|
|
+/** PCM Receive Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_PCM_RX 0x20000000
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_PCM_RX_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_PCM_RX_EN 0x20000000
|
|
+/** Secure Hash Algorithm Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_SHA1_HASH 0x10000000
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_SHA1_HASH_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_SHA1_HASH_EN 0x10000000
|
|
+/** Advanced Encryption Standard Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_AES_AES 0x08000000
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_AES_AES_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_AES_AES_EN 0x08000000
|
|
+/** SSC Frame Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_SSC0_F 0x00020000
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_SSC0_F_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_SSC0_F_EN 0x00020000
|
|
+/** SSC Error Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_SSC0_E 0x00010000
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_SSC0_E_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_SSC0_E_EN 0x00010000
|
|
+/** SSC Receive Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_SSC0_R 0x00008000
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_SSC0_R_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_SSC0_R_EN 0x00008000
|
|
+/** SSC Transmit Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_SSC0_T 0x00004000
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_SSC0_T_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_SSC0_T_EN 0x00004000
|
|
+/** I2C Peripheral Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_I2C_I2C_P_INT 0x00002000
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_I2C_I2C_P_INT_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_I2C_I2C_P_INT_EN 0x00002000
|
|
+/** I2C Error Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_I2C_I2C_ERR_INT 0x00001000
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_I2C_I2C_ERR_INT_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_I2C_I2C_ERR_INT_EN 0x00001000
|
|
+/** I2C Burst Data Transfer Request
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_I2C_BREQ_INT 0x00000800
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_I2C_BREQ_INT_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_I2C_BREQ_INT_EN 0x00000800
|
|
+/** I2C Last Burst Data Transfer Request
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_I2C_LBREQ_INT 0x00000400
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_I2C_LBREQ_INT_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_I2C_LBREQ_INT_EN 0x00000400
|
|
+/** I2C Single Data Transfer Request
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_I2C_SREQ_INT 0x00000200
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_I2C_SREQ_INT_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_I2C_SREQ_INT_EN 0x00000200
|
|
+/** I2C Last Single Data Transfer Request
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_I2C_LSREQ_INT 0x00000100
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_I2C_LSREQ_INT_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_I2C_LSREQ_INT_EN 0x00000100
|
|
+/** HOST IF Mailbox1 Transmit Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_HOST_MB1_TIR 0x00000010
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_HOST_MB1_TIR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_HOST_MB1_TIR_EN 0x00000010
|
|
+/** HOST IF Mailbox1 Receive Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_HOST_MB1_RIR 0x00000008
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_HOST_MB1_RIR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_HOST_MB1_RIR_EN 0x00000008
|
|
+/** HOST IF Mailbox0 Transmit Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_HOST_MB0_TIR 0x00000004
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_HOST_MB0_TIR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_HOST_MB0_TIR_EN 0x00000004
|
|
+/** HOST IF Mailbox0 Receive Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_HOST_MB0_RIR 0x00000002
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_HOST_MB0_RIR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_HOST_MB0_RIR_EN 0x00000002
|
|
+/** HOST IF Event Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IER_HOST_EIR 0x00000001
|
|
+/* Disable
|
|
+#define ICU0_IM0_IER_HOST_EIR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM0_IER_HOST_EIR_EN 0x00000001
|
|
+
|
|
+/* Fields of "IM0 Interrupt Output Status Register" */
|
|
+/** PCM Transmit Crash Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_PCM_HW2_CRASH 0x80000000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_PCM_HW2_CRASH_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_PCM_HW2_CRASH_INTOCC 0x80000000
|
|
+/** PCM Transmit Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_PCM_TX 0x40000000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_PCM_TX_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_PCM_TX_INTOCC 0x40000000
|
|
+/** PCM Receive Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_PCM_RX 0x20000000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_PCM_RX_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_PCM_RX_INTOCC 0x20000000
|
|
+/** Secure Hash Algorithm Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_SHA1_HASH 0x10000000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_SHA1_HASH_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_SHA1_HASH_INTOCC 0x10000000
|
|
+/** Advanced Encryption Standard Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_AES_AES 0x08000000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_AES_AES_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_AES_AES_INTOCC 0x08000000
|
|
+/** SSC Frame Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_SSC0_F 0x00020000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_SSC0_F_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_SSC0_F_INTOCC 0x00020000
|
|
+/** SSC Error Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_SSC0_E 0x00010000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_SSC0_E_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_SSC0_E_INTOCC 0x00010000
|
|
+/** SSC Receive Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_SSC0_R 0x00008000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_SSC0_R_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_SSC0_R_INTOCC 0x00008000
|
|
+/** SSC Transmit Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_SSC0_T 0x00004000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_SSC0_T_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_SSC0_T_INTOCC 0x00004000
|
|
+/** I2C Peripheral Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_I2C_I2C_P_INT 0x00002000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_I2C_I2C_P_INT_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_I2C_I2C_P_INT_INTOCC 0x00002000
|
|
+/** I2C Error Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT 0x00001000
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT_INTOCC 0x00001000
|
|
+/** I2C Burst Data Transfer Request
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_I2C_BREQ_INT 0x00000800
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_I2C_BREQ_INT_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_I2C_BREQ_INT_INTOCC 0x00000800
|
|
+/** I2C Last Burst Data Transfer Request
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_I2C_LBREQ_INT 0x00000400
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_I2C_LBREQ_INT_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_I2C_LBREQ_INT_INTOCC 0x00000400
|
|
+/** I2C Single Data Transfer Request
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_I2C_SREQ_INT 0x00000200
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_I2C_SREQ_INT_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_I2C_SREQ_INT_INTOCC 0x00000200
|
|
+/** I2C Last Single Data Transfer Request
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_I2C_LSREQ_INT 0x00000100
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_I2C_LSREQ_INT_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_I2C_LSREQ_INT_INTOCC 0x00000100
|
|
+/** HOST IF Mailbox1 Transmit Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_HOST_MB1_TIR 0x00000010
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_HOST_MB1_TIR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_HOST_MB1_TIR_INTOCC 0x00000010
|
|
+/** HOST IF Mailbox1 Receive Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_HOST_MB1_RIR 0x00000008
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_HOST_MB1_RIR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_HOST_MB1_RIR_INTOCC 0x00000008
|
|
+/** HOST IF Mailbox0 Transmit Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_HOST_MB0_TIR 0x00000004
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_HOST_MB0_TIR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_HOST_MB0_TIR_INTOCC 0x00000004
|
|
+/** HOST IF Mailbox0 Receive Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_HOST_MB0_RIR 0x00000002
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_HOST_MB0_RIR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_HOST_MB0_RIR_INTOCC 0x00000002
|
|
+/** HOST IF Event Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IOSR_HOST_EIR 0x00000001
|
|
+/* Nothing
|
|
+#define ICU0_IM0_IOSR_HOST_EIR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM0_IOSR_HOST_EIR_INTOCC 0x00000001
|
|
+
|
|
+/* Fields of "IM0 Interrupt Request Set Register" */
|
|
+/** PCM Transmit Crash Interrupt
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_PCM_HW2_CRASH 0x80000000
|
|
+/** PCM Transmit Interrupt
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_PCM_TX 0x40000000
|
|
+/** PCM Receive Interrupt
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_PCM_RX 0x20000000
|
|
+/** Secure Hash Algorithm Interrupt
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_SHA1_HASH 0x10000000
|
|
+/** Advanced Encryption Standard Interrupt
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_AES_AES 0x08000000
|
|
+/** SSC Frame Interrupt
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_SSC0_F 0x00020000
|
|
+/** SSC Error Interrupt
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_SSC0_E 0x00010000
|
|
+/** SSC Receive Interrupt
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_SSC0_R 0x00008000
|
|
+/** SSC Transmit Interrupt
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_SSC0_T 0x00004000
|
|
+/** I2C Peripheral Interrupt
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_I2C_I2C_P_INT 0x00002000
|
|
+/** I2C Error Interrupt
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_I2C_I2C_ERR_INT 0x00001000
|
|
+/** I2C Burst Data Transfer Request
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_I2C_BREQ_INT 0x00000800
|
|
+/** I2C Last Burst Data Transfer Request
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_I2C_LBREQ_INT 0x00000400
|
|
+/** I2C Single Data Transfer Request
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_I2C_SREQ_INT 0x00000200
|
|
+/** I2C Last Single Data Transfer Request
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_I2C_LSREQ_INT 0x00000100
|
|
+/** HOST IF Mailbox1 Transmit Interrupt
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_HOST_MB1_TIR 0x00000010
|
|
+/** HOST IF Mailbox1 Receive Interrupt
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_HOST_MB1_RIR 0x00000008
|
|
+/** HOST IF Mailbox0 Transmit Interrupt
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_HOST_MB0_TIR 0x00000004
|
|
+/** HOST IF Mailbox0 Receive Interrupt
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_HOST_MB0_RIR 0x00000002
|
|
+/** HOST IF Event Interrupt
|
|
+ Software control for the corresponding bit in the IM0_ISR register. */
|
|
+#define ICU0_IM0_IRSR_HOST_EIR 0x00000001
|
|
+
|
|
+/* Fields of "IM0 Interrupt Mode Register" */
|
|
+/** PCM Transmit Crash Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_PCM_HW2_CRASH 0x80000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_PCM_HW2_CRASH_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_PCM_HW2_CRASH_DIR 0x80000000
|
|
+/** PCM Transmit Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_PCM_TX 0x40000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_PCM_TX_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_PCM_TX_DIR 0x40000000
|
|
+/** PCM Receive Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_PCM_RX 0x20000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_PCM_RX_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_PCM_RX_DIR 0x20000000
|
|
+/** Secure Hash Algorithm Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_SHA1_HASH 0x10000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_SHA1_HASH_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_SHA1_HASH_DIR 0x10000000
|
|
+/** Advanced Encryption Standard Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_AES_AES 0x08000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_AES_AES_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_AES_AES_DIR 0x08000000
|
|
+/** SSC Frame Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_SSC0_F 0x00020000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_SSC0_F_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_SSC0_F_DIR 0x00020000
|
|
+/** SSC Error Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_SSC0_E 0x00010000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_SSC0_E_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_SSC0_E_DIR 0x00010000
|
|
+/** SSC Receive Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_SSC0_R 0x00008000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_SSC0_R_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_SSC0_R_DIR 0x00008000
|
|
+/** SSC Transmit Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_SSC0_T 0x00004000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_SSC0_T_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_SSC0_T_DIR 0x00004000
|
|
+/** I2C Peripheral Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_I2C_I2C_P_INT 0x00002000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_I2C_I2C_P_INT_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_I2C_I2C_P_INT_DIR 0x00002000
|
|
+/** I2C Error Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_I2C_I2C_ERR_INT 0x00001000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_I2C_I2C_ERR_INT_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_I2C_I2C_ERR_INT_DIR 0x00001000
|
|
+/** I2C Burst Data Transfer Request
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_I2C_BREQ_INT 0x00000800
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_I2C_BREQ_INT_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_I2C_BREQ_INT_DIR 0x00000800
|
|
+/** I2C Last Burst Data Transfer Request
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_I2C_LBREQ_INT 0x00000400
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_I2C_LBREQ_INT_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_I2C_LBREQ_INT_DIR 0x00000400
|
|
+/** I2C Single Data Transfer Request
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_I2C_SREQ_INT 0x00000200
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_I2C_SREQ_INT_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_I2C_SREQ_INT_DIR 0x00000200
|
|
+/** I2C Last Single Data Transfer Request
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_I2C_LSREQ_INT 0x00000100
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_I2C_LSREQ_INT_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_I2C_LSREQ_INT_DIR 0x00000100
|
|
+/** HOST IF Mailbox1 Transmit Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_HOST_MB1_TIR 0x00000010
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_HOST_MB1_TIR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_HOST_MB1_TIR_DIR 0x00000010
|
|
+/** HOST IF Mailbox1 Receive Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_HOST_MB1_RIR 0x00000008
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_HOST_MB1_RIR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_HOST_MB1_RIR_DIR 0x00000008
|
|
+/** HOST IF Mailbox0 Transmit Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_HOST_MB0_TIR 0x00000004
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_HOST_MB0_TIR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_HOST_MB0_TIR_DIR 0x00000004
|
|
+/** HOST IF Mailbox0 Receive Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_HOST_MB0_RIR 0x00000002
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_HOST_MB0_RIR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_HOST_MB0_RIR_DIR 0x00000002
|
|
+/** HOST IF Event Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM0_IMR_HOST_EIR 0x00000001
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM0_IMR_HOST_EIR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM0_IMR_HOST_EIR_DIR 0x00000001
|
|
+
|
|
+/* Fields of "IM1 Interrupt Status Register" */
|
|
+/** Crossbar Error Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_XBAR_ERROR 0x80000000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_XBAR_ERROR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_XBAR_ERROR_INTACK 0x80000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_XBAR_ERROR_INTOCC 0x80000000
|
|
+/** DDR Controller Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_DDR 0x40000000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_DDR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_DDR_INTACK 0x40000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_DDR_INTOCC 0x40000000
|
|
+/** FPI Bus Control Unit Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM1_ISR_BCU0 0x20000000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_BCU0_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_BCU0_INTACK 0x20000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_BCU0_INTOCC 0x20000000
|
|
+/** SBIU interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_SBIU0 0x08000000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_SBIU0_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_SBIU0_INTACK 0x08000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_SBIU0_INTOCC 0x08000000
|
|
+/** Watchdog Prewarning Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_WDT_PIR 0x02000000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_WDT_PIR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_WDT_PIR_INTACK 0x02000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_WDT_PIR_INTOCC 0x02000000
|
|
+/** Watchdog Access Error Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_WDT_AEIR 0x01000000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_WDT_AEIR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_WDT_AEIR_INTACK 0x01000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_WDT_AEIR_INTOCC 0x01000000
|
|
+/** SYS GPE Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_SYS_GPE 0x00200000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_SYS_GPE_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_SYS_GPE_INTACK 0x00200000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_SYS_GPE_INTOCC 0x00200000
|
|
+/** SYS1 Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_SYS1 0x00100000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_SYS1_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_SYS1_INTACK 0x00100000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_SYS1_INTOCC 0x00100000
|
|
+/** PMA Interrupt from IntNode of the RX Clk Domain
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_PMA_RX 0x00020000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_PMA_RX_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_PMA_RX_INTACK 0x00020000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_PMA_RX_INTOCC 0x00020000
|
|
+/** PMA Interrupt from IntNode of the TX Clk Domain
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_PMA_TX 0x00010000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_PMA_TX_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_PMA_TX_INTACK 0x00010000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_PMA_TX_INTOCC 0x00010000
|
|
+/** PMA Interrupt from IntNode of the 200MHz Domain
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_PMA_200M 0x00008000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_PMA_200M_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_PMA_200M_INTACK 0x00008000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_PMA_200M_INTOCC 0x00008000
|
|
+/** Time of Day
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_TOD 0x00004000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_TOD_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_TOD_INTACK 0x00004000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_TOD_INTOCC 0x00004000
|
|
+/** 8kHz root interrupt derived from GPON interface
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM1_ISR_FSC_ROOT 0x00002000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_FSC_ROOT_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_FSC_ROOT_INTACK 0x00002000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_FSC_ROOT_INTOCC 0x00002000
|
|
+/** FSC Timer Interrupt 1
|
|
+ Delayed version of FSCROOT. This bit is a direct interrupt. */
|
|
+#define ICU0_IM1_ISR_FSCT_CMP1 0x00001000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_FSCT_CMP1_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_FSCT_CMP1_INTACK 0x00001000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_FSCT_CMP1_INTOCC 0x00001000
|
|
+/** FSC Timer Interrupt 0
|
|
+ Delayed version of FSCROOT. This bit is a direct interrupt. */
|
|
+#define ICU0_IM1_ISR_FSCT_CMP0 0x00000800
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_FSCT_CMP0_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_FSCT_CMP0_INTACK 0x00000800
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_FSCT_CMP0_INTOCC 0x00000800
|
|
+/** 8kHz backup interrupt derived from core-PLL
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_FSC_BKP 0x00000400
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_FSC_BKP_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_FSC_BKP_INTACK 0x00000400
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_FSC_BKP_INTOCC 0x00000400
|
|
+/** External Interrupt from GPIO P4
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_P4 0x00000100
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_P4_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_P4_INTACK 0x00000100
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_P4_INTOCC 0x00000100
|
|
+/** External Interrupt from GPIO P3
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_P3 0x00000080
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_P3_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_P3_INTACK 0x00000080
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_P3_INTOCC 0x00000080
|
|
+/** External Interrupt from GPIO P2
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_P2 0x00000040
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_P2_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_P2_INTACK 0x00000040
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_P2_INTOCC 0x00000040
|
|
+/** External Interrupt from GPIO P1
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_P1 0x00000020
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_P1_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_P1_INTACK 0x00000020
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_P1_INTOCC 0x00000020
|
|
+/** External Interrupt from GPIO P0
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_P0 0x00000010
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_P0_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_P0_INTACK 0x00000010
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_P0_INTOCC 0x00000010
|
|
+/** EBU Serial Flash Busy
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_EBU_SF_BUSY 0x00000004
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_EBU_SF_BUSY_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_EBU_SF_BUSY_INTACK 0x00000004
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_EBU_SF_BUSY_INTOCC 0x00000004
|
|
+/** EBU Serial Flash Command Overwrite Error
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_EBU_SF_COVERR 0x00000002
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_EBU_SF_COVERR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_EBU_SF_COVERR_INTACK 0x00000002
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_EBU_SF_COVERR_INTOCC 0x00000002
|
|
+/** EBU Serial Flash Command Error
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM1_ISR_EBU_SF_CMDERR 0x00000001
|
|
+/* Nothing
|
|
+#define ICU0_IM1_ISR_EBU_SF_CMDERR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM1_ISR_EBU_SF_CMDERR_INTACK 0x00000001
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_ISR_EBU_SF_CMDERR_INTOCC 0x00000001
|
|
+
|
|
+/* Fields of "IM1 Interrupt Enable Register" */
|
|
+/** Crossbar Error Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_XBAR_ERROR 0x80000000
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_XBAR_ERROR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_XBAR_ERROR_EN 0x80000000
|
|
+/** DDR Controller Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_DDR 0x40000000
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_DDR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_DDR_EN 0x40000000
|
|
+/** FPI Bus Control Unit Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_BCU0 0x20000000
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_BCU0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_BCU0_EN 0x20000000
|
|
+/** SBIU interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_SBIU0 0x08000000
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_SBIU0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_SBIU0_EN 0x08000000
|
|
+/** Watchdog Prewarning Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_WDT_PIR 0x02000000
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_WDT_PIR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_WDT_PIR_EN 0x02000000
|
|
+/** Watchdog Access Error Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_WDT_AEIR 0x01000000
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_WDT_AEIR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_WDT_AEIR_EN 0x01000000
|
|
+/** SYS GPE Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_SYS_GPE 0x00200000
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_SYS_GPE_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_SYS_GPE_EN 0x00200000
|
|
+/** SYS1 Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_SYS1 0x00100000
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_SYS1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_SYS1_EN 0x00100000
|
|
+/** PMA Interrupt from IntNode of the RX Clk Domain
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_PMA_RX 0x00020000
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_PMA_RX_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_PMA_RX_EN 0x00020000
|
|
+/** PMA Interrupt from IntNode of the TX Clk Domain
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_PMA_TX 0x00010000
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_PMA_TX_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_PMA_TX_EN 0x00010000
|
|
+/** PMA Interrupt from IntNode of the 200MHz Domain
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_PMA_200M 0x00008000
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_PMA_200M_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_PMA_200M_EN 0x00008000
|
|
+/** Time of Day
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_TOD 0x00004000
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_TOD_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_TOD_EN 0x00004000
|
|
+/** 8kHz root interrupt derived from GPON interface
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_FSC_ROOT 0x00002000
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_FSC_ROOT_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_FSC_ROOT_EN 0x00002000
|
|
+/** FSC Timer Interrupt 1
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_FSCT_CMP1 0x00001000
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_FSCT_CMP1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_FSCT_CMP1_EN 0x00001000
|
|
+/** FSC Timer Interrupt 0
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_FSCT_CMP0 0x00000800
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_FSCT_CMP0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_FSCT_CMP0_EN 0x00000800
|
|
+/** 8kHz backup interrupt derived from core-PLL
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_FSC_BKP 0x00000400
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_FSC_BKP_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_FSC_BKP_EN 0x00000400
|
|
+/** External Interrupt from GPIO P4
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_P4 0x00000100
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_P4_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_P4_EN 0x00000100
|
|
+/** External Interrupt from GPIO P3
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_P3 0x00000080
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_P3_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_P3_EN 0x00000080
|
|
+/** External Interrupt from GPIO P2
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_P2 0x00000040
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_P2_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_P2_EN 0x00000040
|
|
+/** External Interrupt from GPIO P1
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_P1 0x00000020
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_P1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_P1_EN 0x00000020
|
|
+/** External Interrupt from GPIO P0
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_P0 0x00000010
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_P0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_P0_EN 0x00000010
|
|
+/** EBU Serial Flash Busy
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_EBU_SF_BUSY 0x00000004
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_EBU_SF_BUSY_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_EBU_SF_BUSY_EN 0x00000004
|
|
+/** EBU Serial Flash Command Overwrite Error
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_EBU_SF_COVERR 0x00000002
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_EBU_SF_COVERR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_EBU_SF_COVERR_EN 0x00000002
|
|
+/** EBU Serial Flash Command Error
|
|
+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IER_EBU_SF_CMDERR 0x00000001
|
|
+/* Disable
|
|
+#define ICU0_IM1_IER_EBU_SF_CMDERR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM1_IER_EBU_SF_CMDERR_EN 0x00000001
|
|
+
|
|
+/* Fields of "IM1 Interrupt Output Status Register" */
|
|
+/** Crossbar Error Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_XBAR_ERROR 0x80000000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_XBAR_ERROR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_XBAR_ERROR_INTOCC 0x80000000
|
|
+/** DDR Controller Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_DDR 0x40000000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_DDR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_DDR_INTOCC 0x40000000
|
|
+/** FPI Bus Control Unit Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_BCU0 0x20000000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_BCU0_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_BCU0_INTOCC 0x20000000
|
|
+/** SBIU interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_SBIU0 0x08000000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_SBIU0_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_SBIU0_INTOCC 0x08000000
|
|
+/** Watchdog Prewarning Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_WDT_PIR 0x02000000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_WDT_PIR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_WDT_PIR_INTOCC 0x02000000
|
|
+/** Watchdog Access Error Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_WDT_AEIR 0x01000000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_WDT_AEIR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_WDT_AEIR_INTOCC 0x01000000
|
|
+/** SYS GPE Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_SYS_GPE 0x00200000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_SYS_GPE_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_SYS_GPE_INTOCC 0x00200000
|
|
+/** SYS1 Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_SYS1 0x00100000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_SYS1_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_SYS1_INTOCC 0x00100000
|
|
+/** PMA Interrupt from IntNode of the RX Clk Domain
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_PMA_RX 0x00020000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_PMA_RX_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_PMA_RX_INTOCC 0x00020000
|
|
+/** PMA Interrupt from IntNode of the TX Clk Domain
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_PMA_TX 0x00010000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_PMA_TX_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_PMA_TX_INTOCC 0x00010000
|
|
+/** PMA Interrupt from IntNode of the 200MHz Domain
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_PMA_200M 0x00008000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_PMA_200M_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_PMA_200M_INTOCC 0x00008000
|
|
+/** Time of Day
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_TOD 0x00004000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_TOD_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_TOD_INTOCC 0x00004000
|
|
+/** 8kHz root interrupt derived from GPON interface
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_FSC_ROOT 0x00002000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_FSC_ROOT_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_FSC_ROOT_INTOCC 0x00002000
|
|
+/** FSC Timer Interrupt 1
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_FSCT_CMP1 0x00001000
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_FSCT_CMP1_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_FSCT_CMP1_INTOCC 0x00001000
|
|
+/** FSC Timer Interrupt 0
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_FSCT_CMP0 0x00000800
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_FSCT_CMP0_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_FSCT_CMP0_INTOCC 0x00000800
|
|
+/** 8kHz backup interrupt derived from core-PLL
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_FSC_BKP 0x00000400
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_FSC_BKP_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_FSC_BKP_INTOCC 0x00000400
|
|
+/** External Interrupt from GPIO P4
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_P4 0x00000100
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_P4_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_P4_INTOCC 0x00000100
|
|
+/** External Interrupt from GPIO P3
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_P3 0x00000080
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_P3_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_P3_INTOCC 0x00000080
|
|
+/** External Interrupt from GPIO P2
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_P2 0x00000040
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_P2_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_P2_INTOCC 0x00000040
|
|
+/** External Interrupt from GPIO P1
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_P1 0x00000020
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_P1_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_P1_INTOCC 0x00000020
|
|
+/** External Interrupt from GPIO P0
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_P0 0x00000010
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_P0_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_P0_INTOCC 0x00000010
|
|
+/** EBU Serial Flash Busy
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_EBU_SF_BUSY 0x00000004
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_EBU_SF_BUSY_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_EBU_SF_BUSY_INTOCC 0x00000004
|
|
+/** EBU Serial Flash Command Overwrite Error
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_EBU_SF_COVERR 0x00000002
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_EBU_SF_COVERR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_EBU_SF_COVERR_INTOCC 0x00000002
|
|
+/** EBU Serial Flash Command Error
|
|
+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IOSR_EBU_SF_CMDERR 0x00000001
|
|
+/* Nothing
|
|
+#define ICU0_IM1_IOSR_EBU_SF_CMDERR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM1_IOSR_EBU_SF_CMDERR_INTOCC 0x00000001
|
|
+
|
|
+/* Fields of "IM1 Interrupt Request Set Register" */
|
|
+/** Crossbar Error Interrupt
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_XBAR_ERROR 0x80000000
|
|
+/** DDR Controller Interrupt
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_DDR 0x40000000
|
|
+/** FPI Bus Control Unit Interrupt
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_BCU0 0x20000000
|
|
+/** SBIU interrupt
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_SBIU0 0x08000000
|
|
+/** Watchdog Prewarning Interrupt
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_WDT_PIR 0x02000000
|
|
+/** Watchdog Access Error Interrupt
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_WDT_AEIR 0x01000000
|
|
+/** SYS GPE Interrupt
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_SYS_GPE 0x00200000
|
|
+/** SYS1 Interrupt
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_SYS1 0x00100000
|
|
+/** PMA Interrupt from IntNode of the RX Clk Domain
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_PMA_RX 0x00020000
|
|
+/** PMA Interrupt from IntNode of the TX Clk Domain
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_PMA_TX 0x00010000
|
|
+/** PMA Interrupt from IntNode of the 200MHz Domain
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_PMA_200M 0x00008000
|
|
+/** Time of Day
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_TOD 0x00004000
|
|
+/** 8kHz root interrupt derived from GPON interface
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_FSC_ROOT 0x00002000
|
|
+/** FSC Timer Interrupt 1
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_FSCT_CMP1 0x00001000
|
|
+/** FSC Timer Interrupt 0
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_FSCT_CMP0 0x00000800
|
|
+/** 8kHz backup interrupt derived from core-PLL
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_FSC_BKP 0x00000400
|
|
+/** External Interrupt from GPIO P4
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_P4 0x00000100
|
|
+/** External Interrupt from GPIO P3
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_P3 0x00000080
|
|
+/** External Interrupt from GPIO P2
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_P2 0x00000040
|
|
+/** External Interrupt from GPIO P1
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_P1 0x00000020
|
|
+/** External Interrupt from GPIO P0
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_P0 0x00000010
|
|
+/** EBU Serial Flash Busy
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_EBU_SF_BUSY 0x00000004
|
|
+/** EBU Serial Flash Command Overwrite Error
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_EBU_SF_COVERR 0x00000002
|
|
+/** EBU Serial Flash Command Error
|
|
+ Software control for the corresponding bit in the IM1_ISR register. */
|
|
+#define ICU0_IM1_IRSR_EBU_SF_CMDERR 0x00000001
|
|
+
|
|
+/* Fields of "IM1 Interrupt Mode Register" */
|
|
+/** Crossbar Error Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_XBAR_ERROR 0x80000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_XBAR_ERROR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_XBAR_ERROR_DIR 0x80000000
|
|
+/** DDR Controller Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_DDR 0x40000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_DDR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_DDR_DIR 0x40000000
|
|
+/** FPI Bus Control Unit Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_BCU0 0x20000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_BCU0_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_BCU0_DIR 0x20000000
|
|
+/** SBIU interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_SBIU0 0x08000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_SBIU0_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_SBIU0_DIR 0x08000000
|
|
+/** Watchdog Prewarning Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_WDT_PIR 0x02000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_WDT_PIR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_WDT_PIR_DIR 0x02000000
|
|
+/** Watchdog Access Error Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_WDT_AEIR 0x01000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_WDT_AEIR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_WDT_AEIR_DIR 0x01000000
|
|
+/** SYS GPE Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_SYS_GPE 0x00200000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_SYS_GPE_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_SYS_GPE_DIR 0x00200000
|
|
+/** SYS1 Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_SYS1 0x00100000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_SYS1_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_SYS1_DIR 0x00100000
|
|
+/** PMA Interrupt from IntNode of the RX Clk Domain
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_PMA_RX 0x00020000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_PMA_RX_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_PMA_RX_DIR 0x00020000
|
|
+/** PMA Interrupt from IntNode of the TX Clk Domain
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_PMA_TX 0x00010000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_PMA_TX_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_PMA_TX_DIR 0x00010000
|
|
+/** PMA Interrupt from IntNode of the 200MHz Domain
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_PMA_200M 0x00008000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_PMA_200M_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_PMA_200M_DIR 0x00008000
|
|
+/** Time of Day
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_TOD 0x00004000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_TOD_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_TOD_DIR 0x00004000
|
|
+/** 8kHz root interrupt derived from GPON interface
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_FSC_ROOT 0x00002000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_FSC_ROOT_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_FSC_ROOT_DIR 0x00002000
|
|
+/** FSC Timer Interrupt 1
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_FSCT_CMP1 0x00001000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_FSCT_CMP1_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_FSCT_CMP1_DIR 0x00001000
|
|
+/** FSC Timer Interrupt 0
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_FSCT_CMP0 0x00000800
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_FSCT_CMP0_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_FSCT_CMP0_DIR 0x00000800
|
|
+/** 8kHz backup interrupt derived from core-PLL
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_FSC_BKP 0x00000400
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_FSC_BKP_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_FSC_BKP_DIR 0x00000400
|
|
+/** External Interrupt from GPIO P4
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_P4 0x00000100
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_P4_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_P4_DIR 0x00000100
|
|
+/** External Interrupt from GPIO P3
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_P3 0x00000080
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_P3_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_P3_DIR 0x00000080
|
|
+/** External Interrupt from GPIO P2
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_P2 0x00000040
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_P2_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_P2_DIR 0x00000040
|
|
+/** External Interrupt from GPIO P1
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_P1 0x00000020
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_P1_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_P1_DIR 0x00000020
|
|
+/** External Interrupt from GPIO P0
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_P0 0x00000010
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_P0_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_P0_DIR 0x00000010
|
|
+/** EBU Serial Flash Busy
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_EBU_SF_BUSY 0x00000004
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_EBU_SF_BUSY_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_EBU_SF_BUSY_DIR 0x00000004
|
|
+/** EBU Serial Flash Command Overwrite Error
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_EBU_SF_COVERR 0x00000002
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_EBU_SF_COVERR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_EBU_SF_COVERR_DIR 0x00000002
|
|
+/** EBU Serial Flash Command Error
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM1_IMR_EBU_SF_CMDERR 0x00000001
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM1_IMR_EBU_SF_CMDERR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM1_IMR_EBU_SF_CMDERR_DIR 0x00000001
|
|
+
|
|
+/* Fields of "IM2 Interrupt Status Register" */
|
|
+/** EIM Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_EIM 0x80000000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_EIM_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_EIM_INTACK 0x80000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_EIM_INTOCC 0x80000000
|
|
+/** GTC Upstream Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_GTC_US 0x40000000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_GTC_US_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_GTC_US_INTACK 0x40000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_GTC_US_INTOCC 0x40000000
|
|
+/** GTC Downstream Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_GTC_DS 0x20000000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_GTC_DS_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_GTC_DS_INTACK 0x20000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_GTC_DS_INTOCC 0x20000000
|
|
+/** TBM Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_TBM 0x00400000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_TBM_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_TBM_INTACK 0x00400000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_TBM_INTOCC 0x00400000
|
|
+/** Dispatcher Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_DISP 0x00200000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_DISP_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_DISP_INTACK 0x00200000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_DISP_INTOCC 0x00200000
|
|
+/** CONFIG Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_CONFIG 0x00100000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_CONFIG_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_CONFIG_INTACK 0x00100000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_CONFIG_INTOCC 0x00100000
|
|
+/** CONFIG Break Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_CONFIG_BREAK 0x00080000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_CONFIG_BREAK_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_CONFIG_BREAK_INTACK 0x00080000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_CONFIG_BREAK_INTOCC 0x00080000
|
|
+/** OCTRLC Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_OCTRLC 0x00040000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_OCTRLC_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_OCTRLC_INTACK 0x00040000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_OCTRLC_INTOCC 0x00040000
|
|
+/** ICTRLC 1 Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_ICTRLC1 0x00020000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_ICTRLC1_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_ICTRLC1_INTACK 0x00020000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_ICTRLC1_INTOCC 0x00020000
|
|
+/** ICTRLC 0 Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_ICTRLC0 0x00010000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_ICTRLC0_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_ICTRLC0_INTACK 0x00010000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_ICTRLC0_INTOCC 0x00010000
|
|
+/** LINK 1 Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_LINK1 0x00004000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_LINK1_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_LINK1_INTACK 0x00004000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_LINK1_INTOCC 0x00004000
|
|
+/** TMU Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_TMU 0x00001000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_TMU_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_TMU_INTACK 0x00001000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_TMU_INTOCC 0x00001000
|
|
+/** FSQM Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_FSQM 0x00000800
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_FSQM_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_FSQM_INTACK 0x00000800
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_FSQM_INTOCC 0x00000800
|
|
+/** IQM Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_IQM 0x00000400
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_IQM_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_IQM_INTACK 0x00000400
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_IQM_INTOCC 0x00000400
|
|
+/** OCTRLG Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_OCTRLG 0x00000200
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_OCTRLG_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_OCTRLG_INTACK 0x00000200
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_OCTRLG_INTOCC 0x00000200
|
|
+/** OCTRLL 3 Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_OCTRLL3 0x00000080
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_OCTRLL3_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_OCTRLL3_INTACK 0x00000080
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_OCTRLL3_INTOCC 0x00000080
|
|
+/** OCTRLL 2 Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_OCTRLL2 0x00000040
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_OCTRLL2_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_OCTRLL2_INTACK 0x00000040
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_OCTRLL2_INTOCC 0x00000040
|
|
+/** OCTRLL 1 Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_OCTRLL1 0x00000020
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_OCTRLL1_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_OCTRLL1_INTACK 0x00000020
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_OCTRLL1_INTOCC 0x00000020
|
|
+/** OCTRLL 0 Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_OCTRLL0 0x00000010
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_OCTRLL0_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_OCTRLL0_INTACK 0x00000010
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_OCTRLL0_INTOCC 0x00000010
|
|
+/** ICTRLL 3 Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_ICTRLL3 0x00000008
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_ICTRLL3_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_ICTRLL3_INTACK 0x00000008
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_ICTRLL3_INTOCC 0x00000008
|
|
+/** ICTRLL 2 Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_ICTRLL2 0x00000004
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_ICTRLL2_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_ICTRLL2_INTACK 0x00000004
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_ICTRLL2_INTOCC 0x00000004
|
|
+/** ICTRLL 1 Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_ICTRLL1 0x00000002
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_ICTRLL1_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_ICTRLL1_INTACK 0x00000002
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_ICTRLL1_INTOCC 0x00000002
|
|
+/** ICTRLL 0 Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM2_ISR_ICTRLL0 0x00000001
|
|
+/* Nothing
|
|
+#define ICU0_IM2_ISR_ICTRLL0_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM2_ISR_ICTRLL0_INTACK 0x00000001
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_ISR_ICTRLL0_INTOCC 0x00000001
|
|
+
|
|
+/* Fields of "IM2 Interrupt Enable Register" */
|
|
+/** EIM Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_EIM 0x80000000
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_EIM_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_EIM_EN 0x80000000
|
|
+/** GTC Upstream Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_GTC_US 0x40000000
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_GTC_US_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_GTC_US_EN 0x40000000
|
|
+/** GTC Downstream Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_GTC_DS 0x20000000
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_GTC_DS_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_GTC_DS_EN 0x20000000
|
|
+/** TBM Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_TBM 0x00400000
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_TBM_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_TBM_EN 0x00400000
|
|
+/** Dispatcher Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_DISP 0x00200000
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_DISP_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_DISP_EN 0x00200000
|
|
+/** CONFIG Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_CONFIG 0x00100000
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_CONFIG_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_CONFIG_EN 0x00100000
|
|
+/** CONFIG Break Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_CONFIG_BREAK 0x00080000
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_CONFIG_BREAK_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_CONFIG_BREAK_EN 0x00080000
|
|
+/** OCTRLC Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_OCTRLC 0x00040000
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_OCTRLC_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_OCTRLC_EN 0x00040000
|
|
+/** ICTRLC 1 Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_ICTRLC1 0x00020000
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_ICTRLC1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_ICTRLC1_EN 0x00020000
|
|
+/** ICTRLC 0 Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_ICTRLC0 0x00010000
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_ICTRLC0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_ICTRLC0_EN 0x00010000
|
|
+/** LINK 1 Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_LINK1 0x00004000
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_LINK1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_LINK1_EN 0x00004000
|
|
+/** TMU Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_TMU 0x00001000
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_TMU_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_TMU_EN 0x00001000
|
|
+/** FSQM Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_FSQM 0x00000800
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_FSQM_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_FSQM_EN 0x00000800
|
|
+/** IQM Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_IQM 0x00000400
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_IQM_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_IQM_EN 0x00000400
|
|
+/** OCTRLG Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_OCTRLG 0x00000200
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_OCTRLG_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_OCTRLG_EN 0x00000200
|
|
+/** OCTRLL 3 Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_OCTRLL3 0x00000080
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_OCTRLL3_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_OCTRLL3_EN 0x00000080
|
|
+/** OCTRLL 2 Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_OCTRLL2 0x00000040
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_OCTRLL2_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_OCTRLL2_EN 0x00000040
|
|
+/** OCTRLL 1 Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_OCTRLL1 0x00000020
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_OCTRLL1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_OCTRLL1_EN 0x00000020
|
|
+/** OCTRLL 0 Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_OCTRLL0 0x00000010
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_OCTRLL0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_OCTRLL0_EN 0x00000010
|
|
+/** ICTRLL 3 Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_ICTRLL3 0x00000008
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_ICTRLL3_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_ICTRLL3_EN 0x00000008
|
|
+/** ICTRLL 2 Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_ICTRLL2 0x00000004
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_ICTRLL2_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_ICTRLL2_EN 0x00000004
|
|
+/** ICTRLL 1 Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_ICTRLL1 0x00000002
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_ICTRLL1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_ICTRLL1_EN 0x00000002
|
|
+/** ICTRLL 0 Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IER_ICTRLL0 0x00000001
|
|
+/* Disable
|
|
+#define ICU0_IM2_IER_ICTRLL0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM2_IER_ICTRLL0_EN 0x00000001
|
|
+
|
|
+/* Fields of "IM2 Interrupt Output Status Register" */
|
|
+/** EIM Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_EIM 0x80000000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_EIM_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_EIM_INTOCC 0x80000000
|
|
+/** GTC Upstream Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_GTC_US 0x40000000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_GTC_US_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_GTC_US_INTOCC 0x40000000
|
|
+/** GTC Downstream Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_GTC_DS 0x20000000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_GTC_DS_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_GTC_DS_INTOCC 0x20000000
|
|
+/** TBM Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_TBM 0x00400000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_TBM_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_TBM_INTOCC 0x00400000
|
|
+/** Dispatcher Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_DISP 0x00200000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_DISP_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_DISP_INTOCC 0x00200000
|
|
+/** CONFIG Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_CONFIG 0x00100000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_CONFIG_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_CONFIG_INTOCC 0x00100000
|
|
+/** CONFIG Break Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_CONFIG_BREAK 0x00080000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_CONFIG_BREAK_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_CONFIG_BREAK_INTOCC 0x00080000
|
|
+/** OCTRLC Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_OCTRLC 0x00040000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_OCTRLC_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_OCTRLC_INTOCC 0x00040000
|
|
+/** ICTRLC 1 Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_ICTRLC1 0x00020000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_ICTRLC1_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_ICTRLC1_INTOCC 0x00020000
|
|
+/** ICTRLC 0 Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_ICTRLC0 0x00010000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_ICTRLC0_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_ICTRLC0_INTOCC 0x00010000
|
|
+/** LINK 1 Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_LINK1 0x00004000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_LINK1_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_LINK1_INTOCC 0x00004000
|
|
+/** TMU Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_TMU 0x00001000
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_TMU_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_TMU_INTOCC 0x00001000
|
|
+/** FSQM Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_FSQM 0x00000800
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_FSQM_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_FSQM_INTOCC 0x00000800
|
|
+/** IQM Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_IQM 0x00000400
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_IQM_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_IQM_INTOCC 0x00000400
|
|
+/** OCTRLG Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_OCTRLG 0x00000200
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_OCTRLG_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_OCTRLG_INTOCC 0x00000200
|
|
+/** OCTRLL 3 Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_OCTRLL3 0x00000080
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_OCTRLL3_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_OCTRLL3_INTOCC 0x00000080
|
|
+/** OCTRLL 2 Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_OCTRLL2 0x00000040
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_OCTRLL2_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_OCTRLL2_INTOCC 0x00000040
|
|
+/** OCTRLL 1 Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_OCTRLL1 0x00000020
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_OCTRLL1_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_OCTRLL1_INTOCC 0x00000020
|
|
+/** OCTRLL 0 Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_OCTRLL0 0x00000010
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_OCTRLL0_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_OCTRLL0_INTOCC 0x00000010
|
|
+/** ICTRLL 3 Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_ICTRLL3 0x00000008
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_ICTRLL3_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_ICTRLL3_INTOCC 0x00000008
|
|
+/** ICTRLL 2 Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_ICTRLL2 0x00000004
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_ICTRLL2_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_ICTRLL2_INTOCC 0x00000004
|
|
+/** ICTRLL 1 Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_ICTRLL1 0x00000002
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_ICTRLL1_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_ICTRLL1_INTOCC 0x00000002
|
|
+/** ICTRLL 0 Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IOSR_ICTRLL0 0x00000001
|
|
+/* Nothing
|
|
+#define ICU0_IM2_IOSR_ICTRLL0_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM2_IOSR_ICTRLL0_INTOCC 0x00000001
|
|
+
|
|
+/* Fields of "IM2 Interrupt Request Set Register" */
|
|
+/** EIM Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_EIM 0x80000000
|
|
+/** GTC Upstream Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_GTC_US 0x40000000
|
|
+/** GTC Downstream Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_GTC_DS 0x20000000
|
|
+/** TBM Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_TBM 0x00400000
|
|
+/** Dispatcher Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_DISP 0x00200000
|
|
+/** CONFIG Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_CONFIG 0x00100000
|
|
+/** CONFIG Break Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_CONFIG_BREAK 0x00080000
|
|
+/** OCTRLC Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_OCTRLC 0x00040000
|
|
+/** ICTRLC 1 Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_ICTRLC1 0x00020000
|
|
+/** ICTRLC 0 Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_ICTRLC0 0x00010000
|
|
+/** LINK 1 Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_LINK1 0x00004000
|
|
+/** TMU Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_TMU 0x00001000
|
|
+/** FSQM Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_FSQM 0x00000800
|
|
+/** IQM Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_IQM 0x00000400
|
|
+/** OCTRLG Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_OCTRLG 0x00000200
|
|
+/** OCTRLL 3 Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_OCTRLL3 0x00000080
|
|
+/** OCTRLL 2 Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_OCTRLL2 0x00000040
|
|
+/** OCTRLL 1 Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_OCTRLL1 0x00000020
|
|
+/** OCTRLL 0 Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_OCTRLL0 0x00000010
|
|
+/** ICTRLL 3 Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_ICTRLL3 0x00000008
|
|
+/** ICTRLL 2 Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_ICTRLL2 0x00000004
|
|
+/** ICTRLL 1 Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_ICTRLL1 0x00000002
|
|
+/** ICTRLL 0 Interrupt
|
|
+ Software control for the corresponding bit in the IM2_ISR register. */
|
|
+#define ICU0_IM2_IRSR_ICTRLL0 0x00000001
|
|
+
|
|
+/* Fields of "IM2 Interrupt Mode Register" */
|
|
+/** EIM Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_EIM 0x80000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_EIM_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_EIM_DIR 0x80000000
|
|
+/** GTC Upstream Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_GTC_US 0x40000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_GTC_US_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_GTC_US_DIR 0x40000000
|
|
+/** GTC Downstream Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_GTC_DS 0x20000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_GTC_DS_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_GTC_DS_DIR 0x20000000
|
|
+/** TBM Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_TBM 0x00400000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_TBM_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_TBM_DIR 0x00400000
|
|
+/** Dispatcher Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_DISP 0x00200000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_DISP_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_DISP_DIR 0x00200000
|
|
+/** CONFIG Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_CONFIG 0x00100000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_CONFIG_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_CONFIG_DIR 0x00100000
|
|
+/** CONFIG Break Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_CONFIG_BREAK 0x00080000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_CONFIG_BREAK_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_CONFIG_BREAK_DIR 0x00080000
|
|
+/** OCTRLC Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_OCTRLC 0x00040000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_OCTRLC_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_OCTRLC_DIR 0x00040000
|
|
+/** ICTRLC 1 Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_ICTRLC1 0x00020000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_ICTRLC1_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_ICTRLC1_DIR 0x00020000
|
|
+/** ICTRLC 0 Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_ICTRLC0 0x00010000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_ICTRLC0_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_ICTRLC0_DIR 0x00010000
|
|
+/** LINK 1 Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_LINK1 0x00004000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_LINK1_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_LINK1_DIR 0x00004000
|
|
+/** TMU Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_TMU 0x00001000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_TMU_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_TMU_DIR 0x00001000
|
|
+/** FSQM Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_FSQM 0x00000800
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_FSQM_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_FSQM_DIR 0x00000800
|
|
+/** IQM Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_IQM 0x00000400
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_IQM_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_IQM_DIR 0x00000400
|
|
+/** OCTRLG Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_OCTRLG 0x00000200
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_OCTRLG_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_OCTRLG_DIR 0x00000200
|
|
+/** OCTRLL 3 Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_OCTRLL3 0x00000080
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_OCTRLL3_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_OCTRLL3_DIR 0x00000080
|
|
+/** OCTRLL 2 Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_OCTRLL2 0x00000040
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_OCTRLL2_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_OCTRLL2_DIR 0x00000040
|
|
+/** OCTRLL 1 Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_OCTRLL1 0x00000020
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_OCTRLL1_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_OCTRLL1_DIR 0x00000020
|
|
+/** OCTRLL 0 Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_OCTRLL0 0x00000010
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_OCTRLL0_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_OCTRLL0_DIR 0x00000010
|
|
+/** ICTRLL 3 Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_ICTRLL3 0x00000008
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_ICTRLL3_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_ICTRLL3_DIR 0x00000008
|
|
+/** ICTRLL 2 Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_ICTRLL2 0x00000004
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_ICTRLL2_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_ICTRLL2_DIR 0x00000004
|
|
+/** ICTRLL 1 Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_ICTRLL1 0x00000002
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_ICTRLL1_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_ICTRLL1_DIR 0x00000002
|
|
+/** ICTRLL 0 Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM2_IMR_ICTRLL0 0x00000001
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM2_IMR_ICTRLL0_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM2_IMR_ICTRLL0_DIR 0x00000001
|
|
+
|
|
+/* Fields of "IM3 Interrupt Status Register" */
|
|
+/** DFEV0, Channel 0 General Purpose Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM3_ISR_DFEV0_1GP 0x80000000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_DFEV0_1GP_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_DFEV0_1GP_INTACK 0x80000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_DFEV0_1GP_INTOCC 0x80000000
|
|
+/** DFEV0, Channel 0 Receive Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM3_ISR_DFEV0_1RX 0x40000000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_DFEV0_1RX_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_DFEV0_1RX_INTACK 0x40000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_DFEV0_1RX_INTOCC 0x40000000
|
|
+/** DFEV0, Channel 0 Transmit Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM3_ISR_DFEV0_1TX 0x20000000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_DFEV0_1TX_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_DFEV0_1TX_INTACK 0x20000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_DFEV0_1TX_INTOCC 0x20000000
|
|
+/** DFEV0, Channel 1 General Purpose Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM3_ISR_DFEV0_2GP 0x10000000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_DFEV0_2GP_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_DFEV0_2GP_INTACK 0x10000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_DFEV0_2GP_INTOCC 0x10000000
|
|
+/** DFEV0, Channel 1 Receive Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM3_ISR_DFEV0_2RX 0x08000000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_DFEV0_2RX_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_DFEV0_2RX_INTACK 0x08000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_DFEV0_2RX_INTOCC 0x08000000
|
|
+/** DFEV0, Channel 1 Transmit Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM3_ISR_DFEV0_2TX 0x04000000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_DFEV0_2TX_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_DFEV0_2TX_INTACK 0x04000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_DFEV0_2TX_INTOCC 0x04000000
|
|
+/** GPTC Timer/Counter 3B Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_GPTC_TC3B 0x00200000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_GPTC_TC3B_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_GPTC_TC3B_INTACK 0x00200000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_GPTC_TC3B_INTOCC 0x00200000
|
|
+/** GPTC Timer/Counter 3A Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_GPTC_TC3A 0x00100000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_GPTC_TC3A_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_GPTC_TC3A_INTACK 0x00100000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_GPTC_TC3A_INTOCC 0x00100000
|
|
+/** GPTC Timer/Counter 2B Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_GPTC_TC2B 0x00080000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_GPTC_TC2B_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_GPTC_TC2B_INTACK 0x00080000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_GPTC_TC2B_INTOCC 0x00080000
|
|
+/** GPTC Timer/Counter 2A Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_GPTC_TC2A 0x00040000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_GPTC_TC2A_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_GPTC_TC2A_INTACK 0x00040000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_GPTC_TC2A_INTOCC 0x00040000
|
|
+/** GPTC Timer/Counter 1B Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_GPTC_TC1B 0x00020000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_GPTC_TC1B_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_GPTC_TC1B_INTACK 0x00020000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_GPTC_TC1B_INTOCC 0x00020000
|
|
+/** GPTC Timer/Counter 1A Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_GPTC_TC1A 0x00010000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_GPTC_TC1A_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_GPTC_TC1A_INTACK 0x00010000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_GPTC_TC1A_INTOCC 0x00010000
|
|
+/** ASC1 Soft Flow Control Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC1_SFC 0x00008000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_ASC1_SFC_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC1_SFC_INTACK 0x00008000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_ASC1_SFC_INTOCC 0x00008000
|
|
+/** ASC1 Modem Status Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC1_MS 0x00004000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_ASC1_MS_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC1_MS_INTACK 0x00004000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_ASC1_MS_INTOCC 0x00004000
|
|
+/** ASC1 Autobaud Detection Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC1_ABDET 0x00002000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_ASC1_ABDET_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC1_ABDET_INTACK 0x00002000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_ASC1_ABDET_INTOCC 0x00002000
|
|
+/** ASC1 Autobaud Start Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC1_ABST 0x00001000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_ASC1_ABST_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC1_ABST_INTACK 0x00001000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_ASC1_ABST_INTOCC 0x00001000
|
|
+/** ASC1 Transmit Buffer Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC1_TB 0x00000800
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_ASC1_TB_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC1_TB_INTACK 0x00000800
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_ASC1_TB_INTOCC 0x00000800
|
|
+/** ASC1 Error Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC1_E 0x00000400
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_ASC1_E_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC1_E_INTACK 0x00000400
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_ASC1_E_INTOCC 0x00000400
|
|
+/** ASC1 Receive Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC1_R 0x00000200
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_ASC1_R_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC1_R_INTACK 0x00000200
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_ASC1_R_INTOCC 0x00000200
|
|
+/** ASC1 Transmit Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC1_T 0x00000100
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_ASC1_T_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC1_T_INTACK 0x00000100
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_ASC1_T_INTOCC 0x00000100
|
|
+/** ASC0 Soft Flow Control Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC0_SFC 0x00000080
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_ASC0_SFC_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC0_SFC_INTACK 0x00000080
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_ASC0_SFC_INTOCC 0x00000080
|
|
+/** ASC1 Modem Status Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC0_MS 0x00000040
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_ASC0_MS_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC0_MS_INTACK 0x00000040
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_ASC0_MS_INTOCC 0x00000040
|
|
+/** ASC0 Autobaud Detection Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC0_ABDET 0x00000020
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_ASC0_ABDET_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC0_ABDET_INTACK 0x00000020
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_ASC0_ABDET_INTOCC 0x00000020
|
|
+/** ASC0 Autobaud Start Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC0_ABST 0x00000010
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_ASC0_ABST_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC0_ABST_INTACK 0x00000010
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_ASC0_ABST_INTOCC 0x00000010
|
|
+/** ASC0 Transmit Buffer Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC0_TB 0x00000008
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_ASC0_TB_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC0_TB_INTACK 0x00000008
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_ASC0_TB_INTOCC 0x00000008
|
|
+/** ASC0 Error Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC0_E 0x00000004
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_ASC0_E_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC0_E_INTACK 0x00000004
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_ASC0_E_INTOCC 0x00000004
|
|
+/** ASC0 Receive Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC0_R 0x00000002
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_ASC0_R_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC0_R_INTACK 0x00000002
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_ASC0_R_INTOCC 0x00000002
|
|
+/** ASC0 Transmit Interrupt
|
|
+ This bit is a direct interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC0_T 0x00000001
|
|
+/* Nothing
|
|
+#define ICU0_IM3_ISR_ASC0_T_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM3_ISR_ASC0_T_INTACK 0x00000001
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_ISR_ASC0_T_INTOCC 0x00000001
|
|
+
|
|
+/* Fields of "IM3 Interrupt Enable Register" */
|
|
+/** DFEV0, Channel 0 General Purpose Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_DFEV0_1GP 0x80000000
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_DFEV0_1GP_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_DFEV0_1GP_EN 0x80000000
|
|
+/** DFEV0, Channel 0 Receive Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_DFEV0_1RX 0x40000000
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_DFEV0_1RX_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_DFEV0_1RX_EN 0x40000000
|
|
+/** DFEV0, Channel 0 Transmit Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_DFEV0_1TX 0x20000000
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_DFEV0_1TX_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_DFEV0_1TX_EN 0x20000000
|
|
+/** DFEV0, Channel 1 General Purpose Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_DFEV0_2GP 0x10000000
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_DFEV0_2GP_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_DFEV0_2GP_EN 0x10000000
|
|
+/** DFEV0, Channel 1 Receive Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_DFEV0_2RX 0x08000000
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_DFEV0_2RX_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_DFEV0_2RX_EN 0x08000000
|
|
+/** DFEV0, Channel 1 Transmit Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_DFEV0_2TX 0x04000000
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_DFEV0_2TX_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_DFEV0_2TX_EN 0x04000000
|
|
+/** GPTC Timer/Counter 3B Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_GPTC_TC3B 0x00200000
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_GPTC_TC3B_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_GPTC_TC3B_EN 0x00200000
|
|
+/** GPTC Timer/Counter 3A Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_GPTC_TC3A 0x00100000
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_GPTC_TC3A_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_GPTC_TC3A_EN 0x00100000
|
|
+/** GPTC Timer/Counter 2B Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_GPTC_TC2B 0x00080000
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_GPTC_TC2B_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_GPTC_TC2B_EN 0x00080000
|
|
+/** GPTC Timer/Counter 2A Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_GPTC_TC2A 0x00040000
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_GPTC_TC2A_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_GPTC_TC2A_EN 0x00040000
|
|
+/** GPTC Timer/Counter 1B Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_GPTC_TC1B 0x00020000
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_GPTC_TC1B_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_GPTC_TC1B_EN 0x00020000
|
|
+/** GPTC Timer/Counter 1A Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_GPTC_TC1A 0x00010000
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_GPTC_TC1A_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_GPTC_TC1A_EN 0x00010000
|
|
+/** ASC1 Soft Flow Control Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_ASC1_SFC 0x00008000
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_ASC1_SFC_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_ASC1_SFC_EN 0x00008000
|
|
+/** ASC1 Modem Status Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_ASC1_MS 0x00004000
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_ASC1_MS_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_ASC1_MS_EN 0x00004000
|
|
+/** ASC1 Autobaud Detection Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_ASC1_ABDET 0x00002000
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_ASC1_ABDET_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_ASC1_ABDET_EN 0x00002000
|
|
+/** ASC1 Autobaud Start Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_ASC1_ABST 0x00001000
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_ASC1_ABST_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_ASC1_ABST_EN 0x00001000
|
|
+/** ASC1 Transmit Buffer Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_ASC1_TB 0x00000800
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_ASC1_TB_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_ASC1_TB_EN 0x00000800
|
|
+/** ASC1 Error Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_ASC1_E 0x00000400
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_ASC1_E_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_ASC1_E_EN 0x00000400
|
|
+/** ASC1 Receive Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_ASC1_R 0x00000200
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_ASC1_R_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_ASC1_R_EN 0x00000200
|
|
+/** ASC1 Transmit Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_ASC1_T 0x00000100
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_ASC1_T_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_ASC1_T_EN 0x00000100
|
|
+/** ASC0 Soft Flow Control Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_ASC0_SFC 0x00000080
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_ASC0_SFC_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_ASC0_SFC_EN 0x00000080
|
|
+/** ASC1 Modem Status Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_ASC0_MS 0x00000040
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_ASC0_MS_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_ASC0_MS_EN 0x00000040
|
|
+/** ASC0 Autobaud Detection Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_ASC0_ABDET 0x00000020
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_ASC0_ABDET_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_ASC0_ABDET_EN 0x00000020
|
|
+/** ASC0 Autobaud Start Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_ASC0_ABST 0x00000010
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_ASC0_ABST_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_ASC0_ABST_EN 0x00000010
|
|
+/** ASC0 Transmit Buffer Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_ASC0_TB 0x00000008
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_ASC0_TB_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_ASC0_TB_EN 0x00000008
|
|
+/** ASC0 Error Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_ASC0_E 0x00000004
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_ASC0_E_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_ASC0_E_EN 0x00000004
|
|
+/** ASC0 Receive Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_ASC0_R 0x00000002
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_ASC0_R_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_ASC0_R_EN 0x00000002
|
|
+/** ASC0 Transmit Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IER_ASC0_T 0x00000001
|
|
+/* Disable
|
|
+#define ICU0_IM3_IER_ASC0_T_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM3_IER_ASC0_T_EN 0x00000001
|
|
+
|
|
+/* Fields of "IM3 Interrupt Output Status Register" */
|
|
+/** DFEV0, Channel 0 General Purpose Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_DFEV0_1GP 0x80000000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_DFEV0_1GP_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_DFEV0_1GP_INTOCC 0x80000000
|
|
+/** DFEV0, Channel 0 Receive Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_DFEV0_1RX 0x40000000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_DFEV0_1RX_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_DFEV0_1RX_INTOCC 0x40000000
|
|
+/** DFEV0, Channel 0 Transmit Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_DFEV0_1TX 0x20000000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_DFEV0_1TX_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_DFEV0_1TX_INTOCC 0x20000000
|
|
+/** DFEV0, Channel 1 General Purpose Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_DFEV0_2GP 0x10000000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_DFEV0_2GP_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_DFEV0_2GP_INTOCC 0x10000000
|
|
+/** DFEV0, Channel 1 Receive Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_DFEV0_2RX 0x08000000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_DFEV0_2RX_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_DFEV0_2RX_INTOCC 0x08000000
|
|
+/** DFEV0, Channel 1 Transmit Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_DFEV0_2TX 0x04000000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_DFEV0_2TX_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_DFEV0_2TX_INTOCC 0x04000000
|
|
+/** GPTC Timer/Counter 3B Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_GPTC_TC3B 0x00200000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_GPTC_TC3B_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_GPTC_TC3B_INTOCC 0x00200000
|
|
+/** GPTC Timer/Counter 3A Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_GPTC_TC3A 0x00100000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_GPTC_TC3A_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_GPTC_TC3A_INTOCC 0x00100000
|
|
+/** GPTC Timer/Counter 2B Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_GPTC_TC2B 0x00080000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_GPTC_TC2B_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_GPTC_TC2B_INTOCC 0x00080000
|
|
+/** GPTC Timer/Counter 2A Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_GPTC_TC2A 0x00040000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_GPTC_TC2A_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_GPTC_TC2A_INTOCC 0x00040000
|
|
+/** GPTC Timer/Counter 1B Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_GPTC_TC1B 0x00020000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_GPTC_TC1B_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_GPTC_TC1B_INTOCC 0x00020000
|
|
+/** GPTC Timer/Counter 1A Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_GPTC_TC1A 0x00010000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_GPTC_TC1A_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_GPTC_TC1A_INTOCC 0x00010000
|
|
+/** ASC1 Soft Flow Control Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_ASC1_SFC 0x00008000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_ASC1_SFC_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_ASC1_SFC_INTOCC 0x00008000
|
|
+/** ASC1 Modem Status Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_ASC1_MS 0x00004000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_ASC1_MS_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_ASC1_MS_INTOCC 0x00004000
|
|
+/** ASC1 Autobaud Detection Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_ASC1_ABDET 0x00002000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_ASC1_ABDET_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_ASC1_ABDET_INTOCC 0x00002000
|
|
+/** ASC1 Autobaud Start Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_ASC1_ABST 0x00001000
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_ASC1_ABST_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_ASC1_ABST_INTOCC 0x00001000
|
|
+/** ASC1 Transmit Buffer Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_ASC1_TB 0x00000800
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_ASC1_TB_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_ASC1_TB_INTOCC 0x00000800
|
|
+/** ASC1 Error Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_ASC1_E 0x00000400
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_ASC1_E_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_ASC1_E_INTOCC 0x00000400
|
|
+/** ASC1 Receive Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_ASC1_R 0x00000200
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_ASC1_R_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_ASC1_R_INTOCC 0x00000200
|
|
+/** ASC1 Transmit Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_ASC1_T 0x00000100
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_ASC1_T_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_ASC1_T_INTOCC 0x00000100
|
|
+/** ASC0 Soft Flow Control Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_ASC0_SFC 0x00000080
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_ASC0_SFC_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_ASC0_SFC_INTOCC 0x00000080
|
|
+/** ASC1 Modem Status Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_ASC0_MS 0x00000040
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_ASC0_MS_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_ASC0_MS_INTOCC 0x00000040
|
|
+/** ASC0 Autobaud Detection Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_ASC0_ABDET 0x00000020
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_ASC0_ABDET_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_ASC0_ABDET_INTOCC 0x00000020
|
|
+/** ASC0 Autobaud Start Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_ASC0_ABST 0x00000010
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_ASC0_ABST_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_ASC0_ABST_INTOCC 0x00000010
|
|
+/** ASC0 Transmit Buffer Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_ASC0_TB 0x00000008
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_ASC0_TB_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_ASC0_TB_INTOCC 0x00000008
|
|
+/** ASC0 Error Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_ASC0_E 0x00000004
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_ASC0_E_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_ASC0_E_INTOCC 0x00000004
|
|
+/** ASC0 Receive Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_ASC0_R 0x00000002
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_ASC0_R_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_ASC0_R_INTOCC 0x00000002
|
|
+/** ASC0 Transmit Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IOSR_ASC0_T 0x00000001
|
|
+/* Nothing
|
|
+#define ICU0_IM3_IOSR_ASC0_T_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM3_IOSR_ASC0_T_INTOCC 0x00000001
|
|
+
|
|
+/* Fields of "IM3 Interrupt Request Set Register" */
|
|
+/** DFEV0, Channel 0 General Purpose Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_DFEV0_1GP 0x80000000
|
|
+/** DFEV0, Channel 0 Receive Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_DFEV0_1RX 0x40000000
|
|
+/** DFEV0, Channel 0 Transmit Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_DFEV0_1TX 0x20000000
|
|
+/** DFEV0, Channel 1 General Purpose Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_DFEV0_2GP 0x10000000
|
|
+/** DFEV0, Channel 1 Receive Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_DFEV0_2RX 0x08000000
|
|
+/** DFEV0, Channel 1 Transmit Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_DFEV0_2TX 0x04000000
|
|
+/** GPTC Timer/Counter 3B Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_GPTC_TC3B 0x00200000
|
|
+/** GPTC Timer/Counter 3A Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_GPTC_TC3A 0x00100000
|
|
+/** GPTC Timer/Counter 2B Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_GPTC_TC2B 0x00080000
|
|
+/** GPTC Timer/Counter 2A Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_GPTC_TC2A 0x00040000
|
|
+/** GPTC Timer/Counter 1B Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_GPTC_TC1B 0x00020000
|
|
+/** GPTC Timer/Counter 1A Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_GPTC_TC1A 0x00010000
|
|
+/** ASC1 Soft Flow Control Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_ASC1_SFC 0x00008000
|
|
+/** ASC1 Modem Status Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_ASC1_MS 0x00004000
|
|
+/** ASC1 Autobaud Detection Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_ASC1_ABDET 0x00002000
|
|
+/** ASC1 Autobaud Start Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_ASC1_ABST 0x00001000
|
|
+/** ASC1 Transmit Buffer Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_ASC1_TB 0x00000800
|
|
+/** ASC1 Error Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_ASC1_E 0x00000400
|
|
+/** ASC1 Receive Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_ASC1_R 0x00000200
|
|
+/** ASC1 Transmit Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_ASC1_T 0x00000100
|
|
+/** ASC0 Soft Flow Control Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_ASC0_SFC 0x00000080
|
|
+/** ASC1 Modem Status Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_ASC0_MS 0x00000040
|
|
+/** ASC0 Autobaud Detection Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_ASC0_ABDET 0x00000020
|
|
+/** ASC0 Autobaud Start Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_ASC0_ABST 0x00000010
|
|
+/** ASC0 Transmit Buffer Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_ASC0_TB 0x00000008
|
|
+/** ASC0 Error Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_ASC0_E 0x00000004
|
|
+/** ASC0 Receive Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_ASC0_R 0x00000002
|
|
+/** ASC0 Transmit Interrupt
|
|
+ Software control for the corresponding bit in the IM3_ISR register. */
|
|
+#define ICU0_IM3_IRSR_ASC0_T 0x00000001
|
|
+
|
|
+/* Fields of "IM3 Interrupt Mode Register" */
|
|
+/** DFEV0, Channel 0 General Purpose Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_DFEV0_1GP 0x80000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_DFEV0_1GP_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_DFEV0_1GP_DIR 0x80000000
|
|
+/** DFEV0, Channel 0 Receive Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_DFEV0_1RX 0x40000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_DFEV0_1RX_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_DFEV0_1RX_DIR 0x40000000
|
|
+/** DFEV0, Channel 0 Transmit Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_DFEV0_1TX 0x20000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_DFEV0_1TX_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_DFEV0_1TX_DIR 0x20000000
|
|
+/** DFEV0, Channel 1 General Purpose Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_DFEV0_2GP 0x10000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_DFEV0_2GP_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_DFEV0_2GP_DIR 0x10000000
|
|
+/** DFEV0, Channel 1 Receive Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_DFEV0_2RX 0x08000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_DFEV0_2RX_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_DFEV0_2RX_DIR 0x08000000
|
|
+/** DFEV0, Channel 1 Transmit Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_DFEV0_2TX 0x04000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_DFEV0_2TX_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_DFEV0_2TX_DIR 0x04000000
|
|
+/** GPTC Timer/Counter 3B Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_GPTC_TC3B 0x00200000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_GPTC_TC3B_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_GPTC_TC3B_DIR 0x00200000
|
|
+/** GPTC Timer/Counter 3A Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_GPTC_TC3A 0x00100000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_GPTC_TC3A_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_GPTC_TC3A_DIR 0x00100000
|
|
+/** GPTC Timer/Counter 2B Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_GPTC_TC2B 0x00080000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_GPTC_TC2B_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_GPTC_TC2B_DIR 0x00080000
|
|
+/** GPTC Timer/Counter 2A Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_GPTC_TC2A 0x00040000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_GPTC_TC2A_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_GPTC_TC2A_DIR 0x00040000
|
|
+/** GPTC Timer/Counter 1B Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_GPTC_TC1B 0x00020000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_GPTC_TC1B_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_GPTC_TC1B_DIR 0x00020000
|
|
+/** GPTC Timer/Counter 1A Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_GPTC_TC1A 0x00010000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_GPTC_TC1A_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_GPTC_TC1A_DIR 0x00010000
|
|
+/** ASC1 Soft Flow Control Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC1_SFC 0x00008000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_ASC1_SFC_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC1_SFC_DIR 0x00008000
|
|
+/** ASC1 Modem Status Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC1_MS 0x00004000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_ASC1_MS_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC1_MS_DIR 0x00004000
|
|
+/** ASC1 Autobaud Detection Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC1_ABDET 0x00002000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_ASC1_ABDET_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC1_ABDET_DIR 0x00002000
|
|
+/** ASC1 Autobaud Start Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC1_ABST 0x00001000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_ASC1_ABST_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC1_ABST_DIR 0x00001000
|
|
+/** ASC1 Transmit Buffer Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC1_TB 0x00000800
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_ASC1_TB_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC1_TB_DIR 0x00000800
|
|
+/** ASC1 Error Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC1_E 0x00000400
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_ASC1_E_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC1_E_DIR 0x00000400
|
|
+/** ASC1 Receive Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC1_R 0x00000200
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_ASC1_R_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC1_R_DIR 0x00000200
|
|
+/** ASC1 Transmit Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC1_T 0x00000100
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_ASC1_T_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC1_T_DIR 0x00000100
|
|
+/** ASC0 Soft Flow Control Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC0_SFC 0x00000080
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_ASC0_SFC_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC0_SFC_DIR 0x00000080
|
|
+/** ASC1 Modem Status Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC0_MS 0x00000040
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_ASC0_MS_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC0_MS_DIR 0x00000040
|
|
+/** ASC0 Autobaud Detection Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC0_ABDET 0x00000020
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_ASC0_ABDET_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC0_ABDET_DIR 0x00000020
|
|
+/** ASC0 Autobaud Start Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC0_ABST 0x00000010
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_ASC0_ABST_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC0_ABST_DIR 0x00000010
|
|
+/** ASC0 Transmit Buffer Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC0_TB 0x00000008
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_ASC0_TB_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC0_TB_DIR 0x00000008
|
|
+/** ASC0 Error Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC0_E 0x00000004
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_ASC0_E_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC0_E_DIR 0x00000004
|
|
+/** ASC0 Receive Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC0_R 0x00000002
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_ASC0_R_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC0_R_DIR 0x00000002
|
|
+/** ASC0 Transmit Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC0_T 0x00000001
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM3_IMR_ASC0_T_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM3_IMR_ASC0_T_DIR 0x00000001
|
|
+
|
|
+/* Fields of "IM4 Interrupt Status Register" */
|
|
+/** VPE0 Performance Monitoring Counter Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_VPE0_PMCIR 0x80000000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_VPE0_PMCIR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_VPE0_PMCIR_INTACK 0x80000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_VPE0_PMCIR_INTOCC 0x80000000
|
|
+/** VPE0 Error Level Flag Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_VPE0_ERL 0x40000000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_VPE0_ERL_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_VPE0_ERL_INTACK 0x40000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_VPE0_ERL_INTOCC 0x40000000
|
|
+/** VPE0 Exception Level Flag Interrupt
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_VPE0_EXL 0x20000000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_VPE0_EXL_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_VPE0_EXL_INTACK 0x20000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_VPE0_EXL_INTOCC 0x20000000
|
|
+/** MPS Bin. Sem Interrupt to VPE0
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_MPS_IR8 0x00400000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_MPS_IR8_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_MPS_IR8_INTACK 0x00400000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_MPS_IR8_INTOCC 0x00400000
|
|
+/** MPS Global Interrupt to VPE0
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_MPS_IR7 0x00200000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_MPS_IR7_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_MPS_IR7_INTACK 0x00200000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_MPS_IR7_INTOCC 0x00200000
|
|
+/** MPS Status Interrupt #6 (VPE1 to VPE0)
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_MPS_IR6 0x00100000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_MPS_IR6_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_MPS_IR6_INTACK 0x00100000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_MPS_IR6_INTOCC 0x00100000
|
|
+/** MPS Status Interrupt #5 (VPE1 to VPE0)
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_MPS_IR5 0x00080000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_MPS_IR5_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_MPS_IR5_INTACK 0x00080000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_MPS_IR5_INTOCC 0x00080000
|
|
+/** MPS Status Interrupt #4 (VPE1 to VPE0)
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_MPS_IR4 0x00040000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_MPS_IR4_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_MPS_IR4_INTACK 0x00040000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_MPS_IR4_INTOCC 0x00040000
|
|
+/** MPS Status Interrupt #3 (VPE1 to VPE0)
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_MPS_IR3 0x00020000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_MPS_IR3_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_MPS_IR3_INTACK 0x00020000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_MPS_IR3_INTOCC 0x00020000
|
|
+/** MPS Status Interrupt #2 (VPE1 to VPE0)
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_MPS_IR2 0x00010000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_MPS_IR2_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_MPS_IR2_INTACK 0x00010000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_MPS_IR2_INTOCC 0x00010000
|
|
+/** MPS Status Interrupt #1 (VPE1 to VPE0)
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_MPS_IR1 0x00008000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_MPS_IR1_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_MPS_IR1_INTACK 0x00008000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_MPS_IR1_INTOCC 0x00008000
|
|
+/** MPS Status Interrupt #0 (VPE1 to VPE0)
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_MPS_IR0 0x00004000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_MPS_IR0_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_MPS_IR0_INTACK 0x00004000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_MPS_IR0_INTOCC 0x00004000
|
|
+/** TMU Error
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_TMU_ERR 0x00001000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_TMU_ERR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_TMU_ERR_INTACK 0x00001000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_TMU_ERR_INTOCC 0x00001000
|
|
+/** FSQM Error
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_FSQM_ERR 0x00000800
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_FSQM_ERR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_FSQM_ERR_INTACK 0x00000800
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_FSQM_ERR_INTOCC 0x00000800
|
|
+/** IQM Error
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_IQM_ERR 0x00000400
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_IQM_ERR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_IQM_ERR_INTACK 0x00000400
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_IQM_ERR_INTOCC 0x00000400
|
|
+/** OCTRLG Error
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_OCTRLG_ERR 0x00000200
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_OCTRLG_ERR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_OCTRLG_ERR_INTACK 0x00000200
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_OCTRLG_ERR_INTOCC 0x00000200
|
|
+/** ICTRLG Error
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_ICTRLG_ERR 0x00000100
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_ICTRLG_ERR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_ICTRLG_ERR_INTACK 0x00000100
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_ICTRLG_ERR_INTOCC 0x00000100
|
|
+/** OCTRLL 3 Error
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_OCTRLL3_ERR 0x00000080
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_OCTRLL3_ERR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_OCTRLL3_ERR_INTACK 0x00000080
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_OCTRLL3_ERR_INTOCC 0x00000080
|
|
+/** OCTRLL 2 Error
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_OCTRLL2_ERR 0x00000040
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_OCTRLL2_ERR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_OCTRLL2_ERR_INTACK 0x00000040
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_OCTRLL2_ERR_INTOCC 0x00000040
|
|
+/** OCTRLL 1 Error
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_OCTRLL1_ERR 0x00000020
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_OCTRLL1_ERR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_OCTRLL1_ERR_INTACK 0x00000020
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_OCTRLL1_ERR_INTOCC 0x00000020
|
|
+/** OCTRLL 0 Error
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_OCTRLL0_ERR 0x00000010
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_OCTRLL0_ERR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_OCTRLL0_ERR_INTACK 0x00000010
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_OCTRLL0_ERR_INTOCC 0x00000010
|
|
+/** ICTRLL 3 Error
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_ICTRLL3_ERR 0x00000008
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_ICTRLL3_ERR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_ICTRLL3_ERR_INTACK 0x00000008
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_ICTRLL3_ERR_INTOCC 0x00000008
|
|
+/** ICTRLL 2 Error
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_ICTRLL2_ERR 0x00000004
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_ICTRLL2_ERR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_ICTRLL2_ERR_INTACK 0x00000004
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_ICTRLL2_ERR_INTOCC 0x00000004
|
|
+/** ICTRLL 1 Error
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_ICTRLL1_ERR 0x00000002
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_ICTRLL1_ERR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_ICTRLL1_ERR_INTACK 0x00000002
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_ICTRLL1_ERR_INTOCC 0x00000002
|
|
+/** ICTRLL 0 Error
|
|
+ This bit is an indirect interrupt. */
|
|
+#define ICU0_IM4_ISR_ICTRLL0_ERR 0x00000001
|
|
+/* Nothing
|
|
+#define ICU0_IM4_ISR_ICTRLL0_ERR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define ICU0_IM4_ISR_ICTRLL0_ERR_INTACK 0x00000001
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_ISR_ICTRLL0_ERR_INTOCC 0x00000001
|
|
+
|
|
+/* Fields of "IM4 Interrupt Enable Register" */
|
|
+/** VPE0 Performance Monitoring Counter Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_VPE0_PMCIR 0x80000000
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_VPE0_PMCIR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_VPE0_PMCIR_EN 0x80000000
|
|
+/** VPE0 Error Level Flag Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_VPE0_ERL 0x40000000
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_VPE0_ERL_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_VPE0_ERL_EN 0x40000000
|
|
+/** VPE0 Exception Level Flag Interrupt
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_VPE0_EXL 0x20000000
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_VPE0_EXL_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_VPE0_EXL_EN 0x20000000
|
|
+/** MPS Bin. Sem Interrupt to VPE0
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_MPS_IR8 0x00400000
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_MPS_IR8_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_MPS_IR8_EN 0x00400000
|
|
+/** MPS Global Interrupt to VPE0
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_MPS_IR7 0x00200000
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_MPS_IR7_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_MPS_IR7_EN 0x00200000
|
|
+/** MPS Status Interrupt #6 (VPE1 to VPE0)
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_MPS_IR6 0x00100000
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_MPS_IR6_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_MPS_IR6_EN 0x00100000
|
|
+/** MPS Status Interrupt #5 (VPE1 to VPE0)
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_MPS_IR5 0x00080000
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_MPS_IR5_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_MPS_IR5_EN 0x00080000
|
|
+/** MPS Status Interrupt #4 (VPE1 to VPE0)
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_MPS_IR4 0x00040000
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_MPS_IR4_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_MPS_IR4_EN 0x00040000
|
|
+/** MPS Status Interrupt #3 (VPE1 to VPE0)
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_MPS_IR3 0x00020000
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_MPS_IR3_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_MPS_IR3_EN 0x00020000
|
|
+/** MPS Status Interrupt #2 (VPE1 to VPE0)
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_MPS_IR2 0x00010000
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_MPS_IR2_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_MPS_IR2_EN 0x00010000
|
|
+/** MPS Status Interrupt #1 (VPE1 to VPE0)
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_MPS_IR1 0x00008000
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_MPS_IR1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_MPS_IR1_EN 0x00008000
|
|
+/** MPS Status Interrupt #0 (VPE1 to VPE0)
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_MPS_IR0 0x00004000
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_MPS_IR0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_MPS_IR0_EN 0x00004000
|
|
+/** TMU Error
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_TMU_ERR 0x00001000
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_TMU_ERR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_TMU_ERR_EN 0x00001000
|
|
+/** FSQM Error
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_FSQM_ERR 0x00000800
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_FSQM_ERR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_FSQM_ERR_EN 0x00000800
|
|
+/** IQM Error
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_IQM_ERR 0x00000400
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_IQM_ERR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_IQM_ERR_EN 0x00000400
|
|
+/** OCTRLG Error
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_OCTRLG_ERR 0x00000200
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_OCTRLG_ERR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_OCTRLG_ERR_EN 0x00000200
|
|
+/** ICTRLG Error
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_ICTRLG_ERR 0x00000100
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_ICTRLG_ERR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_ICTRLG_ERR_EN 0x00000100
|
|
+/** OCTRLL 3 Error
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_OCTRLL3_ERR 0x00000080
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_OCTRLL3_ERR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_OCTRLL3_ERR_EN 0x00000080
|
|
+/** OCTRLL 2 Error
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_OCTRLL2_ERR 0x00000040
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_OCTRLL2_ERR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_OCTRLL2_ERR_EN 0x00000040
|
|
+/** OCTRLL 1 Error
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_OCTRLL1_ERR 0x00000020
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_OCTRLL1_ERR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_OCTRLL1_ERR_EN 0x00000020
|
|
+/** OCTRLL 0 Error
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_OCTRLL0_ERR 0x00000010
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_OCTRLL0_ERR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_OCTRLL0_ERR_EN 0x00000010
|
|
+/** ICTRLL 3 Error
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_ICTRLL3_ERR 0x00000008
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_ICTRLL3_ERR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_ICTRLL3_ERR_EN 0x00000008
|
|
+/** ICTRLL 2 Error
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_ICTRLL2_ERR 0x00000004
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_ICTRLL2_ERR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_ICTRLL2_ERR_EN 0x00000004
|
|
+/** ICTRLL 1 Error
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_ICTRLL1_ERR 0x00000002
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_ICTRLL1_ERR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_ICTRLL1_ERR_EN 0x00000002
|
|
+/** ICTRLL 0 Error
|
|
+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IER_ICTRLL0_ERR 0x00000001
|
|
+/* Disable
|
|
+#define ICU0_IM4_IER_ICTRLL0_ERR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define ICU0_IM4_IER_ICTRLL0_ERR_EN 0x00000001
|
|
+
|
|
+/* Fields of "IM4 Interrupt Output Status Register" */
|
|
+/** VPE0 Performance Monitoring Counter Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_VPE0_PMCIR 0x80000000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_VPE0_PMCIR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_VPE0_PMCIR_INTOCC 0x80000000
|
|
+/** VPE0 Error Level Flag Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_VPE0_ERL 0x40000000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_VPE0_ERL_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_VPE0_ERL_INTOCC 0x40000000
|
|
+/** VPE0 Exception Level Flag Interrupt
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_VPE0_EXL 0x20000000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_VPE0_EXL_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_VPE0_EXL_INTOCC 0x20000000
|
|
+/** MPS Bin. Sem Interrupt to VPE0
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_MPS_IR8 0x00400000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_MPS_IR8_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_MPS_IR8_INTOCC 0x00400000
|
|
+/** MPS Global Interrupt to VPE0
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_MPS_IR7 0x00200000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_MPS_IR7_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_MPS_IR7_INTOCC 0x00200000
|
|
+/** MPS Status Interrupt #6 (VPE1 to VPE0)
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_MPS_IR6 0x00100000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_MPS_IR6_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_MPS_IR6_INTOCC 0x00100000
|
|
+/** MPS Status Interrupt #5 (VPE1 to VPE0)
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_MPS_IR5 0x00080000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_MPS_IR5_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_MPS_IR5_INTOCC 0x00080000
|
|
+/** MPS Status Interrupt #4 (VPE1 to VPE0)
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_MPS_IR4 0x00040000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_MPS_IR4_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_MPS_IR4_INTOCC 0x00040000
|
|
+/** MPS Status Interrupt #3 (VPE1 to VPE0)
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_MPS_IR3 0x00020000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_MPS_IR3_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_MPS_IR3_INTOCC 0x00020000
|
|
+/** MPS Status Interrupt #2 (VPE1 to VPE0)
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_MPS_IR2 0x00010000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_MPS_IR2_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_MPS_IR2_INTOCC 0x00010000
|
|
+/** MPS Status Interrupt #1 (VPE1 to VPE0)
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_MPS_IR1 0x00008000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_MPS_IR1_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_MPS_IR1_INTOCC 0x00008000
|
|
+/** MPS Status Interrupt #0 (VPE1 to VPE0)
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_MPS_IR0 0x00004000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_MPS_IR0_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_MPS_IR0_INTOCC 0x00004000
|
|
+/** TMU Error
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_TMU_ERR 0x00001000
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_TMU_ERR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_TMU_ERR_INTOCC 0x00001000
|
|
+/** FSQM Error
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_FSQM_ERR 0x00000800
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_FSQM_ERR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_FSQM_ERR_INTOCC 0x00000800
|
|
+/** IQM Error
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_IQM_ERR 0x00000400
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_IQM_ERR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_IQM_ERR_INTOCC 0x00000400
|
|
+/** OCTRLG Error
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_OCTRLG_ERR 0x00000200
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_OCTRLG_ERR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_OCTRLG_ERR_INTOCC 0x00000200
|
|
+/** ICTRLG Error
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_ICTRLG_ERR 0x00000100
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_ICTRLG_ERR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_ICTRLG_ERR_INTOCC 0x00000100
|
|
+/** OCTRLL 3 Error
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_OCTRLL3_ERR 0x00000080
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_OCTRLL3_ERR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_OCTRLL3_ERR_INTOCC 0x00000080
|
|
+/** OCTRLL 2 Error
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_OCTRLL2_ERR 0x00000040
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_OCTRLL2_ERR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_OCTRLL2_ERR_INTOCC 0x00000040
|
|
+/** OCTRLL 1 Error
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_OCTRLL1_ERR 0x00000020
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_OCTRLL1_ERR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_OCTRLL1_ERR_INTOCC 0x00000020
|
|
+/** OCTRLL 0 Error
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_OCTRLL0_ERR 0x00000010
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_OCTRLL0_ERR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_OCTRLL0_ERR_INTOCC 0x00000010
|
|
+/** ICTRLL 3 Error
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_ICTRLL3_ERR 0x00000008
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_ICTRLL3_ERR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_ICTRLL3_ERR_INTOCC 0x00000008
|
|
+/** ICTRLL 2 Error
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_ICTRLL2_ERR 0x00000004
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_ICTRLL2_ERR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_ICTRLL2_ERR_INTOCC 0x00000004
|
|
+/** ICTRLL 1 Error
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_ICTRLL1_ERR 0x00000002
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_ICTRLL1_ERR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_ICTRLL1_ERR_INTOCC 0x00000002
|
|
+/** ICTRLL 0 Error
|
|
+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IOSR_ICTRLL0_ERR 0x00000001
|
|
+/* Nothing
|
|
+#define ICU0_IM4_IOSR_ICTRLL0_ERR_NULL 0x00000000 */
|
|
+/** Read: Interrupt occurred. */
|
|
+#define ICU0_IM4_IOSR_ICTRLL0_ERR_INTOCC 0x00000001
|
|
+
|
|
+/* Fields of "IM4 Interrupt Request Set Register" */
|
|
+/** VPE0 Performance Monitoring Counter Interrupt
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_VPE0_PMCIR 0x80000000
|
|
+/** VPE0 Error Level Flag Interrupt
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_VPE0_ERL 0x40000000
|
|
+/** VPE0 Exception Level Flag Interrupt
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_VPE0_EXL 0x20000000
|
|
+/** MPS Bin. Sem Interrupt to VPE0
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_MPS_IR8 0x00400000
|
|
+/** MPS Global Interrupt to VPE0
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_MPS_IR7 0x00200000
|
|
+/** MPS Status Interrupt #6 (VPE1 to VPE0)
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_MPS_IR6 0x00100000
|
|
+/** MPS Status Interrupt #5 (VPE1 to VPE0)
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_MPS_IR5 0x00080000
|
|
+/** MPS Status Interrupt #4 (VPE1 to VPE0)
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_MPS_IR4 0x00040000
|
|
+/** MPS Status Interrupt #3 (VPE1 to VPE0)
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_MPS_IR3 0x00020000
|
|
+/** MPS Status Interrupt #2 (VPE1 to VPE0)
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_MPS_IR2 0x00010000
|
|
+/** MPS Status Interrupt #1 (VPE1 to VPE0)
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_MPS_IR1 0x00008000
|
|
+/** MPS Status Interrupt #0 (VPE1 to VPE0)
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_MPS_IR0 0x00004000
|
|
+/** TMU Error
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_TMU_ERR 0x00001000
|
|
+/** FSQM Error
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_FSQM_ERR 0x00000800
|
|
+/** IQM Error
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_IQM_ERR 0x00000400
|
|
+/** OCTRLG Error
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_OCTRLG_ERR 0x00000200
|
|
+/** ICTRLG Error
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_ICTRLG_ERR 0x00000100
|
|
+/** OCTRLL 3 Error
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_OCTRLL3_ERR 0x00000080
|
|
+/** OCTRLL 2 Error
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_OCTRLL2_ERR 0x00000040
|
|
+/** OCTRLL 1 Error
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_OCTRLL1_ERR 0x00000020
|
|
+/** OCTRLL 0 Error
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_OCTRLL0_ERR 0x00000010
|
|
+/** ICTRLL 3 Error
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_ICTRLL3_ERR 0x00000008
|
|
+/** ICTRLL 2 Error
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_ICTRLL2_ERR 0x00000004
|
|
+/** ICTRLL 1 Error
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_ICTRLL1_ERR 0x00000002
|
|
+/** ICTRLL 0 Error
|
|
+ Software control for the corresponding bit in the IM4_ISR register. */
|
|
+#define ICU0_IM4_IRSR_ICTRLL0_ERR 0x00000001
|
|
+
|
|
+/* Fields of "IM4 Interrupt Mode Register" */
|
|
+/** VPE0 Performance Monitoring Counter Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_VPE0_PMCIR 0x80000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_VPE0_PMCIR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_VPE0_PMCIR_DIR 0x80000000
|
|
+/** VPE0 Error Level Flag Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_VPE0_ERL 0x40000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_VPE0_ERL_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_VPE0_ERL_DIR 0x40000000
|
|
+/** VPE0 Exception Level Flag Interrupt
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_VPE0_EXL 0x20000000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_VPE0_EXL_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_VPE0_EXL_DIR 0x20000000
|
|
+/** MPS Bin. Sem Interrupt to VPE0
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_MPS_IR8 0x00400000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_MPS_IR8_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_MPS_IR8_DIR 0x00400000
|
|
+/** MPS Global Interrupt to VPE0
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_MPS_IR7 0x00200000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_MPS_IR7_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_MPS_IR7_DIR 0x00200000
|
|
+/** MPS Status Interrupt #6 (VPE1 to VPE0)
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_MPS_IR6 0x00100000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_MPS_IR6_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_MPS_IR6_DIR 0x00100000
|
|
+/** MPS Status Interrupt #5 (VPE1 to VPE0)
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_MPS_IR5 0x00080000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_MPS_IR5_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_MPS_IR5_DIR 0x00080000
|
|
+/** MPS Status Interrupt #4 (VPE1 to VPE0)
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_MPS_IR4 0x00040000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_MPS_IR4_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_MPS_IR4_DIR 0x00040000
|
|
+/** MPS Status Interrupt #3 (VPE1 to VPE0)
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_MPS_IR3 0x00020000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_MPS_IR3_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_MPS_IR3_DIR 0x00020000
|
|
+/** MPS Status Interrupt #2 (VPE1 to VPE0)
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_MPS_IR2 0x00010000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_MPS_IR2_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_MPS_IR2_DIR 0x00010000
|
|
+/** MPS Status Interrupt #1 (VPE1 to VPE0)
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_MPS_IR1 0x00008000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_MPS_IR1_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_MPS_IR1_DIR 0x00008000
|
|
+/** MPS Status Interrupt #0 (VPE1 to VPE0)
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_MPS_IR0 0x00004000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_MPS_IR0_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_MPS_IR0_DIR 0x00004000
|
|
+/** TMU Error
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_TMU_ERR 0x00001000
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_TMU_ERR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_TMU_ERR_DIR 0x00001000
|
|
+/** FSQM Error
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_FSQM_ERR 0x00000800
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_FSQM_ERR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_FSQM_ERR_DIR 0x00000800
|
|
+/** IQM Error
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_IQM_ERR 0x00000400
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_IQM_ERR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_IQM_ERR_DIR 0x00000400
|
|
+/** OCTRLG Error
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_OCTRLG_ERR 0x00000200
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_OCTRLG_ERR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_OCTRLG_ERR_DIR 0x00000200
|
|
+/** ICTRLG Error
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_ICTRLG_ERR 0x00000100
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_ICTRLG_ERR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_ICTRLG_ERR_DIR 0x00000100
|
|
+/** OCTRLL 3 Error
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_OCTRLL3_ERR 0x00000080
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_OCTRLL3_ERR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_OCTRLL3_ERR_DIR 0x00000080
|
|
+/** OCTRLL 2 Error
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_OCTRLL2_ERR 0x00000040
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_OCTRLL2_ERR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_OCTRLL2_ERR_DIR 0x00000040
|
|
+/** OCTRLL 1 Error
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_OCTRLL1_ERR 0x00000020
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_OCTRLL1_ERR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_OCTRLL1_ERR_DIR 0x00000020
|
|
+/** OCTRLL 0 Error
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_OCTRLL0_ERR 0x00000010
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_OCTRLL0_ERR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_OCTRLL0_ERR_DIR 0x00000010
|
|
+/** ICTRLL 3 Error
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_ICTRLL3_ERR 0x00000008
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_ICTRLL3_ERR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_ICTRLL3_ERR_DIR 0x00000008
|
|
+/** ICTRLL 2 Error
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_ICTRLL2_ERR 0x00000004
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_ICTRLL2_ERR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_ICTRLL2_ERR_DIR 0x00000004
|
|
+/** ICTRLL 1 Error
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_ICTRLL1_ERR 0x00000002
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_ICTRLL1_ERR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_ICTRLL1_ERR_DIR 0x00000002
|
|
+/** ICTRLL 0 Error
|
|
+ Type of interrupt. */
|
|
+#define ICU0_IM4_IMR_ICTRLL0_ERR 0x00000001
|
|
+/* Indirect Interrupt.
|
|
+#define ICU0_IM4_IMR_ICTRLL0_ERR_IND 0x00000000 */
|
|
+/** Direct Interrupt. */
|
|
+#define ICU0_IM4_IMR_ICTRLL0_ERR_DIR 0x00000001
|
|
+
|
|
+/* Fields of "ICU Interrupt Vector Register (5 bit variant)" */
|
|
+/** IM4 Interrupt Vector Value
|
|
+ Returns the highest priority pending interrupt vector. */
|
|
+#define ICU0_ICU_IVEC_IM4_vec_MASK 0x01F00000
|
|
+/** field offset */
|
|
+#define ICU0_ICU_IVEC_IM4_vec_OFFSET 20
|
|
+/** Interrupt pending at bit 31 or no pending interrupt */
|
|
+#define ICU0_ICU_IVEC_IM4_vec_NOINTorBit31 0x00000000
|
|
+/** Interrupt pending at bit 0. */
|
|
+#define ICU0_ICU_IVEC_IM4_vec_BIT0 0x00100000
|
|
+/** Interrupt pending at bit 1. */
|
|
+#define ICU0_ICU_IVEC_IM4_vec_BIT1 0x00200000
|
|
+/** Interrupt pending at bit 30. */
|
|
+#define ICU0_ICU_IVEC_IM4_vec_BIT30 0x01F00000
|
|
+/** IM3 Interrupt Vector Value
|
|
+ Returns the highest priority pending interrupt vector. */
|
|
+#define ICU0_ICU_IVEC_IM3_vec_MASK 0x000F8000
|
|
+/** field offset */
|
|
+#define ICU0_ICU_IVEC_IM3_vec_OFFSET 15
|
|
+/** Interrupt pending at bit 31 or no pending interrupt */
|
|
+#define ICU0_ICU_IVEC_IM3_vec_NOINTorBit31 0x00000000
|
|
+/** Interrupt pending at bit 0. */
|
|
+#define ICU0_ICU_IVEC_IM3_vec_BIT0 0x00008000
|
|
+/** Interrupt pending at bit 1. */
|
|
+#define ICU0_ICU_IVEC_IM3_vec_BIT1 0x00010000
|
|
+/** Interrupt pending at bit 30. */
|
|
+#define ICU0_ICU_IVEC_IM3_vec_BIT30 0x000F8000
|
|
+/** IM2 Interrupt Vector Value
|
|
+ Returns the highest priority pending interrupt vector. */
|
|
+#define ICU0_ICU_IVEC_IM2_vec_MASK 0x00007C00
|
|
+/** field offset */
|
|
+#define ICU0_ICU_IVEC_IM2_vec_OFFSET 10
|
|
+/** Interrupt pending at bit 31 or no pending interrupt */
|
|
+#define ICU0_ICU_IVEC_IM2_vec_NOINTorBit31 0x00000000
|
|
+/** Interrupt pending at bit 0. */
|
|
+#define ICU0_ICU_IVEC_IM2_vec_BIT0 0x00000400
|
|
+/** Interrupt pending at bit 1. */
|
|
+#define ICU0_ICU_IVEC_IM2_vec_BIT1 0x00000800
|
|
+/** Interrupt pending at bit 30. */
|
|
+#define ICU0_ICU_IVEC_IM2_vec_BIT30 0x00007C00
|
|
+/** IM1 Interrupt Vector Value
|
|
+ Returns the highest priority pending interrupt vector. */
|
|
+#define ICU0_ICU_IVEC_IM1_vec_MASK 0x000003E0
|
|
+/** field offset */
|
|
+#define ICU0_ICU_IVEC_IM1_vec_OFFSET 5
|
|
+/** Interrupt pending at bit 31 or no pending interrupt */
|
|
+#define ICU0_ICU_IVEC_IM1_vec_NOINTorBit31 0x00000000
|
|
+/** Interrupt pending at bit 0. */
|
|
+#define ICU0_ICU_IVEC_IM1_vec_BIT0 0x00000020
|
|
+/** Interrupt pending at bit 1. */
|
|
+#define ICU0_ICU_IVEC_IM1_vec_BIT1 0x00000040
|
|
+/** Interrupt pending at bit 30. */
|
|
+#define ICU0_ICU_IVEC_IM1_vec_BIT30 0x000003E0
|
|
+/** IM0 Interrupt Vector Value
|
|
+ Returns the highest priority pending interrupt vector. */
|
|
+#define ICU0_ICU_IVEC_IM0_vec_MASK 0x0000001F
|
|
+/** field offset */
|
|
+#define ICU0_ICU_IVEC_IM0_vec_OFFSET 0
|
|
+/** Interrupt pending at bit 31 or no pending interrupt */
|
|
+#define ICU0_ICU_IVEC_IM0_vec_NOINTorBit31 0x00000000
|
|
+/** Interrupt pending at bit 0. */
|
|
+#define ICU0_ICU_IVEC_IM0_vec_BIT0 0x00000001
|
|
+/** Interrupt pending at bit 1. */
|
|
+#define ICU0_ICU_IVEC_IM0_vec_BIT1 0x00000002
|
|
+/** Interrupt pending at bit 30. */
|
|
+#define ICU0_ICU_IVEC_IM0_vec_BIT30 0x0000001F
|
|
+
|
|
+/* Fields of "ICU Interrupt Vector Register (6 bit variant)" */
|
|
+/** IM4 Interrupt Vector Value
|
|
+ Returns the highest priority pending interrupt vector. */
|
|
+#define ICU0_ICU_IVEC_6_IM4_vec_MASK 0x3F000000
|
|
+/** field offset */
|
|
+#define ICU0_ICU_IVEC_6_IM4_vec_OFFSET 24
|
|
+/** No pending interrupt */
|
|
+#define ICU0_ICU_IVEC_6_IM4_vec_NOINT 0x00000000
|
|
+/** Interrupt pending at bit 0. */
|
|
+#define ICU0_ICU_IVEC_6_IM4_vec_BIT0 0x01000000
|
|
+/** Interrupt pending at bit 1. */
|
|
+#define ICU0_ICU_IVEC_6_IM4_vec_BIT1 0x02000000
|
|
+/** Interrupt pending at bit 30. */
|
|
+#define ICU0_ICU_IVEC_6_IM4_vec_BIT30 0x1F000000
|
|
+/** Interrupt pending at bit 31. */
|
|
+#define ICU0_ICU_IVEC_6_IM4_vec_BIT31 0x20000000
|
|
+/** IM3 Interrupt Vector Value
|
|
+ Returns the highest priority pending interrupt vector. */
|
|
+#define ICU0_ICU_IVEC_6_IM3_vec_MASK 0x00FC0000
|
|
+/** field offset */
|
|
+#define ICU0_ICU_IVEC_6_IM3_vec_OFFSET 18
|
|
+/** No pending interrupt */
|
|
+#define ICU0_ICU_IVEC_6_IM3_vec_NOINT 0x00000000
|
|
+/** Interrupt pending at bit 0. */
|
|
+#define ICU0_ICU_IVEC_6_IM3_vec_BIT0 0x00040000
|
|
+/** Interrupt pending at bit 1. */
|
|
+#define ICU0_ICU_IVEC_6_IM3_vec_BIT1 0x00080000
|
|
+/** Interrupt pending at bit 30. */
|
|
+#define ICU0_ICU_IVEC_6_IM3_vec_BIT30 0x007C0000
|
|
+/** Interrupt pending at bit 31. */
|
|
+#define ICU0_ICU_IVEC_6_IM3_vec_BIT31 0x00800000
|
|
+/** IM2 Interrupt Vector Value
|
|
+ Returns the highest priority pending interrupt vector. */
|
|
+#define ICU0_ICU_IVEC_6_IM2_vec_MASK 0x0003F000
|
|
+/** field offset */
|
|
+#define ICU0_ICU_IVEC_6_IM2_vec_OFFSET 12
|
|
+/** No pending interrupt */
|
|
+#define ICU0_ICU_IVEC_6_IM2_vec_NOINT 0x00000000
|
|
+/** Interrupt pending at bit 0. */
|
|
+#define ICU0_ICU_IVEC_6_IM2_vec_BIT0 0x00001000
|
|
+/** Interrupt pending at bit 1. */
|
|
+#define ICU0_ICU_IVEC_6_IM2_vec_BIT1 0x00002000
|
|
+/** Interrupt pending at bit 30. */
|
|
+#define ICU0_ICU_IVEC_6_IM2_vec_BIT30 0x0001F000
|
|
+/** Interrupt pending at bit 31. */
|
|
+#define ICU0_ICU_IVEC_6_IM2_vec_BIT31 0x00020000
|
|
+/** IM1 Interrupt Vector Value
|
|
+ Returns the highest priority pending interrupt vector. */
|
|
+#define ICU0_ICU_IVEC_6_IM1_vec_MASK 0x00000FC0
|
|
+/** field offset */
|
|
+#define ICU0_ICU_IVEC_6_IM1_vec_OFFSET 6
|
|
+/** No pending interrupt */
|
|
+#define ICU0_ICU_IVEC_6_IM1_vec_NOINT 0x00000000
|
|
+/** Interrupt pending at bit 0. */
|
|
+#define ICU0_ICU_IVEC_6_IM1_vec_BIT0 0x00000040
|
|
+/** Interrupt pending at bit 1. */
|
|
+#define ICU0_ICU_IVEC_6_IM1_vec_BIT1 0x00000080
|
|
+/** Interrupt pending at bit 30. */
|
|
+#define ICU0_ICU_IVEC_6_IM1_vec_BIT30 0x000007C0
|
|
+/** Interrupt pending at bit 31. */
|
|
+#define ICU0_ICU_IVEC_6_IM1_vec_BIT31 0x00000800
|
|
+/** IM0 Interrupt Vector Value
|
|
+ Returns the highest priority pending interrupt vector. */
|
|
+#define ICU0_ICU_IVEC_6_IM0_vec_MASK 0x0000003F
|
|
+/** field offset */
|
|
+#define ICU0_ICU_IVEC_6_IM0_vec_OFFSET 0
|
|
+/** No pending interrupt */
|
|
+#define ICU0_ICU_IVEC_6_IM0_vec_NOINT 0x00000000
|
|
+/** Interrupt pending at bit 0. */
|
|
+#define ICU0_ICU_IVEC_6_IM0_vec_BIT0 0x00000001
|
|
+/** Interrupt pending at bit 1. */
|
|
+#define ICU0_ICU_IVEC_6_IM0_vec_BIT1 0x00000002
|
|
+/** Interrupt pending at bit 30. */
|
|
+#define ICU0_ICU_IVEC_6_IM0_vec_BIT30 0x0000001F
|
|
+/** Interrupt pending at bit 31. */
|
|
+#define ICU0_ICU_IVEC_6_IM0_vec_BIT31 0x00000020
|
|
+
|
|
+/*! @} */ /* ICU0_REGISTER */
|
|
+
|
|
+#endif /* _icu0_reg_h */
|
|
--- /dev/null
|
|
+++ b/arch/mips/include/asm/mach-lantiq/falcon/status_reg.h
|
|
@@ -0,0 +1,529 @@
|
|
+/******************************************************************************
|
|
+
|
|
+ Copyright (c) 2010
|
|
+ Lantiq Deutschland GmbH
|
|
+
|
|
+ For licensing information, see the file 'LICENSE' in the root folder of
|
|
+ this software module.
|
|
+
|
|
+******************************************************************************/
|
|
+
|
|
+#ifndef _status_reg_h
|
|
+#define _status_reg_h
|
|
+
|
|
+/** \addtogroup STATUS_REGISTER
|
|
+ @{
|
|
+*/
|
|
+/* access macros */
|
|
+#define status_r32(reg) reg_r32(&status->reg)
|
|
+#define status_w32(val, reg) reg_w32(val, &status->reg)
|
|
+#define status_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &status->reg)
|
|
+#define status_r32_table(reg, idx) reg_r32_table(status->reg, idx)
|
|
+#define status_w32_table(val, reg, idx) reg_w32_table(val, status->reg, idx)
|
|
+#define status_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, status->reg, idx)
|
|
+#define status_adr_table(reg, idx) adr_table(status->reg, idx)
|
|
+
|
|
+
|
|
+/** STATUS register structure */
|
|
+struct gpon_reg_status
|
|
+{
|
|
+ /** Reserved */
|
|
+ unsigned int res_0[3]; /* 0x00000000 */
|
|
+ /** Chip Identification Register */
|
|
+ unsigned int chipid; /* 0x0000000C */
|
|
+ /** Chip Location Register
|
|
+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
|
|
+ unsigned int chiploc; /* 0x00000010 */
|
|
+ /** Redundancy register
|
|
+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
|
|
+ unsigned int red0; /* 0x00000014 */
|
|
+ /** Redundancy register
|
|
+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
|
|
+ unsigned int red1; /* 0x00000018 */
|
|
+ /** Redundancy register
|
|
+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
|
|
+ unsigned int red2; /* 0x0000001C */
|
|
+ /** Redundancy register
|
|
+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
|
|
+ unsigned int red3; /* 0x00000020 */
|
|
+ /** Redundancy register
|
|
+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
|
|
+ unsigned int red4; /* 0x00000024 */
|
|
+ /** Redundancy register
|
|
+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
|
|
+ unsigned int red5; /* 0x00000028 */
|
|
+ /** Redundancy register
|
|
+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
|
|
+ unsigned int red6; /* 0x0000002C */
|
|
+ /** Redundancy register
|
|
+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
|
|
+ unsigned int red7; /* 0x00000030 */
|
|
+ /** Redundancy register
|
|
+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
|
|
+ unsigned int red8; /* 0x00000034 */
|
|
+ /** SPARE fuse register 0
|
|
+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
|
|
+ unsigned int fuse0; /* 0x00000038 */
|
|
+ /** Fuses for Analog modules
|
|
+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
|
|
+ unsigned int analog; /* 0x0000003C */
|
|
+ /** Configuration fuses for drivers and pll
|
|
+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
|
|
+ unsigned int config; /* 0x00000040 */
|
|
+ /** SPARE fuse register 1
|
|
+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */
|
|
+ unsigned int fuse1; /* 0x00000044 */
|
|
+ /** Configuration for sbs0 rambist */
|
|
+ unsigned int mbcfg; /* 0x00000048 */
|
|
+ /** sbs0 bist result and debug data */
|
|
+ unsigned int mbdata; /* 0x0000004C */
|
|
+ /** Reserved */
|
|
+ unsigned int res_1[12]; /* 0x00000050 */
|
|
+};
|
|
+
|
|
+
|
|
+/* Fields of "Chip Identification Register" */
|
|
+/** Chip Version Number
|
|
+ Version number */
|
|
+#define STATUS_CHIPID_VERSION_MASK 0xF0000000
|
|
+/** field offset */
|
|
+#define STATUS_CHIPID_VERSION_OFFSET 28
|
|
+/** Part Number, Constant Part
|
|
+ The Part Number is fixed to 016Bhex. */
|
|
+#define STATUS_CHIPID_PARTNR_MASK 0x0FFFF000
|
|
+/** field offset */
|
|
+#define STATUS_CHIPID_PARTNR_OFFSET 12
|
|
+/** Manufacturer ID
|
|
+ The value of bit field MANID is fixed to 41hex as configured in the JTAG ID register. The JEDEC normalized manufacturer code for Infineon Technologies is C1hex */
|
|
+#define STATUS_CHIPID_MANID_MASK 0x00000FFE
|
|
+/** field offset */
|
|
+#define STATUS_CHIPID_MANID_OFFSET 1
|
|
+/** Constant bit
|
|
+ The value of bit field CONST1 is fixed to 1hex */
|
|
+#define STATUS_CHIPID_CONST1 0x00000001
|
|
+
|
|
+/* Fields of "Chip Location Register" */
|
|
+/** Chip Lot ID */
|
|
+#define STATUS_CHIPLOC_CHIPLOT_MASK 0xFFFF0000
|
|
+/** field offset */
|
|
+#define STATUS_CHIPLOC_CHIPLOT_OFFSET 16
|
|
+/** Chip X Coordinate */
|
|
+#define STATUS_CHIPLOC_CHIPX_MASK 0x0000FF00
|
|
+/** field offset */
|
|
+#define STATUS_CHIPLOC_CHIPX_OFFSET 8
|
|
+/** Chip Y Coordinate */
|
|
+#define STATUS_CHIPLOC_CHIPY_MASK 0x000000FF
|
|
+/** field offset */
|
|
+#define STATUS_CHIPLOC_CHIPY_OFFSET 0
|
|
+
|
|
+/* Fields of "Redundancy register" */
|
|
+/** Redundancy
|
|
+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
|
|
+#define STATUS_RED0_REDUNDANCY_MASK 0x0003FFFF
|
|
+/** field offset */
|
|
+#define STATUS_RED0_REDUNDANCY_OFFSET 0
|
|
+
|
|
+/* Fields of "Redundancy register" */
|
|
+/** Redundancy
|
|
+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
|
|
+#define STATUS_RED1_REDUNDANCY_MASK 0x0003FFFF
|
|
+/** field offset */
|
|
+#define STATUS_RED1_REDUNDANCY_OFFSET 0
|
|
+
|
|
+/* Fields of "Redundancy register" */
|
|
+/** Redundancy
|
|
+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
|
|
+#define STATUS_RED2_REDUNDANCY_MASK 0x0003FFFF
|
|
+/** field offset */
|
|
+#define STATUS_RED2_REDUNDANCY_OFFSET 0
|
|
+
|
|
+/* Fields of "Redundancy register" */
|
|
+/** Redundancy
|
|
+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
|
|
+#define STATUS_RED3_REDUNDANCY_MASK 0x0003FFFF
|
|
+/** field offset */
|
|
+#define STATUS_RED3_REDUNDANCY_OFFSET 0
|
|
+
|
|
+/* Fields of "Redundancy register" */
|
|
+/** Redundancy
|
|
+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
|
|
+#define STATUS_RED4_REDUNDANCY_MASK 0x0003FFFF
|
|
+/** field offset */
|
|
+#define STATUS_RED4_REDUNDANCY_OFFSET 0
|
|
+
|
|
+/* Fields of "Redundancy register" */
|
|
+/** Redundancy
|
|
+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
|
|
+#define STATUS_RED5_REDUNDANCY_MASK 0x0003FFFF
|
|
+/** field offset */
|
|
+#define STATUS_RED5_REDUNDANCY_OFFSET 0
|
|
+
|
|
+/* Fields of "Redundancy register" */
|
|
+/** Redundancy
|
|
+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
|
|
+#define STATUS_RED6_REDUNDANCY_MASK 0x0003FFFF
|
|
+/** field offset */
|
|
+#define STATUS_RED6_REDUNDANCY_OFFSET 0
|
|
+
|
|
+/* Fields of "Redundancy register" */
|
|
+/** Redundancy
|
|
+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
|
|
+#define STATUS_RED7_REDUNDANCY_MASK 0x0003FFFF
|
|
+/** field offset */
|
|
+#define STATUS_RED7_REDUNDANCY_OFFSET 0
|
|
+
|
|
+/* Fields of "Redundancy register" */
|
|
+/** Redundancy
|
|
+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */
|
|
+#define STATUS_RED8_REDUNDANCY_MASK 0x0003FFFF
|
|
+/** field offset */
|
|
+#define STATUS_RED8_REDUNDANCY_OFFSET 0
|
|
+
|
|
+/* Fields of "SPARE fuse register 0" */
|
|
+/** Soft fuse control
|
|
+ Controls whether the status block is in its softfused state or not. In the softfused state the values written via software are active effective. */
|
|
+#define STATUS_FUSE0_SFC 0x80000000
|
|
+/* Not selected
|
|
+#define STATUS_FUSE0_SFC_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define STATUS_FUSE0_SFC_SEL 0x80000000
|
|
+/** Soft control MBCFG
|
|
+ Controls whether mbist configuration can be overwritten or not from subsystem. If not selected jtag mbcfg register is source for software mbist configuration */
|
|
+#define STATUS_FUSE0_SC_MBCFG 0x40000000
|
|
+/* Not selected
|
|
+#define STATUS_FUSE0_SC_MBCFG_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define STATUS_FUSE0_SC_MBCFG_SEL 0x40000000
|
|
+/** spare fuse0
|
|
+ eFuses not assigned to hw/sw, can be used for future applications */
|
|
+#define STATUS_FUSE0_F0_MASK 0x3C000000
|
|
+/** field offset */
|
|
+#define STATUS_FUSE0_F0_OFFSET 26
|
|
+/** VCALMM20 Voltage Reference
|
|
+ Voltage Reference for calibration via R and constant current (20 uA) */
|
|
+#define STATUS_FUSE0_VCALMM20_MASK 0x03F00000
|
|
+/** field offset */
|
|
+#define STATUS_FUSE0_VCALMM20_OFFSET 20
|
|
+/** VCALMM100 Voltage Reference
|
|
+ Voltage Reference for calibration via R and constant current (100 uA) */
|
|
+#define STATUS_FUSE0_VCALMM100_MASK 0x000FC000
|
|
+/** field offset */
|
|
+#define STATUS_FUSE0_VCALMM100_OFFSET 14
|
|
+/** VCALMM400 Voltage Reference
|
|
+ Voltage Reference for calibration via R and constant current (400 uA) */
|
|
+#define STATUS_FUSE0_VCALMM400_MASK 0x00003F00
|
|
+/** field offset */
|
|
+#define STATUS_FUSE0_VCALMM400_OFFSET 8
|
|
+/** RCALMM R error correction
|
|
+ The resistance deviation from ideal R (1000 Ohm) */
|
|
+#define STATUS_FUSE0_RCALMM_MASK 0x000000FF
|
|
+/** field offset */
|
|
+#define STATUS_FUSE0_RCALMM_OFFSET 0
|
|
+
|
|
+/* Fields of "Fuses for Analog modules" */
|
|
+/** reserved Analog eFuses
|
|
+ Reserved Register contains information stored in eFuses needed for the analog modules */
|
|
+#define STATUS_ANALOG_A0_MASK 0xFF000000
|
|
+/** field offset */
|
|
+#define STATUS_ANALOG_A0_OFFSET 24
|
|
+/** Absolut Temperature
|
|
+ Temperature ERROR */
|
|
+#define STATUS_ANALOG_TEMPMM_MASK 0x00FC0000
|
|
+/** field offset */
|
|
+#define STATUS_ANALOG_TEMPMM_OFFSET 18
|
|
+/** Bias Voltage Generation
|
|
+ temperature dependency */
|
|
+#define STATUS_ANALOG_TBGP_MASK 0x00038000
|
|
+/** field offset */
|
|
+#define STATUS_ANALOG_TBGP_OFFSET 15
|
|
+/** Bias Voltage Generation
|
|
+ voltage dependency */
|
|
+#define STATUS_ANALOG_VBGP_MASK 0x00007000
|
|
+/** field offset */
|
|
+#define STATUS_ANALOG_VBGP_OFFSET 12
|
|
+/** Bias Current Generation */
|
|
+#define STATUS_ANALOG_IREFBGP_MASK 0x00000F00
|
|
+/** field offset */
|
|
+#define STATUS_ANALOG_IREFBGP_OFFSET 8
|
|
+/** Drive DAC Gain */
|
|
+#define STATUS_ANALOG_GAINDRIVEDAC_MASK 0x000000F0
|
|
+/** field offset */
|
|
+#define STATUS_ANALOG_GAINDRIVEDAC_OFFSET 4
|
|
+/** BIAS DAC Gain */
|
|
+#define STATUS_ANALOG_GAINBIASDAC_MASK 0x0000000F
|
|
+/** field offset */
|
|
+#define STATUS_ANALOG_GAINBIASDAC_OFFSET 0
|
|
+
|
|
+/* Fields of "Configuration fuses for drivers and pll" */
|
|
+/** ddr PU driver
|
|
+ ddr pullup driver strength adjustment */
|
|
+#define STATUS_CONFIG_DDRPU_MASK 0xC0000000
|
|
+/** field offset */
|
|
+#define STATUS_CONFIG_DDRPU_OFFSET 30
|
|
+/** ddr PD driver
|
|
+ ddr pulldown driver strength adjustment */
|
|
+#define STATUS_CONFIG_DDRPD_MASK 0x30000000
|
|
+/** field offset */
|
|
+#define STATUS_CONFIG_DDRPD_OFFSET 28
|
|
+/** Authentification Unit enable
|
|
+ This bit can only be set via eFuse and enables the authentification unit. */
|
|
+#define STATUS_CONFIG_SHA1EN 0x08000000
|
|
+/* Not selected
|
|
+#define STATUS_CONFIG_SHA1EN_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define STATUS_CONFIG_SHA1EN_SEL 0x08000000
|
|
+/** Encryption Unit enable
|
|
+ This bit can only be set via eFuse and enables the encryption unit. */
|
|
+#define STATUS_CONFIG_AESEN 0x04000000
|
|
+/* Not selected
|
|
+#define STATUS_CONFIG_AESEN_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define STATUS_CONFIG_AESEN_SEL 0x04000000
|
|
+/** Subversion Number
|
|
+ The subversion number has no direct effect on hardware functions. It is used to provide another chip version number that is fixed in hardware and can be read out by software. In this way different product packages consisting of GPON_MODEM and software can be defined for example */
|
|
+#define STATUS_CONFIG_SUBVERS_MASK 0x03C00000
|
|
+/** field offset */
|
|
+#define STATUS_CONFIG_SUBVERS_OFFSET 22
|
|
+/** PLL settings
|
|
+ PLL settings for infrastructure block */
|
|
+#define STATUS_CONFIG_PLLINFRA_MASK 0x003FF000
|
|
+/** field offset */
|
|
+#define STATUS_CONFIG_PLLINFRA_OFFSET 12
|
|
+/** GPE frequency selection
|
|
+ Scaling down the GPE frequency for debugging purpose */
|
|
+#define STATUS_CONFIG_GPEFREQ_MASK 0x00000C00
|
|
+/** field offset */
|
|
+#define STATUS_CONFIG_GPEFREQ_OFFSET 10
|
|
+/** RM enable
|
|
+ Activates the Read Margin Settings defined in the RM Field, for all VIRAGE Memories except GPE */
|
|
+#define STATUS_CONFIG_RME 0x00000200
|
|
+/* Not selected
|
|
+#define STATUS_CONFIG_RME_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define STATUS_CONFIG_RME_SEL 0x00000200
|
|
+/** RM settings
|
|
+ Read Marging Settings for all VIRAGE Memories except GPE */
|
|
+#define STATUS_CONFIG_RM_MASK 0x000001E0
|
|
+/** field offset */
|
|
+#define STATUS_CONFIG_RM_OFFSET 5
|
|
+/** RM enable for GPE Memories
|
|
+ Activates the Read Margin Settings defined in the RM Field */
|
|
+#define STATUS_CONFIG_RMEGPE 0x00000010
|
|
+/* Not selected
|
|
+#define STATUS_CONFIG_RMEGPE_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define STATUS_CONFIG_RMEGPE_SEL 0x00000010
|
|
+/** RM settings for GPE Memories
|
|
+ Read Marging Settings for VIRAGE Memories in GPE module */
|
|
+#define STATUS_CONFIG_RMGPE_MASK 0x0000000F
|
|
+/** field offset */
|
|
+#define STATUS_CONFIG_RMGPE_OFFSET 0
|
|
+
|
|
+/* Fields of "SPARE fuse register 1" */
|
|
+/** spare fuse1
|
|
+ eFuses not assigned to hw/sw, can be used for future applications */
|
|
+#define STATUS_FUSE1_F1_MASK 0xFFF00000
|
|
+/** field offset */
|
|
+#define STATUS_FUSE1_F1_OFFSET 20
|
|
+/** DCDC DDR OFFSET
|
|
+ offset error sense path */
|
|
+#define STATUS_FUSE1_OFFSETDDRDCDC_MASK 0x000F0000
|
|
+/** field offset */
|
|
+#define STATUS_FUSE1_OFFSETDDRDCDC_OFFSET 16
|
|
+/** DCDC DDR GAIN
|
|
+ gain error sense path */
|
|
+#define STATUS_FUSE1_GAINDDRDCDC_MASK 0x0000FC00
|
|
+/** field offset */
|
|
+#define STATUS_FUSE1_GAINDDRDCDC_OFFSET 10
|
|
+/** DCDC APD OFFSET
|
|
+ offset error sense path */
|
|
+#define STATUS_FUSE1_OFFSETAPDDCDC_MASK 0x000003C0
|
|
+/** field offset */
|
|
+#define STATUS_FUSE1_OFFSETAPDDCDC_OFFSET 6
|
|
+/** DCDC APD GAIN
|
|
+ gain error sense path */
|
|
+#define STATUS_FUSE1_GAINAPDDCDC_MASK 0x0000003F
|
|
+/** field offset */
|
|
+#define STATUS_FUSE1_GAINAPDDCDC_OFFSET 0
|
|
+
|
|
+/* Fields of "Configuration for sbs0 rambist" */
|
|
+/** Disable asc monitoring during boot-up
|
|
+ Bit is used to avoid asc output for reducing pattern count on testsystem */
|
|
+#define STATUS_MBCFG_ASC_DBGDIS 0x01000000
|
|
+/* Disable
|
|
+#define STATUS_MBCFG_ASC_DBGDIS_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define STATUS_MBCFG_ASC_DBGDIS_EN 0x01000000
|
|
+/** Descrambling Enable/Disable
|
|
+ Enables Address and Data Descrambling for internal Memory Test */
|
|
+#define STATUS_MBCFG_DSC 0x00800000
|
|
+/* Disable
|
|
+#define STATUS_MBCFG_DSC_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define STATUS_MBCFG_DSC_EN 0x00800000
|
|
+/** Enable repair mode
|
|
+ When bit is set redundancy repair mode is activated */
|
|
+#define STATUS_MBCFG_REPAIR 0x00400000
|
|
+/* Disable
|
|
+#define STATUS_MBCFG_REPAIR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define STATUS_MBCFG_REPAIR_EN 0x00400000
|
|
+/** DEBUG Mode */
|
|
+#define STATUS_MBCFG_DBG 0x00200000
|
|
+/* Disable
|
|
+#define STATUS_MBCFG_DBG_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define STATUS_MBCFG_DBG_EN 0x00200000
|
|
+/** Retention Time
|
|
+ Length oft the Retention Time */
|
|
+#define STATUS_MBCFG_RTIME_MASK 0x001C0000
|
|
+/** field offset */
|
|
+#define STATUS_MBCFG_RTIME_OFFSET 18
|
|
+/** retention mode is switched off */
|
|
+#define STATUS_MBCFG_RTIME_RET0 0x00000000
|
|
+/** Retention time 50 ms */
|
|
+#define STATUS_MBCFG_RTIME_RET50 0x00040000
|
|
+/** Retention time 60 ms */
|
|
+#define STATUS_MBCFG_RTIME_RET60 0x00080000
|
|
+/** Retention time 70 ms */
|
|
+#define STATUS_MBCFG_RTIME_RET70 0x000C0000
|
|
+/** Retention time 80 ms */
|
|
+#define STATUS_MBCFG_RTIME_RET80 0x00100000
|
|
+/** Retention time 90 ms */
|
|
+#define STATUS_MBCFG_RTIME_RET90 0x00140000
|
|
+/** Retention time 1000 ms */
|
|
+#define STATUS_MBCFG_RTIME_RET1000 0x00180000
|
|
+/** Test ID
|
|
+ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
|
|
+#define STATUS_MBCFG_TID_5_MASK 0x00038000
|
|
+/** field offset */
|
|
+#define STATUS_MBCFG_TID_5_OFFSET 15
|
|
+/** No test is performed */
|
|
+#define STATUS_MBCFG_TID_5_NONE 0x00000000
|
|
+/** March test */
|
|
+#define STATUS_MBCFG_TID_5_MARCH 0x00008000
|
|
+/** Checkerboard test */
|
|
+#define STATUS_MBCFG_TID_5_CHCK 0x00010000
|
|
+/** Hammer test */
|
|
+#define STATUS_MBCFG_TID_5_HAM 0x00018000
|
|
+/** Address decoder test */
|
|
+#define STATUS_MBCFG_TID_5_ADEC 0x00020000
|
|
+/** Write mask byte test */
|
|
+#define STATUS_MBCFG_TID_5_WMBYTE 0x00028000
|
|
+/** Reserved */
|
|
+#define STATUS_MBCFG_TID_5_RES 0x00030000
|
|
+/** Test ID
|
|
+ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
|
|
+#define STATUS_MBCFG_TID_4_MASK 0x00007000
|
|
+/** field offset */
|
|
+#define STATUS_MBCFG_TID_4_OFFSET 12
|
|
+/** No test is performed */
|
|
+#define STATUS_MBCFG_TID_4_NONE 0x00000000
|
|
+/** March test */
|
|
+#define STATUS_MBCFG_TID_4_MARCH 0x00001000
|
|
+/** Checkerboard test */
|
|
+#define STATUS_MBCFG_TID_4_CHCK 0x00002000
|
|
+/** Hammer test */
|
|
+#define STATUS_MBCFG_TID_4_HAM 0x00003000
|
|
+/** Address decoder test */
|
|
+#define STATUS_MBCFG_TID_4_ADEC 0x00004000
|
|
+/** Write mask byte test */
|
|
+#define STATUS_MBCFG_TID_4_WMBYTE 0x00005000
|
|
+/** Reserved */
|
|
+#define STATUS_MBCFG_TID_4_RES 0x00006000
|
|
+/** Test ID
|
|
+ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
|
|
+#define STATUS_MBCFG_TID_3_MASK 0x00000E00
|
|
+/** field offset */
|
|
+#define STATUS_MBCFG_TID_3_OFFSET 9
|
|
+/** No test is performed */
|
|
+#define STATUS_MBCFG_TID_3_NONE 0x00000000
|
|
+/** March test */
|
|
+#define STATUS_MBCFG_TID_3_MARCH 0x00000200
|
|
+/** Checkerboard test */
|
|
+#define STATUS_MBCFG_TID_3_CHCK 0x00000400
|
|
+/** Hammer test */
|
|
+#define STATUS_MBCFG_TID_3_HAM 0x00000600
|
|
+/** Address decoder test */
|
|
+#define STATUS_MBCFG_TID_3_ADEC 0x00000800
|
|
+/** Write mask byte test */
|
|
+#define STATUS_MBCFG_TID_3_WMBYTE 0x00000A00
|
|
+/** Reserved */
|
|
+#define STATUS_MBCFG_TID_3_RES 0x00000C00
|
|
+/** Test ID
|
|
+ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
|
|
+#define STATUS_MBCFG_TID_2_MASK 0x000001C0
|
|
+/** field offset */
|
|
+#define STATUS_MBCFG_TID_2_OFFSET 6
|
|
+/** No test is performed */
|
|
+#define STATUS_MBCFG_TID_2_NONE 0x00000000
|
|
+/** March test */
|
|
+#define STATUS_MBCFG_TID_2_MARCH 0x00000040
|
|
+/** Checkerboard test */
|
|
+#define STATUS_MBCFG_TID_2_CHCK 0x00000080
|
|
+/** Hammer test */
|
|
+#define STATUS_MBCFG_TID_2_HAM 0x000000C0
|
|
+/** Address decoder test */
|
|
+#define STATUS_MBCFG_TID_2_ADEC 0x00000100
|
|
+/** Write mask byte test */
|
|
+#define STATUS_MBCFG_TID_2_WMBYTE 0x00000140
|
|
+/** Reserved */
|
|
+#define STATUS_MBCFG_TID_2_RES 0x00000180
|
|
+/** Test ID
|
|
+ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
|
|
+#define STATUS_MBCFG_TID_1_MASK 0x00000038
|
|
+/** field offset */
|
|
+#define STATUS_MBCFG_TID_1_OFFSET 3
|
|
+/** No test is performed */
|
|
+#define STATUS_MBCFG_TID_1_NONE 0x00000000
|
|
+/** March test */
|
|
+#define STATUS_MBCFG_TID_1_MARCH 0x00000008
|
|
+/** Checkerboard test */
|
|
+#define STATUS_MBCFG_TID_1_CHCK 0x00000010
|
|
+/** Hammer test */
|
|
+#define STATUS_MBCFG_TID_1_HAM 0x00000018
|
|
+/** Address decoder test */
|
|
+#define STATUS_MBCFG_TID_1_ADEC 0x00000020
|
|
+/** Write mask byte test */
|
|
+#define STATUS_MBCFG_TID_1_WMBYTE 0x00000028
|
|
+/** Reserved */
|
|
+#define STATUS_MBCFG_TID_1_RES 0x00000030
|
|
+/** Test ID
|
|
+ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */
|
|
+#define STATUS_MBCFG_TID_0_MASK 0x00000007
|
|
+/** field offset */
|
|
+#define STATUS_MBCFG_TID_0_OFFSET 0
|
|
+/** No test is performed */
|
|
+#define STATUS_MBCFG_TID_0_NONE 0x00000000
|
|
+/** March test */
|
|
+#define STATUS_MBCFG_TID_0_MARCH 0x00000001
|
|
+/** Checkerboard test */
|
|
+#define STATUS_MBCFG_TID_0_CHCK 0x00000002
|
|
+/** Hammer test */
|
|
+#define STATUS_MBCFG_TID_0_HAM 0x00000003
|
|
+/** Address decoder test */
|
|
+#define STATUS_MBCFG_TID_0_ADEC 0x00000004
|
|
+/** Write mask byte test */
|
|
+#define STATUS_MBCFG_TID_0_WMBYTE 0x00000005
|
|
+/** Reserved */
|
|
+#define STATUS_MBCFG_TID_0_RES 0x00000006
|
|
+
|
|
+/* Fields of "sbs0 bist result and debug data" */
|
|
+/** BIST result and debug data
|
|
+ Stores additional debug information */
|
|
+#define STATUS_MBDATA_DATA_MASK 0xFFFFFFF8
|
|
+/** field offset */
|
|
+#define STATUS_MBDATA_DATA_OFFSET 3
|
|
+/** MBIST NOGO
|
|
+ The BIST failed and cannot be repaired due to many failure locations */
|
|
+#define STATUS_MBDATA_MBNOGO 0x00000004
|
|
+/** MBIST FAILED
|
|
+ The BIST failed but can be repaired */
|
|
+#define STATUS_MBDATA_MBFAIL 0x00000002
|
|
+/** MBIST PASSED
|
|
+ The BIST passed without any Failures */
|
|
+#define STATUS_MBDATA_MBPASS 0x00000001
|
|
+
|
|
+/*! @} */ /* STATUS_REGISTER */
|
|
+
|
|
+#endif /* _status_reg_h */
|
|
--- /dev/null
|
|
+++ b/arch/mips/include/asm/mach-lantiq/falcon/sys1_reg.h
|
|
@@ -0,0 +1,2008 @@
|
|
+/******************************************************************************
|
|
+
|
|
+ Copyright (c) 2010
|
|
+ Lantiq Deutschland GmbH
|
|
+
|
|
+ For licensing information, see the file 'LICENSE' in the root folder of
|
|
+ this software module.
|
|
+
|
|
+******************************************************************************/
|
|
+
|
|
+#ifndef _sys1_reg_h
|
|
+#define _sys1_reg_h
|
|
+
|
|
+/** \addtogroup SYS1_REGISTER
|
|
+ @{
|
|
+*/
|
|
+/* access macros */
|
|
+#define sys1_r32(reg) reg_r32(&sys1->reg)
|
|
+#define sys1_w32(val, reg) reg_w32(val, &sys1->reg)
|
|
+#define sys1_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys1->reg)
|
|
+#define sys1_r32_table(reg, idx) reg_r32_table(sys1->reg, idx)
|
|
+#define sys1_w32_table(val, reg, idx) reg_w32_table(val, sys1->reg, idx)
|
|
+#define sys1_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys1->reg, idx)
|
|
+#define sys1_adr_table(reg, idx) adr_table(sys1->reg, idx)
|
|
+
|
|
+
|
|
+/** SYS1 register structure */
|
|
+struct gpon_reg_sys1
|
|
+{
|
|
+ /** Clock Status Register */
|
|
+ unsigned int clks; /* 0x00000000 */
|
|
+ /** Clock Enable Register
|
|
+ Via this register the clocks for the domains can be enabled. */
|
|
+ unsigned int clken; /* 0x00000004 */
|
|
+ /** Clock Clear Register
|
|
+ Via this register the clocks for the domains can be disabled. */
|
|
+ unsigned int clkclr; /* 0x00000008 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_0[5]; /* 0x0000000C */
|
|
+ /** Activation Status Register */
|
|
+ unsigned int acts; /* 0x00000020 */
|
|
+ /** Activation Register
|
|
+ Via this register the domains can be activated. */
|
|
+ unsigned int act; /* 0x00000024 */
|
|
+ /** Deactivation Register
|
|
+ Via this register the domains can be deactivated. */
|
|
+ unsigned int deact; /* 0x00000028 */
|
|
+ /** Reboot Trigger Register
|
|
+ Via this register the domains can be rebooted (sent through reset). */
|
|
+ unsigned int rbt; /* 0x0000002C */
|
|
+ /** Reserved */
|
|
+ unsigned int res_1[4]; /* 0x00000030 */
|
|
+ /** CPU0 Clock Control Register
|
|
+ Clock control register for CPU0 */
|
|
+ unsigned int cpu0cc; /* 0x00000040 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_2[7]; /* 0x00000044 */
|
|
+ /** CPU0 Reset Source Register
|
|
+ Via this register the CPU can find the the root cause for the boot it currently goes through, and take the appropriate measures. */
|
|
+ unsigned int cpu0rs; /* 0x00000060 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_3[7]; /* 0x00000064 */
|
|
+ /** CPU0 Wakeup Configuration Register
|
|
+ Controls the wakeup condition for CPU0. Note: The upper 16 bit of this register have to be set to the same value as the mask bits within the yield-resume interface block. If the yield-resume interface is not used at all, set the upper 16 bit to 0. */
|
|
+ unsigned int cpu0wcfg; /* 0x00000080 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_4[7]; /* 0x00000084 */
|
|
+ /** Bootmode Control Register
|
|
+ Reflects the bootmode for the CPU and provides means to manipulate it. */
|
|
+ unsigned int bmc; /* 0x000000A0 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_5[3]; /* 0x000000A4 */
|
|
+ /** Sleep Configuration Register */
|
|
+ unsigned int scfg; /* 0x000000B0 */
|
|
+ /** Power Down Configuration Register
|
|
+ Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be switched off. */
|
|
+ unsigned int pdcfg; /* 0x000000B4 */
|
|
+ /** CLKO Pad Control Register
|
|
+ Controls the behaviour of the CLKO pad/ball. */
|
|
+ unsigned int clkoc; /* 0x000000B8 */
|
|
+ /** Infrastructure Control Register
|
|
+ Controls the behaviour of the components of the infrastructure block. */
|
|
+ unsigned int infrac; /* 0x000000BC */
|
|
+ /** HRST_OUT_N Control Register
|
|
+ Controls the behaviour of the HRST_OUT_N pin. */
|
|
+ unsigned int hrstoutc; /* 0x000000C0 */
|
|
+ /** EBU Clock Control Register
|
|
+ Clock control register for the EBU. */
|
|
+ unsigned int ebucc; /* 0x000000C4 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_6[2]; /* 0x000000C8 */
|
|
+ /** NMI Status Register
|
|
+ The Test NMI source is the GPTC counter 1A overflow bit. */
|
|
+ unsigned int nmis; /* 0x000000D0 */
|
|
+ /** NMI Set Register */
|
|
+ unsigned int nmiset; /* 0x000000D4 */
|
|
+ /** NMI Clear Register */
|
|
+ unsigned int nmiclr; /* 0x000000D8 */
|
|
+ /** NMI Test Configuration Register */
|
|
+ unsigned int nmitcfg; /* 0x000000DC */
|
|
+ /** NMI VPE1 Control Register */
|
|
+ unsigned int nmivpe1c; /* 0x000000E0 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_7[3]; /* 0x000000E4 */
|
|
+ /** IRN Capture Register
|
|
+ This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNEN register. The interrupts can be acknowledged by a write operation. */
|
|
+ unsigned int irncr; /* 0x000000F0 */
|
|
+ /** IRN Interrupt Control Register
|
|
+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
|
|
+ unsigned int irnicr; /* 0x000000F4 */
|
|
+ /** IRN Interrupt Enable Register
|
|
+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCR register and are not signalled via the interrupt line towards the controller. */
|
|
+ unsigned int irnen; /* 0x000000F8 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_8; /* 0x000000FC */
|
|
+};
|
|
+
|
|
+
|
|
+/* Fields of "Clock Status Register" */
|
|
+/** STATUS Clock Enable
|
|
+ Shows the clock enable bit for the STATUS domain. This domain contains the STATUS block. */
|
|
+#define CLKS_STATUS 0x80000000
|
|
+/* Disable
|
|
+#define CLKS_STATUS_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_STATUS_EN 0x80000000
|
|
+/** SHA1 Clock Enable
|
|
+ Shows the clock enable bit for the SHA1 domain. This domain contains the SHA1 block. */
|
|
+#define CLKS_SHA1 0x40000000
|
|
+/* Disable
|
|
+#define CLKS_SHA1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_SHA1_EN 0x40000000
|
|
+/** AES Clock Enable
|
|
+ Shows the clock enable bit for the AES domain. This domain contains the AES block. */
|
|
+#define CLKS_AES 0x20000000
|
|
+/* Disable
|
|
+#define CLKS_AES_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_AES_EN 0x20000000
|
|
+/** PCM Clock Enable
|
|
+ Shows the clock enable bit for the PCM domain. This domain contains the PCM interface block. */
|
|
+#define CLKS_PCM 0x10000000
|
|
+/* Disable
|
|
+#define CLKS_PCM_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_PCM_EN 0x10000000
|
|
+/** FSCT Clock Enable
|
|
+ Shows the clock enable bit for the FSCT domain. This domain contains the FSCT block. */
|
|
+#define CLKS_FSCT 0x08000000
|
|
+/* Disable
|
|
+#define CLKS_FSCT_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_FSCT_EN 0x08000000
|
|
+/** GPTC Clock Enable
|
|
+ Shows the clock enable bit for the GPTC domain. This domain contains the GPTC block. */
|
|
+#define CLKS_GPTC 0x04000000
|
|
+/* Disable
|
|
+#define CLKS_GPTC_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_GPTC_EN 0x04000000
|
|
+/** MPS Clock Enable
|
|
+ Shows the clock enable bit for the MPS domain. This domain contains the MPS block. */
|
|
+#define CLKS_MPS 0x02000000
|
|
+/* Disable
|
|
+#define CLKS_MPS_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_MPS_EN 0x02000000
|
|
+/** DFEV0 Clock Enable
|
|
+ Shows the clock enable bit for the DFEV0 domain. This domain contains the DFEV0 block. */
|
|
+#define CLKS_DFEV0 0x01000000
|
|
+/* Disable
|
|
+#define CLKS_DFEV0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_DFEV0_EN 0x01000000
|
|
+/** PADCTRL4 Clock Enable
|
|
+ Shows the clock enable bit for the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
|
|
+#define CLKS_PADCTRL4 0x00400000
|
|
+/* Disable
|
|
+#define CLKS_PADCTRL4_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_PADCTRL4_EN 0x00400000
|
|
+/** PADCTRL3 Clock Enable
|
|
+ Shows the clock enable bit for the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
|
|
+#define CLKS_PADCTRL3 0x00200000
|
|
+/* Disable
|
|
+#define CLKS_PADCTRL3_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_PADCTRL3_EN 0x00200000
|
|
+/** PADCTRL1 Clock Enable
|
|
+ Shows the clock enable bit for the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
|
|
+#define CLKS_PADCTRL1 0x00100000
|
|
+/* Disable
|
|
+#define CLKS_PADCTRL1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_PADCTRL1_EN 0x00100000
|
|
+/** P4 Clock Enable
|
|
+ Shows the clock enable bit for the P4 domain. This domain contains the P4 instance of the GPIO block. */
|
|
+#define CLKS_P4 0x00040000
|
|
+/* Disable
|
|
+#define CLKS_P4_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_P4_EN 0x00040000
|
|
+/** P3 Clock Enable
|
|
+ Shows the clock enable bit for the P3 domain. This domain contains the P3 instance of the GPIO block. */
|
|
+#define CLKS_P3 0x00020000
|
|
+/* Disable
|
|
+#define CLKS_P3_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_P3_EN 0x00020000
|
|
+/** P1 Clock Enable
|
|
+ Shows the clock enable bit for the P1 domain. This domain contains the P1 instance of the GPIO block. */
|
|
+#define CLKS_P1 0x00010000
|
|
+/* Disable
|
|
+#define CLKS_P1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_P1_EN 0x00010000
|
|
+/** HOST Clock Enable
|
|
+ Shows the clock enable bit for the HOST domain. This domain contains the HOST interface block. */
|
|
+#define CLKS_HOST 0x00008000
|
|
+/* Disable
|
|
+#define CLKS_HOST_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_HOST_EN 0x00008000
|
|
+/** I2C Clock Enable
|
|
+ Shows the clock enable bit for the I2C domain. This domain contains the I2C interface block. */
|
|
+#define CLKS_I2C 0x00004000
|
|
+/* Disable
|
|
+#define CLKS_I2C_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_I2C_EN 0x00004000
|
|
+/** SSC0 Clock Enable
|
|
+ Shows the clock enable bit for the SSC0 domain. This domain contains the SSC0 interface block. */
|
|
+#define CLKS_SSC0 0x00002000
|
|
+/* Disable
|
|
+#define CLKS_SSC0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_SSC0_EN 0x00002000
|
|
+/** ASC0 Clock Enable
|
|
+ Shows the clock enable bit for the ASC0 domain. This domain contains the ASC0 interface block. */
|
|
+#define CLKS_ASC0 0x00001000
|
|
+/* Disable
|
|
+#define CLKS_ASC0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_ASC0_EN 0x00001000
|
|
+/** ASC1 Clock Enable
|
|
+ Shows the clock enable bit for the ASC1 domain. This domain contains the ASC1 block. */
|
|
+#define CLKS_ASC1 0x00000800
|
|
+/* Disable
|
|
+#define CLKS_ASC1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_ASC1_EN 0x00000800
|
|
+/** DCDCAPD Clock Enable
|
|
+ Shows the clock enable bit for the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
|
|
+#define CLKS_DCDCAPD 0x00000400
|
|
+/* Disable
|
|
+#define CLKS_DCDCAPD_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_DCDCAPD_EN 0x00000400
|
|
+/** DCDCDDR Clock Enable
|
|
+ Shows the clock enable bit for the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
|
|
+#define CLKS_DCDCDDR 0x00000200
|
|
+/* Disable
|
|
+#define CLKS_DCDCDDR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_DCDCDDR_EN 0x00000200
|
|
+/** DCDC1V0 Clock Enable
|
|
+ Shows the clock enable bit for the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
|
|
+#define CLKS_DCDC1V0 0x00000100
|
|
+/* Disable
|
|
+#define CLKS_DCDC1V0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_DCDC1V0_EN 0x00000100
|
|
+/** TRC2MEM Clock Enable
|
|
+ Shows the clock enable bit for the TRC2MEM domain. This domain contains the TRC2MEM block. */
|
|
+#define CLKS_TRC2MEM 0x00000040
|
|
+/* Disable
|
|
+#define CLKS_TRC2MEM_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_TRC2MEM_EN 0x00000040
|
|
+/** DDR Clock Enable
|
|
+ Shows the clock enable bit for the DDR domain. This domain contains the DDR interface block. */
|
|
+#define CLKS_DDR 0x00000020
|
|
+/* Disable
|
|
+#define CLKS_DDR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_DDR_EN 0x00000020
|
|
+/** EBU Clock Enable
|
|
+ Shows the clock enable bit for the EBU domain. This domain contains the EBU interface block. */
|
|
+#define CLKS_EBU 0x00000010
|
|
+/* Disable
|
|
+#define CLKS_EBU_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKS_EBU_EN 0x00000010
|
|
+
|
|
+/* Fields of "Clock Enable Register" */
|
|
+/** Set Clock Enable STATUS
|
|
+ Sets the clock enable bit of the STATUS domain. This domain contains the STATUS block. */
|
|
+#define CLKEN_STATUS 0x80000000
|
|
+/* No-Operation
|
|
+#define CLKEN_STATUS_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_STATUS_SET 0x80000000
|
|
+/** Set Clock Enable SHA1
|
|
+ Sets the clock enable bit of the SHA1 domain. This domain contains the SHA1 block. */
|
|
+#define CLKEN_SHA1 0x40000000
|
|
+/* No-Operation
|
|
+#define CLKEN_SHA1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_SHA1_SET 0x40000000
|
|
+/** Set Clock Enable AES
|
|
+ Sets the clock enable bit of the AES domain. This domain contains the AES block. */
|
|
+#define CLKEN_AES 0x20000000
|
|
+/* No-Operation
|
|
+#define CLKEN_AES_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_AES_SET 0x20000000
|
|
+/** Set Clock Enable PCM
|
|
+ Sets the clock enable bit of the PCM domain. This domain contains the PCM interface block. */
|
|
+#define CLKEN_PCM 0x10000000
|
|
+/* No-Operation
|
|
+#define CLKEN_PCM_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_PCM_SET 0x10000000
|
|
+/** Set Clock Enable FSCT
|
|
+ Sets the clock enable bit of the FSCT domain. This domain contains the FSCT block. */
|
|
+#define CLKEN_FSCT 0x08000000
|
|
+/* No-Operation
|
|
+#define CLKEN_FSCT_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_FSCT_SET 0x08000000
|
|
+/** Set Clock Enable GPTC
|
|
+ Sets the clock enable bit of the GPTC domain. This domain contains the GPTC block. */
|
|
+#define CLKEN_GPTC 0x04000000
|
|
+/* No-Operation
|
|
+#define CLKEN_GPTC_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_GPTC_SET 0x04000000
|
|
+/** Set Clock Enable MPS
|
|
+ Sets the clock enable bit of the MPS domain. This domain contains the MPS block. */
|
|
+#define CLKEN_MPS 0x02000000
|
|
+/* No-Operation
|
|
+#define CLKEN_MPS_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_MPS_SET 0x02000000
|
|
+/** Set Clock Enable DFEV0
|
|
+ Sets the clock enable bit of the DFEV0 domain. This domain contains the DFEV0 block. */
|
|
+#define CLKEN_DFEV0 0x01000000
|
|
+/* No-Operation
|
|
+#define CLKEN_DFEV0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_DFEV0_SET 0x01000000
|
|
+/** Set Clock Enable PADCTRL4
|
|
+ Sets the clock enable bit of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
|
|
+#define CLKEN_PADCTRL4 0x00400000
|
|
+/* No-Operation
|
|
+#define CLKEN_PADCTRL4_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_PADCTRL4_SET 0x00400000
|
|
+/** Set Clock Enable PADCTRL3
|
|
+ Sets the clock enable bit of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
|
|
+#define CLKEN_PADCTRL3 0x00200000
|
|
+/* No-Operation
|
|
+#define CLKEN_PADCTRL3_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_PADCTRL3_SET 0x00200000
|
|
+/** Set Clock Enable PADCTRL1
|
|
+ Sets the clock enable bit of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
|
|
+#define CLKEN_PADCTRL1 0x00100000
|
|
+/* No-Operation
|
|
+#define CLKEN_PADCTRL1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_PADCTRL1_SET 0x00100000
|
|
+/** Set Clock Enable P4
|
|
+ Sets the clock enable bit of the P4 domain. This domain contains the P4 instance of the GPIO block. */
|
|
+#define CLKEN_P4 0x00040000
|
|
+/* No-Operation
|
|
+#define CLKEN_P4_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_P4_SET 0x00040000
|
|
+/** Set Clock Enable P3
|
|
+ Sets the clock enable bit of the P3 domain. This domain contains the P3 instance of the GPIO block. */
|
|
+#define CLKEN_P3 0x00020000
|
|
+/* No-Operation
|
|
+#define CLKEN_P3_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_P3_SET 0x00020000
|
|
+/** Set Clock Enable P1
|
|
+ Sets the clock enable bit of the P1 domain. This domain contains the P1 instance of the GPIO block. */
|
|
+#define CLKEN_P1 0x00010000
|
|
+/* No-Operation
|
|
+#define CLKEN_P1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_P1_SET 0x00010000
|
|
+/** Set Clock Enable HOST
|
|
+ Sets the clock enable bit of the HOST domain. This domain contains the HOST interface block. */
|
|
+#define CLKEN_HOST 0x00008000
|
|
+/* No-Operation
|
|
+#define CLKEN_HOST_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_HOST_SET 0x00008000
|
|
+/** Set Clock Enable I2C
|
|
+ Sets the clock enable bit of the I2C domain. This domain contains the I2C interface block. */
|
|
+#define CLKEN_I2C 0x00004000
|
|
+/* No-Operation
|
|
+#define CLKEN_I2C_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_I2C_SET 0x00004000
|
|
+/** Set Clock Enable SSC0
|
|
+ Sets the clock enable bit of the SSC0 domain. This domain contains the SSC0 interface block. */
|
|
+#define CLKEN_SSC0 0x00002000
|
|
+/* No-Operation
|
|
+#define CLKEN_SSC0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_SSC0_SET 0x00002000
|
|
+/** Set Clock Enable ASC0
|
|
+ Sets the clock enable bit of the ASC0 domain. This domain contains the ASC0 interface block. */
|
|
+#define CLKEN_ASC0 0x00001000
|
|
+/* No-Operation
|
|
+#define CLKEN_ASC0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_ASC0_SET 0x00001000
|
|
+/** Set Clock Enable ASC1
|
|
+ Sets the clock enable bit of the ASC1 domain. This domain contains the ASC1 block. */
|
|
+#define CLKEN_ASC1 0x00000800
|
|
+/* No-Operation
|
|
+#define CLKEN_ASC1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_ASC1_SET 0x00000800
|
|
+/** Set Clock Enable DCDCAPD
|
|
+ Sets the clock enable bit of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
|
|
+#define CLKEN_DCDCAPD 0x00000400
|
|
+/* No-Operation
|
|
+#define CLKEN_DCDCAPD_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_DCDCAPD_SET 0x00000400
|
|
+/** Set Clock Enable DCDCDDR
|
|
+ Sets the clock enable bit of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
|
|
+#define CLKEN_DCDCDDR 0x00000200
|
|
+/* No-Operation
|
|
+#define CLKEN_DCDCDDR_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_DCDCDDR_SET 0x00000200
|
|
+/** Set Clock Enable DCDC1V0
|
|
+ Sets the clock enable bit of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
|
|
+#define CLKEN_DCDC1V0 0x00000100
|
|
+/* No-Operation
|
|
+#define CLKEN_DCDC1V0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_DCDC1V0_SET 0x00000100
|
|
+/** Set Clock Enable TRC2MEM
|
|
+ Sets the clock enable bit of the TRC2MEM domain. This domain contains the TRC2MEM block. */
|
|
+#define CLKEN_TRC2MEM 0x00000040
|
|
+/* No-Operation
|
|
+#define CLKEN_TRC2MEM_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_TRC2MEM_SET 0x00000040
|
|
+/** Set Clock Enable DDR
|
|
+ Sets the clock enable bit of the DDR domain. This domain contains the DDR interface block. */
|
|
+#define CLKEN_DDR 0x00000020
|
|
+/* No-Operation
|
|
+#define CLKEN_DDR_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_DDR_SET 0x00000020
|
|
+/** Set Clock Enable EBU
|
|
+ Sets the clock enable bit of the EBU domain. This domain contains the EBU interface block. */
|
|
+#define CLKEN_EBU 0x00000010
|
|
+/* No-Operation
|
|
+#define CLKEN_EBU_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define CLKEN_EBU_SET 0x00000010
|
|
+
|
|
+/* Fields of "Clock Clear Register" */
|
|
+/** Clear Clock Enable STATUS
|
|
+ Clears the clock enable bit of the STATUS domain. This domain contains the STATUS block. */
|
|
+#define CLKCLR_STATUS 0x80000000
|
|
+/* No-Operation
|
|
+#define CLKCLR_STATUS_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_STATUS_CLR 0x80000000
|
|
+/** Clear Clock Enable SHA1
|
|
+ Clears the clock enable bit of the SHA1 domain. This domain contains the SHA1 block. */
|
|
+#define CLKCLR_SHA1 0x40000000
|
|
+/* No-Operation
|
|
+#define CLKCLR_SHA1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_SHA1_CLR 0x40000000
|
|
+/** Clear Clock Enable AES
|
|
+ Clears the clock enable bit of the AES domain. This domain contains the AES block. */
|
|
+#define CLKCLR_AES 0x20000000
|
|
+/* No-Operation
|
|
+#define CLKCLR_AES_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_AES_CLR 0x20000000
|
|
+/** Clear Clock Enable PCM
|
|
+ Clears the clock enable bit of the PCM domain. This domain contains the PCM interface block. */
|
|
+#define CLKCLR_PCM 0x10000000
|
|
+/* No-Operation
|
|
+#define CLKCLR_PCM_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_PCM_CLR 0x10000000
|
|
+/** Clear Clock Enable FSCT
|
|
+ Clears the clock enable bit of the FSCT domain. This domain contains the FSCT block. */
|
|
+#define CLKCLR_FSCT 0x08000000
|
|
+/* No-Operation
|
|
+#define CLKCLR_FSCT_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_FSCT_CLR 0x08000000
|
|
+/** Clear Clock Enable GPTC
|
|
+ Clears the clock enable bit of the GPTC domain. This domain contains the GPTC block. */
|
|
+#define CLKCLR_GPTC 0x04000000
|
|
+/* No-Operation
|
|
+#define CLKCLR_GPTC_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_GPTC_CLR 0x04000000
|
|
+/** Clear Clock Enable MPS
|
|
+ Clears the clock enable bit of the MPS domain. This domain contains the MPS block. */
|
|
+#define CLKCLR_MPS 0x02000000
|
|
+/* No-Operation
|
|
+#define CLKCLR_MPS_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_MPS_CLR 0x02000000
|
|
+/** Clear Clock Enable DFEV0
|
|
+ Clears the clock enable bit of the DFEV0 domain. This domain contains the DFEV0 block. */
|
|
+#define CLKCLR_DFEV0 0x01000000
|
|
+/* No-Operation
|
|
+#define CLKCLR_DFEV0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_DFEV0_CLR 0x01000000
|
|
+/** Clear Clock Enable PADCTRL4
|
|
+ Clears the clock enable bit of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
|
|
+#define CLKCLR_PADCTRL4 0x00400000
|
|
+/* No-Operation
|
|
+#define CLKCLR_PADCTRL4_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_PADCTRL4_CLR 0x00400000
|
|
+/** Clear Clock Enable PADCTRL3
|
|
+ Clears the clock enable bit of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
|
|
+#define CLKCLR_PADCTRL3 0x00200000
|
|
+/* No-Operation
|
|
+#define CLKCLR_PADCTRL3_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_PADCTRL3_CLR 0x00200000
|
|
+/** Clear Clock Enable PADCTRL1
|
|
+ Clears the clock enable bit of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
|
|
+#define CLKCLR_PADCTRL1 0x00100000
|
|
+/* No-Operation
|
|
+#define CLKCLR_PADCTRL1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_PADCTRL1_CLR 0x00100000
|
|
+/** Clear Clock Enable P4
|
|
+ Clears the clock enable bit of the P4 domain. This domain contains the P4 instance of the GPIO block. */
|
|
+#define CLKCLR_P4 0x00040000
|
|
+/* No-Operation
|
|
+#define CLKCLR_P4_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_P4_CLR 0x00040000
|
|
+/** Clear Clock Enable P3
|
|
+ Clears the clock enable bit of the P3 domain. This domain contains the P3 instance of the GPIO block. */
|
|
+#define CLKCLR_P3 0x00020000
|
|
+/* No-Operation
|
|
+#define CLKCLR_P3_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_P3_CLR 0x00020000
|
|
+/** Clear Clock Enable P1
|
|
+ Clears the clock enable bit of the P1 domain. This domain contains the P1 instance of the GPIO block. */
|
|
+#define CLKCLR_P1 0x00010000
|
|
+/* No-Operation
|
|
+#define CLKCLR_P1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_P1_CLR 0x00010000
|
|
+/** Clear Clock Enable HOST
|
|
+ Clears the clock enable bit of the HOST domain. This domain contains the HOST interface block. */
|
|
+#define CLKCLR_HOST 0x00008000
|
|
+/* No-Operation
|
|
+#define CLKCLR_HOST_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_HOST_CLR 0x00008000
|
|
+/** Clear Clock Enable I2C
|
|
+ Clears the clock enable bit of the I2C domain. This domain contains the I2C interface block. */
|
|
+#define CLKCLR_I2C 0x00004000
|
|
+/* No-Operation
|
|
+#define CLKCLR_I2C_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_I2C_CLR 0x00004000
|
|
+/** Clear Clock Enable SSC0
|
|
+ Clears the clock enable bit of the SSC0 domain. This domain contains the SSC0 interface block. */
|
|
+#define CLKCLR_SSC0 0x00002000
|
|
+/* No-Operation
|
|
+#define CLKCLR_SSC0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_SSC0_CLR 0x00002000
|
|
+/** Clear Clock Enable ASC0
|
|
+ Clears the clock enable bit of the ASC0 domain. This domain contains the ASC0 interface block. */
|
|
+#define CLKCLR_ASC0 0x00001000
|
|
+/* No-Operation
|
|
+#define CLKCLR_ASC0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_ASC0_CLR 0x00001000
|
|
+/** Clear Clock Enable ASC1
|
|
+ Clears the clock enable bit of the ASC1 domain. This domain contains the ASC1 block. */
|
|
+#define CLKCLR_ASC1 0x00000800
|
|
+/* No-Operation
|
|
+#define CLKCLR_ASC1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_ASC1_CLR 0x00000800
|
|
+/** Clear Clock Enable DCDCAPD
|
|
+ Clears the clock enable bit of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
|
|
+#define CLKCLR_DCDCAPD 0x00000400
|
|
+/* No-Operation
|
|
+#define CLKCLR_DCDCAPD_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_DCDCAPD_CLR 0x00000400
|
|
+/** Clear Clock Enable DCDCDDR
|
|
+ Clears the clock enable bit of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
|
|
+#define CLKCLR_DCDCDDR 0x00000200
|
|
+/* No-Operation
|
|
+#define CLKCLR_DCDCDDR_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_DCDCDDR_CLR 0x00000200
|
|
+/** Clear Clock Enable DCDC1V0
|
|
+ Clears the clock enable bit of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
|
|
+#define CLKCLR_DCDC1V0 0x00000100
|
|
+/* No-Operation
|
|
+#define CLKCLR_DCDC1V0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_DCDC1V0_CLR 0x00000100
|
|
+/** Clear Clock Enable TRC2MEM
|
|
+ Clears the clock enable bit of the TRC2MEM domain. This domain contains the TRC2MEM block. */
|
|
+#define CLKCLR_TRC2MEM 0x00000040
|
|
+/* No-Operation
|
|
+#define CLKCLR_TRC2MEM_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_TRC2MEM_CLR 0x00000040
|
|
+/** Clear Clock Enable DDR
|
|
+ Clears the clock enable bit of the DDR domain. This domain contains the DDR interface block. */
|
|
+#define CLKCLR_DDR 0x00000020
|
|
+/* No-Operation
|
|
+#define CLKCLR_DDR_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_DDR_CLR 0x00000020
|
|
+/** Clear Clock Enable EBU
|
|
+ Clears the clock enable bit of the EBU domain. This domain contains the EBU interface block. */
|
|
+#define CLKCLR_EBU 0x00000010
|
|
+/* No-Operation
|
|
+#define CLKCLR_EBU_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define CLKCLR_EBU_CLR 0x00000010
|
|
+
|
|
+/* Fields of "Activation Status Register" */
|
|
+/** STATUS Status
|
|
+ Shows the activation status of the STATUS domain. This domain contains the STATUS block. */
|
|
+#define ACTS_STATUS 0x80000000
|
|
+/* The block is inactive.
|
|
+#define ACTS_STATUS_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_STATUS_ACT 0x80000000
|
|
+/** SHA1 Status
|
|
+ Shows the activation status of the SHA1 domain. This domain contains the SHA1 block. */
|
|
+#define ACTS_SHA1 0x40000000
|
|
+/* The block is inactive.
|
|
+#define ACTS_SHA1_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_SHA1_ACT 0x40000000
|
|
+/** AES Status
|
|
+ Shows the activation status of the AES domain. This domain contains the AES block. */
|
|
+#define ACTS_AES 0x20000000
|
|
+/* The block is inactive.
|
|
+#define ACTS_AES_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_AES_ACT 0x20000000
|
|
+/** PCM Status
|
|
+ Shows the activation status of the PCM domain. This domain contains the PCM interface block. */
|
|
+#define ACTS_PCM 0x10000000
|
|
+/* The block is inactive.
|
|
+#define ACTS_PCM_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_PCM_ACT 0x10000000
|
|
+/** FSCT Status
|
|
+ Shows the activation status of the FSCT domain. This domain contains the FSCT block. */
|
|
+#define ACTS_FSCT 0x08000000
|
|
+/* The block is inactive.
|
|
+#define ACTS_FSCT_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_FSCT_ACT 0x08000000
|
|
+/** GPTC Status
|
|
+ Shows the activation status of the GPTC domain. This domain contains the GPTC block. */
|
|
+#define ACTS_GPTC 0x04000000
|
|
+/* The block is inactive.
|
|
+#define ACTS_GPTC_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_GPTC_ACT 0x04000000
|
|
+/** MPS Status
|
|
+ Shows the activation status of the MPS domain. This domain contains the MPS block. */
|
|
+#define ACTS_MPS 0x02000000
|
|
+/* The block is inactive.
|
|
+#define ACTS_MPS_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_MPS_ACT 0x02000000
|
|
+/** DFEV0 Status
|
|
+ Shows the activation status of the DFEV0 domain. This domain contains the DFEV0 block. */
|
|
+#define ACTS_DFEV0 0x01000000
|
|
+/* The block is inactive.
|
|
+#define ACTS_DFEV0_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_DFEV0_ACT 0x01000000
|
|
+/** PADCTRL4 Status
|
|
+ Shows the activation status of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
|
|
+#define ACTS_PADCTRL4 0x00400000
|
|
+/* The block is inactive.
|
|
+#define ACTS_PADCTRL4_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_PADCTRL4_ACT 0x00400000
|
|
+/** PADCTRL3 Status
|
|
+ Shows the activation status of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
|
|
+#define ACTS_PADCTRL3 0x00200000
|
|
+/* The block is inactive.
|
|
+#define ACTS_PADCTRL3_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_PADCTRL3_ACT 0x00200000
|
|
+/** PADCTRL1 Status
|
|
+ Shows the activation status of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
|
|
+#define ACTS_PADCTRL1 0x00100000
|
|
+/* The block is inactive.
|
|
+#define ACTS_PADCTRL1_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_PADCTRL1_ACT 0x00100000
|
|
+/** P4 Status
|
|
+ Shows the activation status of the P4 domain. This domain contains the P4 instance of the GPIO block. */
|
|
+#define ACTS_P4 0x00040000
|
|
+/* The block is inactive.
|
|
+#define ACTS_P4_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_P4_ACT 0x00040000
|
|
+/** P3 Status
|
|
+ Shows the activation status of the P3 domain. This domain contains the P3 instance of the GPIO block. */
|
|
+#define ACTS_P3 0x00020000
|
|
+/* The block is inactive.
|
|
+#define ACTS_P3_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_P3_ACT 0x00020000
|
|
+/** P1 Status
|
|
+ Shows the activation status of the P1 domain. This domain contains the P1 instance of the GPIO block. */
|
|
+#define ACTS_P1 0x00010000
|
|
+/* The block is inactive.
|
|
+#define ACTS_P1_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_P1_ACT 0x00010000
|
|
+/** HOST Status
|
|
+ Shows the activation status of the HOST domain. This domain contains the HOST interface block. */
|
|
+#define ACTS_HOST 0x00008000
|
|
+/* The block is inactive.
|
|
+#define ACTS_HOST_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_HOST_ACT 0x00008000
|
|
+/** I2C Status
|
|
+ Shows the activation status of the I2C domain. This domain contains the I2C interface block. */
|
|
+#define ACTS_I2C 0x00004000
|
|
+/* The block is inactive.
|
|
+#define ACTS_I2C_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_I2C_ACT 0x00004000
|
|
+/** SSC0 Status
|
|
+ Shows the activation status of the SSC0 domain. This domain contains the SSC0 interface block. */
|
|
+#define ACTS_SSC0 0x00002000
|
|
+/* The block is inactive.
|
|
+#define ACTS_SSC0_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_SSC0_ACT 0x00002000
|
|
+/** ASC0 Status
|
|
+ Shows the activation status of the ASC0 domain. This domain contains the ASC0 interface block. */
|
|
+#define ACTS_ASC0 0x00001000
|
|
+/* The block is inactive.
|
|
+#define ACTS_ASC0_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_ASC0_ACT 0x00001000
|
|
+/** ASC1 Status
|
|
+ Shows the activation status of the ASC1 domain. This domain contains the ASC1 block. */
|
|
+#define ACTS_ASC1 0x00000800
|
|
+/* The block is inactive.
|
|
+#define ACTS_ASC1_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_ASC1_ACT 0x00000800
|
|
+/** DCDCAPD Status
|
|
+ Shows the activation status of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
|
|
+#define ACTS_DCDCAPD 0x00000400
|
|
+/* The block is inactive.
|
|
+#define ACTS_DCDCAPD_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_DCDCAPD_ACT 0x00000400
|
|
+/** DCDCDDR Status
|
|
+ Shows the activation status of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
|
|
+#define ACTS_DCDCDDR 0x00000200
|
|
+/* The block is inactive.
|
|
+#define ACTS_DCDCDDR_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_DCDCDDR_ACT 0x00000200
|
|
+/** DCDC1V0 Status
|
|
+ Shows the activation status of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
|
|
+#define ACTS_DCDC1V0 0x00000100
|
|
+/* The block is inactive.
|
|
+#define ACTS_DCDC1V0_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_DCDC1V0_ACT 0x00000100
|
|
+/** TRC2MEM Status
|
|
+ Shows the activation status of the TRC2MEM domain. This domain contains the TRC2MEM block. */
|
|
+#define ACTS_TRC2MEM 0x00000040
|
|
+/* The block is inactive.
|
|
+#define ACTS_TRC2MEM_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_TRC2MEM_ACT 0x00000040
|
|
+/** DDR Status
|
|
+ Shows the activation status of the DDR domain. This domain contains the DDR interface block. */
|
|
+#define ACTS_DDR 0x00000020
|
|
+/* The block is inactive.
|
|
+#define ACTS_DDR_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_DDR_ACT 0x00000020
|
|
+/** EBU Status
|
|
+ Shows the activation status of the EBU domain. This domain contains the EBU interface block. */
|
|
+#define ACTS_EBU 0x00000010
|
|
+/* The block is inactive.
|
|
+#define ACTS_EBU_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define ACTS_EBU_ACT 0x00000010
|
|
+
|
|
+/* Fields of "Activation Register" */
|
|
+/** Activate STATUS
|
|
+ Sets the activation flag of the STATUS domain. This domain contains the STATUS block. */
|
|
+#define ACT_STATUS 0x80000000
|
|
+/* No-Operation
|
|
+#define ACT_STATUS_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_STATUS_SET 0x80000000
|
|
+/** Activate SHA1
|
|
+ Sets the activation flag of the SHA1 domain. This domain contains the SHA1 block. */
|
|
+#define ACT_SHA1 0x40000000
|
|
+/* No-Operation
|
|
+#define ACT_SHA1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_SHA1_SET 0x40000000
|
|
+/** Activate AES
|
|
+ Sets the activation flag of the AES domain. This domain contains the AES block. */
|
|
+#define ACT_AES 0x20000000
|
|
+/* No-Operation
|
|
+#define ACT_AES_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_AES_SET 0x20000000
|
|
+/** Activate PCM
|
|
+ Sets the activation flag of the PCM domain. This domain contains the PCM interface block. */
|
|
+#define ACT_PCM 0x10000000
|
|
+/* No-Operation
|
|
+#define ACT_PCM_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_PCM_SET 0x10000000
|
|
+/** Activate FSCT
|
|
+ Sets the activation flag of the FSCT domain. This domain contains the FSCT block. */
|
|
+#define ACT_FSCT 0x08000000
|
|
+/* No-Operation
|
|
+#define ACT_FSCT_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_FSCT_SET 0x08000000
|
|
+/** Activate GPTC
|
|
+ Sets the activation flag of the GPTC domain. This domain contains the GPTC block. */
|
|
+#define ACT_GPTC 0x04000000
|
|
+/* No-Operation
|
|
+#define ACT_GPTC_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_GPTC_SET 0x04000000
|
|
+/** Activate MPS
|
|
+ Sets the activation flag of the MPS domain. This domain contains the MPS block. */
|
|
+#define ACT_MPS 0x02000000
|
|
+/* No-Operation
|
|
+#define ACT_MPS_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_MPS_SET 0x02000000
|
|
+/** Activate DFEV0
|
|
+ Sets the activation flag of the DFEV0 domain. This domain contains the DFEV0 block. */
|
|
+#define ACT_DFEV0 0x01000000
|
|
+/* No-Operation
|
|
+#define ACT_DFEV0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_DFEV0_SET 0x01000000
|
|
+/** Activate PADCTRL4
|
|
+ Sets the activation flag of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
|
|
+#define ACT_PADCTRL4 0x00400000
|
|
+/* No-Operation
|
|
+#define ACT_PADCTRL4_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_PADCTRL4_SET 0x00400000
|
|
+/** Activate PADCTRL3
|
|
+ Sets the activation flag of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
|
|
+#define ACT_PADCTRL3 0x00200000
|
|
+/* No-Operation
|
|
+#define ACT_PADCTRL3_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_PADCTRL3_SET 0x00200000
|
|
+/** Activate PADCTRL1
|
|
+ Sets the activation flag of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
|
|
+#define ACT_PADCTRL1 0x00100000
|
|
+/* No-Operation
|
|
+#define ACT_PADCTRL1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_PADCTRL1_SET 0x00100000
|
|
+/** Activate P4
|
|
+ Sets the activation flag of the P4 domain. This domain contains the P4 instance of the GPIO block. */
|
|
+#define ACT_P4 0x00040000
|
|
+/* No-Operation
|
|
+#define ACT_P4_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_P4_SET 0x00040000
|
|
+/** Activate P3
|
|
+ Sets the activation flag of the P3 domain. This domain contains the P3 instance of the GPIO block. */
|
|
+#define ACT_P3 0x00020000
|
|
+/* No-Operation
|
|
+#define ACT_P3_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_P3_SET 0x00020000
|
|
+/** Activate P1
|
|
+ Sets the activation flag of the P1 domain. This domain contains the P1 instance of the GPIO block. */
|
|
+#define ACT_P1 0x00010000
|
|
+/* No-Operation
|
|
+#define ACT_P1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_P1_SET 0x00010000
|
|
+/** Activate HOST
|
|
+ Sets the activation flag of the HOST domain. This domain contains the HOST interface block. */
|
|
+#define ACT_HOST 0x00008000
|
|
+/* No-Operation
|
|
+#define ACT_HOST_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_HOST_SET 0x00008000
|
|
+/** Activate I2C
|
|
+ Sets the activation flag of the I2C domain. This domain contains the I2C interface block. */
|
|
+#define ACT_I2C 0x00004000
|
|
+/* No-Operation
|
|
+#define ACT_I2C_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_I2C_SET 0x00004000
|
|
+/** Activate SSC0
|
|
+ Sets the activation flag of the SSC0 domain. This domain contains the SSC0 interface block. */
|
|
+#define ACT_SSC0 0x00002000
|
|
+/* No-Operation
|
|
+#define ACT_SSC0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_SSC0_SET 0x00002000
|
|
+/** Activate ASC0
|
|
+ Sets the activation flag of the ASC0 domain. This domain contains the ASC0 interface block. */
|
|
+#define ACT_ASC0 0x00001000
|
|
+/* No-Operation
|
|
+#define ACT_ASC0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_ASC0_SET 0x00001000
|
|
+/** Activate ASC1
|
|
+ Sets the activation flag of the ASC1 domain. This domain contains the ASC1 block. */
|
|
+#define ACT_ASC1 0x00000800
|
|
+/* No-Operation
|
|
+#define ACT_ASC1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_ASC1_SET 0x00000800
|
|
+/** Activate DCDCAPD
|
|
+ Sets the activation flag of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
|
|
+#define ACT_DCDCAPD 0x00000400
|
|
+/* No-Operation
|
|
+#define ACT_DCDCAPD_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_DCDCAPD_SET 0x00000400
|
|
+/** Activate DCDCDDR
|
|
+ Sets the activation flag of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
|
|
+#define ACT_DCDCDDR 0x00000200
|
|
+/* No-Operation
|
|
+#define ACT_DCDCDDR_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_DCDCDDR_SET 0x00000200
|
|
+/** Activate DCDC1V0
|
|
+ Sets the activation flag of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
|
|
+#define ACT_DCDC1V0 0x00000100
|
|
+/* No-Operation
|
|
+#define ACT_DCDC1V0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_DCDC1V0_SET 0x00000100
|
|
+/** Activate TRC2MEM
|
|
+ Sets the activation flag of the TRC2MEM domain. This domain contains the TRC2MEM block. */
|
|
+#define ACT_TRC2MEM 0x00000040
|
|
+/* No-Operation
|
|
+#define ACT_TRC2MEM_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_TRC2MEM_SET 0x00000040
|
|
+/** Activate DDR
|
|
+ Sets the activation flag of the DDR domain. This domain contains the DDR interface block. */
|
|
+#define ACT_DDR 0x00000020
|
|
+/* No-Operation
|
|
+#define ACT_DDR_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_DDR_SET 0x00000020
|
|
+/** Activate EBU
|
|
+ Sets the activation flag of the EBU domain. This domain contains the EBU interface block. */
|
|
+#define ACT_EBU 0x00000010
|
|
+/* No-Operation
|
|
+#define ACT_EBU_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define ACT_EBU_SET 0x00000010
|
|
+
|
|
+/* Fields of "Deactivation Register" */
|
|
+/** Deactivate STATUS
|
|
+ Clears the activation flag of the STATUS domain. This domain contains the STATUS block. */
|
|
+#define DEACT_STATUS 0x80000000
|
|
+/* No-Operation
|
|
+#define DEACT_STATUS_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_STATUS_CLR 0x80000000
|
|
+/** Deactivate SHA1
|
|
+ Clears the activation flag of the SHA1 domain. This domain contains the SHA1 block. */
|
|
+#define DEACT_SHA1 0x40000000
|
|
+/* No-Operation
|
|
+#define DEACT_SHA1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_SHA1_CLR 0x40000000
|
|
+/** Deactivate AES
|
|
+ Clears the activation flag of the AES domain. This domain contains the AES block. */
|
|
+#define DEACT_AES 0x20000000
|
|
+/* No-Operation
|
|
+#define DEACT_AES_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_AES_CLR 0x20000000
|
|
+/** Deactivate PCM
|
|
+ Clears the activation flag of the PCM domain. This domain contains the PCM interface block. */
|
|
+#define DEACT_PCM 0x10000000
|
|
+/* No-Operation
|
|
+#define DEACT_PCM_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_PCM_CLR 0x10000000
|
|
+/** Deactivate FSCT
|
|
+ Clears the activation flag of the FSCT domain. This domain contains the FSCT block. */
|
|
+#define DEACT_FSCT 0x08000000
|
|
+/* No-Operation
|
|
+#define DEACT_FSCT_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_FSCT_CLR 0x08000000
|
|
+/** Deactivate GPTC
|
|
+ Clears the activation flag of the GPTC domain. This domain contains the GPTC block. */
|
|
+#define DEACT_GPTC 0x04000000
|
|
+/* No-Operation
|
|
+#define DEACT_GPTC_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_GPTC_CLR 0x04000000
|
|
+/** Deactivate MPS
|
|
+ Clears the activation flag of the MPS domain. This domain contains the MPS block. */
|
|
+#define DEACT_MPS 0x02000000
|
|
+/* No-Operation
|
|
+#define DEACT_MPS_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_MPS_CLR 0x02000000
|
|
+/** Deactivate DFEV0
|
|
+ Clears the activation flag of the DFEV0 domain. This domain contains the DFEV0 block. */
|
|
+#define DEACT_DFEV0 0x01000000
|
|
+/* No-Operation
|
|
+#define DEACT_DFEV0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_DFEV0_CLR 0x01000000
|
|
+/** Deactivate PADCTRL4
|
|
+ Clears the activation flag of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
|
|
+#define DEACT_PADCTRL4 0x00400000
|
|
+/* No-Operation
|
|
+#define DEACT_PADCTRL4_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_PADCTRL4_CLR 0x00400000
|
|
+/** Deactivate PADCTRL3
|
|
+ Clears the activation flag of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
|
|
+#define DEACT_PADCTRL3 0x00200000
|
|
+/* No-Operation
|
|
+#define DEACT_PADCTRL3_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_PADCTRL3_CLR 0x00200000
|
|
+/** Deactivate PADCTRL1
|
|
+ Clears the activation flag of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
|
|
+#define DEACT_PADCTRL1 0x00100000
|
|
+/* No-Operation
|
|
+#define DEACT_PADCTRL1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_PADCTRL1_CLR 0x00100000
|
|
+/** Deactivate P4
|
|
+ Clears the activation flag of the P4 domain. This domain contains the P4 instance of the GPIO block. */
|
|
+#define DEACT_P4 0x00040000
|
|
+/* No-Operation
|
|
+#define DEACT_P4_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_P4_CLR 0x00040000
|
|
+/** Deactivate P3
|
|
+ Clears the activation flag of the P3 domain. This domain contains the P3 instance of the GPIO block. */
|
|
+#define DEACT_P3 0x00020000
|
|
+/* No-Operation
|
|
+#define DEACT_P3_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_P3_CLR 0x00020000
|
|
+/** Deactivate P1
|
|
+ Clears the activation flag of the P1 domain. This domain contains the P1 instance of the GPIO block. */
|
|
+#define DEACT_P1 0x00010000
|
|
+/* No-Operation
|
|
+#define DEACT_P1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_P1_CLR 0x00010000
|
|
+/** Deactivate HOST
|
|
+ Clears the activation flag of the HOST domain. This domain contains the HOST interface block. */
|
|
+#define DEACT_HOST 0x00008000
|
|
+/* No-Operation
|
|
+#define DEACT_HOST_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_HOST_CLR 0x00008000
|
|
+/** Deactivate I2C
|
|
+ Clears the activation flag of the I2C domain. This domain contains the I2C interface block. */
|
|
+#define DEACT_I2C 0x00004000
|
|
+/* No-Operation
|
|
+#define DEACT_I2C_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_I2C_CLR 0x00004000
|
|
+/** Deactivate SSC0
|
|
+ Clears the activation flag of the SSC0 domain. This domain contains the SSC0 interface block. */
|
|
+#define DEACT_SSC0 0x00002000
|
|
+/* No-Operation
|
|
+#define DEACT_SSC0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_SSC0_CLR 0x00002000
|
|
+/** Deactivate ASC0
|
|
+ Clears the activation flag of the ASC0 domain. This domain contains the ASC0 interface block. */
|
|
+#define DEACT_ASC0 0x00001000
|
|
+/* No-Operation
|
|
+#define DEACT_ASC0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_ASC0_CLR 0x00001000
|
|
+/** Deactivate ASC1
|
|
+ Clears the activation flag of the ASC1 domain. This domain contains the ASC1 block. */
|
|
+#define DEACT_ASC1 0x00000800
|
|
+/* No-Operation
|
|
+#define DEACT_ASC1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_ASC1_CLR 0x00000800
|
|
+/** Deactivate DCDCAPD
|
|
+ Clears the activation flag of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
|
|
+#define DEACT_DCDCAPD 0x00000400
|
|
+/* No-Operation
|
|
+#define DEACT_DCDCAPD_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_DCDCAPD_CLR 0x00000400
|
|
+/** Deactivate DCDCDDR
|
|
+ Clears the activation flag of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
|
|
+#define DEACT_DCDCDDR 0x00000200
|
|
+/* No-Operation
|
|
+#define DEACT_DCDCDDR_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_DCDCDDR_CLR 0x00000200
|
|
+/** Deactivate DCDC1V0
|
|
+ Clears the activation flag of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
|
|
+#define DEACT_DCDC1V0 0x00000100
|
|
+/* No-Operation
|
|
+#define DEACT_DCDC1V0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_DCDC1V0_CLR 0x00000100
|
|
+/** Deactivate TRC2MEM
|
|
+ Clears the activation flag of the TRC2MEM domain. This domain contains the TRC2MEM block. */
|
|
+#define DEACT_TRC2MEM 0x00000040
|
|
+/* No-Operation
|
|
+#define DEACT_TRC2MEM_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_TRC2MEM_CLR 0x00000040
|
|
+/** Deactivate DDR
|
|
+ Clears the activation flag of the DDR domain. This domain contains the DDR interface block. */
|
|
+#define DEACT_DDR 0x00000020
|
|
+/* No-Operation
|
|
+#define DEACT_DDR_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_DDR_CLR 0x00000020
|
|
+/** Deactivate EBU
|
|
+ Clears the activation flag of the EBU domain. This domain contains the EBU interface block. */
|
|
+#define DEACT_EBU 0x00000010
|
|
+/* No-Operation
|
|
+#define DEACT_EBU_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define DEACT_EBU_CLR 0x00000010
|
|
+
|
|
+/* Fields of "Reboot Trigger Register" */
|
|
+/** Reboot STATUS
|
|
+ Triggers a reboot of the STATUS domain. This domain contains the STATUS block. */
|
|
+#define RBT_STATUS 0x80000000
|
|
+/* No-Operation
|
|
+#define RBT_STATUS_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_STATUS_TRIG 0x80000000
|
|
+/** Reboot SHA1
|
|
+ Triggers a reboot of the SHA1 domain. This domain contains the SHA1 block. */
|
|
+#define RBT_SHA1 0x40000000
|
|
+/* No-Operation
|
|
+#define RBT_SHA1_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_SHA1_TRIG 0x40000000
|
|
+/** Reboot AES
|
|
+ Triggers a reboot of the AES domain. This domain contains the AES block. */
|
|
+#define RBT_AES 0x20000000
|
|
+/* No-Operation
|
|
+#define RBT_AES_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_AES_TRIG 0x20000000
|
|
+/** Reboot PCM
|
|
+ Triggers a reboot of the PCM domain. This domain contains the PCM interface block. */
|
|
+#define RBT_PCM 0x10000000
|
|
+/* No-Operation
|
|
+#define RBT_PCM_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_PCM_TRIG 0x10000000
|
|
+/** Reboot FSCT
|
|
+ Triggers a reboot of the FSCT domain. This domain contains the FSCT block. */
|
|
+#define RBT_FSCT 0x08000000
|
|
+/* No-Operation
|
|
+#define RBT_FSCT_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_FSCT_TRIG 0x08000000
|
|
+/** Reboot GPTC
|
|
+ Triggers a reboot of the GPTC domain. This domain contains the GPTC block. */
|
|
+#define RBT_GPTC 0x04000000
|
|
+/* No-Operation
|
|
+#define RBT_GPTC_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_GPTC_TRIG 0x04000000
|
|
+/** Reboot MPS
|
|
+ Triggers a reboot of the MPS domain. This domain contains the MPS block. */
|
|
+#define RBT_MPS 0x02000000
|
|
+/* No-Operation
|
|
+#define RBT_MPS_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_MPS_TRIG 0x02000000
|
|
+/** Reboot DFEV0
|
|
+ Triggers a reboot of the DFEV0 domain. This domain contains the DFEV0 block. */
|
|
+#define RBT_DFEV0 0x01000000
|
|
+/* No-Operation
|
|
+#define RBT_DFEV0_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_DFEV0_TRIG 0x01000000
|
|
+/** Reboot PADCTRL4
|
|
+ Triggers a reboot of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */
|
|
+#define RBT_PADCTRL4 0x00400000
|
|
+/* No-Operation
|
|
+#define RBT_PADCTRL4_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_PADCTRL4_TRIG 0x00400000
|
|
+/** Reboot PADCTRL3
|
|
+ Triggers a reboot of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */
|
|
+#define RBT_PADCTRL3 0x00200000
|
|
+/* No-Operation
|
|
+#define RBT_PADCTRL3_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_PADCTRL3_TRIG 0x00200000
|
|
+/** Reboot PADCTRL1
|
|
+ Triggers a reboot of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */
|
|
+#define RBT_PADCTRL1 0x00100000
|
|
+/* No-Operation
|
|
+#define RBT_PADCTRL1_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_PADCTRL1_TRIG 0x00100000
|
|
+/** Reboot P4
|
|
+ Triggers a reboot of the P4 domain. This domain contains the P4 instance of the GPIO block. */
|
|
+#define RBT_P4 0x00040000
|
|
+/* No-Operation
|
|
+#define RBT_P4_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_P4_TRIG 0x00040000
|
|
+/** Reboot P3
|
|
+ Triggers a reboot of the P3 domain. This domain contains the P3 instance of the GPIO block. */
|
|
+#define RBT_P3 0x00020000
|
|
+/* No-Operation
|
|
+#define RBT_P3_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_P3_TRIG 0x00020000
|
|
+/** Reboot P1
|
|
+ Triggers a reboot of the P1 domain. This domain contains the P1 instance of the GPIO block. */
|
|
+#define RBT_P1 0x00010000
|
|
+/* No-Operation
|
|
+#define RBT_P1_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_P1_TRIG 0x00010000
|
|
+/** Reboot HOST
|
|
+ Triggers a reboot of the HOST domain. This domain contains the HOST interface block. */
|
|
+#define RBT_HOST 0x00008000
|
|
+/* No-Operation
|
|
+#define RBT_HOST_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_HOST_TRIG 0x00008000
|
|
+/** Reboot I2C
|
|
+ Triggers a reboot of the I2C domain. This domain contains the I2C interface block. */
|
|
+#define RBT_I2C 0x00004000
|
|
+/* No-Operation
|
|
+#define RBT_I2C_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_I2C_TRIG 0x00004000
|
|
+/** Reboot SSC0
|
|
+ Triggers a reboot of the SSC0 domain. This domain contains the SSC0 interface block. */
|
|
+#define RBT_SSC0 0x00002000
|
|
+/* No-Operation
|
|
+#define RBT_SSC0_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_SSC0_TRIG 0x00002000
|
|
+/** Reboot ASC0
|
|
+ Triggers a reboot of the ASC0 domain. This domain contains the ASC0 interface block. */
|
|
+#define RBT_ASC0 0x00001000
|
|
+/* No-Operation
|
|
+#define RBT_ASC0_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_ASC0_TRIG 0x00001000
|
|
+/** Reboot ASC1
|
|
+ Triggers a reboot of the ASC1 domain. This domain contains the ASC1 block. */
|
|
+#define RBT_ASC1 0x00000800
|
|
+/* No-Operation
|
|
+#define RBT_ASC1_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_ASC1_TRIG 0x00000800
|
|
+/** Reboot DCDCAPD
|
|
+ Triggers a reboot of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */
|
|
+#define RBT_DCDCAPD 0x00000400
|
|
+/* No-Operation
|
|
+#define RBT_DCDCAPD_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_DCDCAPD_TRIG 0x00000400
|
|
+/** Reboot DCDCDDR
|
|
+ Triggers a reboot of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */
|
|
+#define RBT_DCDCDDR 0x00000200
|
|
+/* No-Operation
|
|
+#define RBT_DCDCDDR_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_DCDCDDR_TRIG 0x00000200
|
|
+/** Reboot DCDC1V0
|
|
+ Triggers a reboot of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */
|
|
+#define RBT_DCDC1V0 0x00000100
|
|
+/* No-Operation
|
|
+#define RBT_DCDC1V0_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_DCDC1V0_TRIG 0x00000100
|
|
+/** Reboot TRC2MEM
|
|
+ Triggers a reboot of the TRC2MEM domain. This domain contains the TRC2MEM block. */
|
|
+#define RBT_TRC2MEM 0x00000040
|
|
+/* No-Operation
|
|
+#define RBT_TRC2MEM_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_TRC2MEM_TRIG 0x00000040
|
|
+/** Reboot DDR
|
|
+ Triggers a reboot of the DDR domain. This domain contains the DDR interface block. */
|
|
+#define RBT_DDR 0x00000020
|
|
+/* No-Operation
|
|
+#define RBT_DDR_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_DDR_TRIG 0x00000020
|
|
+/** Reboot EBU
|
|
+ Triggers a reboot of the EBU domain. This domain contains the EBU interface block. */
|
|
+#define RBT_EBU 0x00000010
|
|
+/* No-Operation
|
|
+#define RBT_EBU_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_EBU_TRIG 0x00000010
|
|
+/** Reboot XBAR
|
|
+ Triggers a reboot of the XBAR. */
|
|
+#define RBT_XBAR 0x00000002
|
|
+/* No-Operation
|
|
+#define RBT_XBAR_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_XBAR_TRIG 0x00000002
|
|
+/** Reboot CPU
|
|
+ Triggers a reboot of the CPU. */
|
|
+#define RBT_CPU 0x00000001
|
|
+/* No-Operation
|
|
+#define RBT_CPU_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define RBT_CPU_TRIG 0x00000001
|
|
+
|
|
+/* Fields of "CPU0 Clock Control Register" */
|
|
+/** CPU Clock Divider
|
|
+ Via this bit the divider and therefore the frequency of the clock of CPU0 can be selected. */
|
|
+#define CPU0CC_CPUDIV 0x00000001
|
|
+/* Frequency set to the nominal value.
|
|
+#define CPU0CC_CPUDIV_SELFNOM 0x00000000 */
|
|
+/** Frequency set to half of its nominal value. */
|
|
+#define CPU0CC_CPUDIV_SELFHALF 0x00000001
|
|
+
|
|
+/* Fields of "CPU0 Reset Source Register" */
|
|
+/** Software Reboot Request Occurred
|
|
+ This bit can be acknowledged by a write operation. */
|
|
+#define CPU0RS_SWRRO 0x00000004
|
|
+/* Nothing
|
|
+#define CPU0RS_SWRRO_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the event. */
|
|
+#define CPU0RS_SWRRO_EVACK 0x00000004
|
|
+/** Read: Event occurred. */
|
|
+#define CPU0RS_SWRRO_EVOCC 0x00000004
|
|
+/** Hardware Reset Source
|
|
+ Reflects the root cause for the last hardware reset. The infrastructure-block is only reset in case of POR. For all other blocks there is no difference between the three HW-reset sources. */
|
|
+#define CPU0RS_HWRS_MASK 0x00000003
|
|
+/** field offset */
|
|
+#define CPU0RS_HWRS_OFFSET 0
|
|
+/** Power-on reset. */
|
|
+#define CPU0RS_HWRS_POR 0x00000000
|
|
+/** RST pin. */
|
|
+#define CPU0RS_HWRS_RST 0x00000001
|
|
+/** Watchdog reset request. */
|
|
+#define CPU0RS_HWRS_WDT 0x00000002
|
|
+
|
|
+/* Fields of "CPU0 Wakeup Configuration Register" */
|
|
+/** Wakeup Request Source Yield Resume 15
|
|
+ Select the signal connected to the yield/resume interface pin 15 as source for wakeup from sleep state. */
|
|
+#define CPU0WCFG_WRSYR15 0x80000000
|
|
+/* Not selected
|
|
+#define CPU0WCFG_WRSYR15_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CPU0WCFG_WRSYR15_SEL 0x80000000
|
|
+/** Wakeup Request Source Yield Resume 14
|
|
+ Select the signal connected to the yield/resume interface pin 14 as source for wakeup from sleep state. */
|
|
+#define CPU0WCFG_WRSYR14 0x40000000
|
|
+/* Not selected
|
|
+#define CPU0WCFG_WRSYR14_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CPU0WCFG_WRSYR14_SEL 0x40000000
|
|
+/** Wakeup Request Source Yield Resume 13
|
|
+ Select the signal connected to the yield/resume interface pin 13 as source for wakeup from sleep state. */
|
|
+#define CPU0WCFG_WRSYR13 0x20000000
|
|
+/* Not selected
|
|
+#define CPU0WCFG_WRSYR13_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CPU0WCFG_WRSYR13_SEL 0x20000000
|
|
+/** Wakeup Request Source Yield Resume 12
|
|
+ Select the signal connected to the yield/resume interface pin 12 as source for wakeup from sleep state. */
|
|
+#define CPU0WCFG_WRSYR12 0x10000000
|
|
+/* Not selected
|
|
+#define CPU0WCFG_WRSYR12_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CPU0WCFG_WRSYR12_SEL 0x10000000
|
|
+/** Wakeup Request Source Yield Resume 11
|
|
+ Select the signal connected to the yield/resume interface pin 11 as source for wakeup from sleep state. */
|
|
+#define CPU0WCFG_WRSYR11 0x08000000
|
|
+/* Not selected
|
|
+#define CPU0WCFG_WRSYR11_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CPU0WCFG_WRSYR11_SEL 0x08000000
|
|
+/** Wakeup Request Source Yield Resume 10
|
|
+ Select the signal connected to the yield/resume interface pin 10 as source for wakeup from sleep state. */
|
|
+#define CPU0WCFG_WRSYR10 0x04000000
|
|
+/* Not selected
|
|
+#define CPU0WCFG_WRSYR10_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CPU0WCFG_WRSYR10_SEL 0x04000000
|
|
+/** Wakeup Request Source Yield Resume 9
|
|
+ Select the signal connected to the yield/resume interface pin 9 as source for wakeup from sleep state. */
|
|
+#define CPU0WCFG_WRSYR9 0x02000000
|
|
+/* Not selected
|
|
+#define CPU0WCFG_WRSYR9_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CPU0WCFG_WRSYR9_SEL 0x02000000
|
|
+/** Wakeup Request Source Yield Resume 8
|
|
+ Select the signal connected to the yield/resume interface pin 8 as source for wakeup from sleep state. */
|
|
+#define CPU0WCFG_WRSYR8 0x01000000
|
|
+/* Not selected
|
|
+#define CPU0WCFG_WRSYR8_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CPU0WCFG_WRSYR8_SEL 0x01000000
|
|
+/** Wakeup Request Source Yield Resume 7
|
|
+ Select the signal connected to the yield/resume interface pin 7 as source for wakeup from sleep state. */
|
|
+#define CPU0WCFG_WRSYR7 0x00800000
|
|
+/* Not selected
|
|
+#define CPU0WCFG_WRSYR7_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CPU0WCFG_WRSYR7_SEL 0x00800000
|
|
+/** Wakeup Request Source Yield Resume 6
|
|
+ Select the signal connected to the yield/resume interface pin 6 as source for wakeup from sleep state. */
|
|
+#define CPU0WCFG_WRSYR6 0x00400000
|
|
+/* Not selected
|
|
+#define CPU0WCFG_WRSYR6_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CPU0WCFG_WRSYR6_SEL 0x00400000
|
|
+/** Wakeup Request Source Yield Resume 5
|
|
+ Select the signal connected to the yield/resume interface pin 5 as source for wakeup from sleep state. */
|
|
+#define CPU0WCFG_WRSYR5 0x00200000
|
|
+/* Not selected
|
|
+#define CPU0WCFG_WRSYR5_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CPU0WCFG_WRSYR5_SEL 0x00200000
|
|
+/** Wakeup Request Source Yield Resume 4
|
|
+ Select the signal connected to the yield/resume interface pin 4 as source for wakeup from sleep state. */
|
|
+#define CPU0WCFG_WRSYR4 0x00100000
|
|
+/* Not selected
|
|
+#define CPU0WCFG_WRSYR4_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CPU0WCFG_WRSYR4_SEL 0x00100000
|
|
+/** Wakeup Request Source Yield Resume 3
|
|
+ Select the signal connected to the yield/resume interface pin 3 as source for wakeup from sleep state. */
|
|
+#define CPU0WCFG_WRSYR3 0x00080000
|
|
+/* Not selected
|
|
+#define CPU0WCFG_WRSYR3_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CPU0WCFG_WRSYR3_SEL 0x00080000
|
|
+/** Wakeup Request Source Yield Resume 2
|
|
+ Select the signal connected to the yield/resume interface pin 2 as source for wakeup from sleep state. */
|
|
+#define CPU0WCFG_WRSYR2 0x00040000
|
|
+/* Not selected
|
|
+#define CPU0WCFG_WRSYR2_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CPU0WCFG_WRSYR2_SEL 0x00040000
|
|
+/** Wakeup Request Source Yield Resume 1
|
|
+ Select the signal connected to the yield/resume interface pin 1 as source for wakeup from sleep state. */
|
|
+#define CPU0WCFG_WRSYR1 0x00020000
|
|
+/* Not selected
|
|
+#define CPU0WCFG_WRSYR1_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CPU0WCFG_WRSYR1_SEL 0x00020000
|
|
+/** Wakeup Request Source Yield Resume 0
|
|
+ Select the signal connected to the yield/resume interface pin 0 as source for wakeup from sleep state. */
|
|
+#define CPU0WCFG_WRSYR0 0x00010000
|
|
+/* Not selected
|
|
+#define CPU0WCFG_WRSYR0_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CPU0WCFG_WRSYR0_SEL 0x00010000
|
|
+/** Wakeup Request Source Debug
|
|
+ Select signal EJ_DINT as source for wakeup from sleep state. */
|
|
+#define CPU0WCFG_WRSDBG 0x00000100
|
|
+/* Not selected
|
|
+#define CPU0WCFG_WRSDBG_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CPU0WCFG_WRSDBG_SEL 0x00000100
|
|
+/** Wakeup Request Source ICU of VPE1
|
|
+ Select signal ICU_IRQ of VPE1 as source for wakeup from sleep state. */
|
|
+#define CPU0WCFG_WRSICUVPE1 0x00000002
|
|
+/* Not selected
|
|
+#define CPU0WCFG_WRSICUVPE1_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CPU0WCFG_WRSICUVPE1_SEL 0x00000002
|
|
+/** Wakeup Request Source ICU of VPE0
|
|
+ Select signal ICU_IRQ of VPE0 as source for wakeup from sleep state. */
|
|
+#define CPU0WCFG_WRSICUVPE0 0x00000001
|
|
+/* Not selected
|
|
+#define CPU0WCFG_WRSICUVPE0_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CPU0WCFG_WRSICUVPE0_SEL 0x00000001
|
|
+
|
|
+/* Fields of "Bootmode Control Register" */
|
|
+/** Software Bootmode Select
|
|
+ Enables SW writing of Bootmode and shows whether or not the SW-programmed bootmode is reflected in field Bootmode instead of the hardware given value. */
|
|
+#define BMC_BMSW 0x80000000
|
|
+/* Disable
|
|
+#define BMC_BMSW_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define BMC_BMSW_EN 0x80000000
|
|
+/** Bootmode
|
|
+ Initially this field holds the value of the pinstraps LED_BMODEx on positions 5:0, and the value of the corresponding JTAG register bit on position 6. Writing is enabled by setting Software Bootmode Select to 1 during the write cycle. */
|
|
+#define BMC_BM_MASK 0x0000007F
|
|
+/** field offset */
|
|
+#define BMC_BM_OFFSET 0
|
|
+
|
|
+/* Fields of "Sleep Configuration Register" */
|
|
+/** Enable XBAR Clockoff When All XBAR masters Clockoff
|
|
+ Enable XBAR clock shutdown in case all XBAR masters are in clockoff mode. This bit has no effect if bit CPU0 is not enabled. */
|
|
+#define SCFG_XBAR 0x00010000
|
|
+/* Disable
|
|
+#define SCFG_XBAR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SCFG_XBAR_EN 0x00010000
|
|
+/** CPU0 Clockoff On Sleep
|
|
+ Enable CPU0 clock shutdown in case its SI_SLEEP signal becomes active. */
|
|
+#define SCFG_CPU0 0x00000001
|
|
+/* Disable
|
|
+#define SCFG_CPU0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SCFG_CPU0_EN 0x00000001
|
|
+
|
|
+/* Fields of "Power Down Configuration Register" */
|
|
+/** Enable Power Down STATUS
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_STATUS 0x80000000
|
|
+/* Disable
|
|
+#define PDCFG_STATUS_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_STATUS_EN 0x80000000
|
|
+/** Enable Power Down SHA1
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_SHA1 0x40000000
|
|
+/* Disable
|
|
+#define PDCFG_SHA1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_SHA1_EN 0x40000000
|
|
+/** Enable Power Down AES
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_AES 0x20000000
|
|
+/* Disable
|
|
+#define PDCFG_AES_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_AES_EN 0x20000000
|
|
+/** Enable Power Down PCM
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_PCM 0x10000000
|
|
+/* Disable
|
|
+#define PDCFG_PCM_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_PCM_EN 0x10000000
|
|
+/** Enable Power Down FSCT
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_FSCT 0x08000000
|
|
+/* Disable
|
|
+#define PDCFG_FSCT_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_FSCT_EN 0x08000000
|
|
+/** Enable Power Down GPTC
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_GPTC 0x04000000
|
|
+/* Disable
|
|
+#define PDCFG_GPTC_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_GPTC_EN 0x04000000
|
|
+/** Enable Power Down MPS
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_MPS 0x02000000
|
|
+/* Disable
|
|
+#define PDCFG_MPS_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_MPS_EN 0x02000000
|
|
+/** Enable Power Down DFEV0
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_DFEV0 0x01000000
|
|
+/* Disable
|
|
+#define PDCFG_DFEV0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_DFEV0_EN 0x01000000
|
|
+/** Enable Power Down PADCTRL4
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_PADCTRL4 0x00400000
|
|
+/* Disable
|
|
+#define PDCFG_PADCTRL4_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_PADCTRL4_EN 0x00400000
|
|
+/** Enable Power Down PADCTRL3
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_PADCTRL3 0x00200000
|
|
+/* Disable
|
|
+#define PDCFG_PADCTRL3_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_PADCTRL3_EN 0x00200000
|
|
+/** Enable Power Down PADCTRL1
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_PADCTRL1 0x00100000
|
|
+/* Disable
|
|
+#define PDCFG_PADCTRL1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_PADCTRL1_EN 0x00100000
|
|
+/** Enable Power Down P4
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_P4 0x00040000
|
|
+/* Disable
|
|
+#define PDCFG_P4_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_P4_EN 0x00040000
|
|
+/** Enable Power Down P3
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_P3 0x00020000
|
|
+/* Disable
|
|
+#define PDCFG_P3_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_P3_EN 0x00020000
|
|
+/** Enable Power Down P1
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_P1 0x00010000
|
|
+/* Disable
|
|
+#define PDCFG_P1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_P1_EN 0x00010000
|
|
+/** Enable Power Down HOST
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_HOST 0x00008000
|
|
+/* Disable
|
|
+#define PDCFG_HOST_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_HOST_EN 0x00008000
|
|
+/** Enable Power Down I2C
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_I2C 0x00004000
|
|
+/* Disable
|
|
+#define PDCFG_I2C_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_I2C_EN 0x00004000
|
|
+/** Enable Power Down SSC0
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_SSC0 0x00002000
|
|
+/* Disable
|
|
+#define PDCFG_SSC0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_SSC0_EN 0x00002000
|
|
+/** Enable Power Down ASC0
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_ASC0 0x00001000
|
|
+/* Disable
|
|
+#define PDCFG_ASC0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_ASC0_EN 0x00001000
|
|
+/** Enable Power Down ASC1
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_ASC1 0x00000800
|
|
+/* Disable
|
|
+#define PDCFG_ASC1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_ASC1_EN 0x00000800
|
|
+/** Enable Power Down DCDCAPD
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_DCDCAPD 0x00000400
|
|
+/* Disable
|
|
+#define PDCFG_DCDCAPD_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_DCDCAPD_EN 0x00000400
|
|
+/** Enable Power Down DCDCDDR
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_DCDCDDR 0x00000200
|
|
+/* Disable
|
|
+#define PDCFG_DCDCDDR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_DCDCDDR_EN 0x00000200
|
|
+/** Enable Power Down DCDC1V0
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_DCDC1V0 0x00000100
|
|
+/* Disable
|
|
+#define PDCFG_DCDC1V0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_DCDC1V0_EN 0x00000100
|
|
+/** Enable Power Down TRC2MEM
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_TRC2MEM 0x00000040
|
|
+/* Disable
|
|
+#define PDCFG_TRC2MEM_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_TRC2MEM_EN 0x00000040
|
|
+/** Enable Power Down DDR
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_DDR 0x00000020
|
|
+/* Disable
|
|
+#define PDCFG_DDR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_DDR_EN 0x00000020
|
|
+/** Enable Power Down EBU
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define PDCFG_EBU 0x00000010
|
|
+/* Disable
|
|
+#define PDCFG_EBU_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define PDCFG_EBU_EN 0x00000010
|
|
+
|
|
+/* Fields of "CLKO Pad Control Register" */
|
|
+/** Ethernet Reference Clock CLKO Select
|
|
+ Selects the CLKO pad's input as source for the GPHY, SGMII PLLs. */
|
|
+#define CLKOC_ETHREF 0x00000002
|
|
+/* Not selected
|
|
+#define CLKOC_ETHREF_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define CLKOC_ETHREF_SEL 0x00000002
|
|
+/** Output Enable
|
|
+ Enables the output driver of the CLKO pad. */
|
|
+#define CLKOC_OEN 0x00000001
|
|
+/* Disable
|
|
+#define CLKOC_OEN_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define CLKOC_OEN_EN 0x00000001
|
|
+
|
|
+/* Fields of "Infrastructure Control Register" */
|
|
+/** General Purpose Control
|
|
+ Backup bits. Currently they are connected as: bit 0 : connected to the configmode_on pin of the pinstrapping block. bit 1 : clock enable of the GPE primary clock. bits 3:2 : frequency select of the GPE primary clock. 00 = 769.2MHz, 01 = 625MHz, 10 = 555.6MHz, 11 = 500MHz All other bits are unconnected. */
|
|
+#define INFRAC_GP_MASK 0x1F000000
|
|
+/** field offset */
|
|
+#define INFRAC_GP_OFFSET 24
|
|
+/** CMOS2CML Ethernet Control
|
|
+ CMOS2CML Ethernet Control. */
|
|
+#define INFRAC_CMOS2CML_GPON_MASK 0x0000F000
|
|
+/** field offset */
|
|
+#define INFRAC_CMOS2CML_GPON_OFFSET 12
|
|
+/** CMOS2CML Ethernet Control
|
|
+ CMOS2CML Ethernet Control. */
|
|
+#define INFRAC_CMOS2CML_ETH_MASK 0x00000F00
|
|
+/** field offset */
|
|
+#define INFRAC_CMOS2CML_ETH_OFFSET 8
|
|
+/** Dying Gasp Enable
|
|
+ Enables the dying gasp detector. */
|
|
+#define INFRAC_DGASPEN 0x00000040
|
|
+/* Disable
|
|
+#define INFRAC_DGASPEN_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define INFRAC_DGASPEN_EN 0x00000040
|
|
+/** Dying Gasp Hysteresis Control
|
|
+ Dying Gasp Hysteresis Control. */
|
|
+#define INFRAC_DGASPHYS_MASK 0x00000030
|
|
+/** field offset */
|
|
+#define INFRAC_DGASPHYS_OFFSET 4
|
|
+/** Linear Regulator 1.5V Enable
|
|
+ Enables 1.5V linear regulator. */
|
|
+#define INFRAC_LIN1V5EN 0x00000008
|
|
+/* Disable
|
|
+#define INFRAC_LIN1V5EN_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define INFRAC_LIN1V5EN_EN 0x00000008
|
|
+/** Linear Regulator 1.5V Control
|
|
+ Linear regulator 1.5V control. */
|
|
+#define INFRAC_LIN1V5C_MASK 0x00000007
|
|
+/** field offset */
|
|
+#define INFRAC_LIN1V5C_OFFSET 0
|
|
+
|
|
+/* Fields of "HRST_OUT_N Control Register" */
|
|
+/** HRST_OUT_N Pin Value
|
|
+ Controls the value of the HRST_OUT_N pin. */
|
|
+#define HRSTOUTC_VALUE 0x00000001
|
|
+
|
|
+/* Fields of "EBU Clock Control Register" */
|
|
+/** EBU Clock Divider
|
|
+ Via this bit the frequency of the clock of the EBU can be selected. */
|
|
+#define EBUCC_EBUDIV 0x00000001
|
|
+/* Frequency set to 50MHz.
|
|
+#define EBUCC_EBUDIV_SELF50 0x00000000 */
|
|
+/** Frequency set to 100MHz. */
|
|
+#define EBUCC_EBUDIV_SELF100 0x00000001
|
|
+
|
|
+/* Fields of "NMI Status Register" */
|
|
+/** NMI Status Flag TEST
|
|
+ Shows whether the event NMI TEST occurred. */
|
|
+#define NMIS_TEST 0x00000100
|
|
+/* Nothing
|
|
+#define NMIS_TEST_NULL 0x00000000 */
|
|
+/** Read: Event occurred. */
|
|
+#define NMIS_TEST_EVOCC 0x00000100
|
|
+/** NMI Status Flag DGASP
|
|
+ Shows whether the event NMI DGASP occurred. */
|
|
+#define NMIS_DGASP 0x00000004
|
|
+/* Nothing
|
|
+#define NMIS_DGASP_NULL 0x00000000 */
|
|
+/** Read: Event occurred. */
|
|
+#define NMIS_DGASP_EVOCC 0x00000004
|
|
+/** NMI Status Flag HOST
|
|
+ Shows whether the event NMI HOST occurred. */
|
|
+#define NMIS_HOST 0x00000002
|
|
+/* Nothing
|
|
+#define NMIS_HOST_NULL 0x00000000 */
|
|
+/** Read: Event occurred. */
|
|
+#define NMIS_HOST_EVOCC 0x00000002
|
|
+/** NMI Status Flag PIN
|
|
+ Shows whether the event NMI PIN occurred. */
|
|
+#define NMIS_PIN 0x00000001
|
|
+/* Nothing
|
|
+#define NMIS_PIN_NULL 0x00000000 */
|
|
+/** Read: Event occurred. */
|
|
+#define NMIS_PIN_EVOCC 0x00000001
|
|
+
|
|
+/* Fields of "NMI Set Register" */
|
|
+/** Set NMI Status Flag TEST
|
|
+ Sets the corresponding NMI status flag. */
|
|
+#define NMISET_TEST 0x00000100
|
|
+/* Nothing
|
|
+#define NMISET_TEST_NULL 0x00000000 */
|
|
+/** Set */
|
|
+#define NMISET_TEST_SET 0x00000100
|
|
+/** Set NMI Status Flag DGASP
|
|
+ Sets the corresponding NMI status flag. */
|
|
+#define NMISET_DGASP 0x00000004
|
|
+/* Nothing
|
|
+#define NMISET_DGASP_NULL 0x00000000 */
|
|
+/** Set */
|
|
+#define NMISET_DGASP_SET 0x00000004
|
|
+/** Set NMI Status Flag HOST
|
|
+ Sets the corresponding NMI status flag. */
|
|
+#define NMISET_HOST 0x00000002
|
|
+/* Nothing
|
|
+#define NMISET_HOST_NULL 0x00000000 */
|
|
+/** Set */
|
|
+#define NMISET_HOST_SET 0x00000002
|
|
+/** Set NMI Status Flag PIN
|
|
+ Sets the corresponding NMI status flag. */
|
|
+#define NMISET_PIN 0x00000001
|
|
+/* Nothing
|
|
+#define NMISET_PIN_NULL 0x00000000 */
|
|
+/** Set */
|
|
+#define NMISET_PIN_SET 0x00000001
|
|
+
|
|
+/* Fields of "NMI Clear Register" */
|
|
+/** Clear NMI Status Flag TEST
|
|
+ Clears the corresponding NMI status flag. */
|
|
+#define NMICLR_TEST 0x00000100
|
|
+/* Nothing
|
|
+#define NMICLR_TEST_NULL 0x00000000 */
|
|
+/** Clear */
|
|
+#define NMICLR_TEST_CLR 0x00000100
|
|
+/** Clear NMI Status Flag DGASP
|
|
+ Clears the corresponding NMI status flag. */
|
|
+#define NMICLR_DGASP 0x00000004
|
|
+/* Nothing
|
|
+#define NMICLR_DGASP_NULL 0x00000000 */
|
|
+/** Clear */
|
|
+#define NMICLR_DGASP_CLR 0x00000004
|
|
+/** Clear NMI Status Flag HOST
|
|
+ Clears the corresponding NMI status flag. */
|
|
+#define NMICLR_HOST 0x00000002
|
|
+/* Nothing
|
|
+#define NMICLR_HOST_NULL 0x00000000 */
|
|
+/** Clear */
|
|
+#define NMICLR_HOST_CLR 0x00000002
|
|
+/** Clear NMI Status Flag PIN
|
|
+ Clears the corresponding NMI status flag. */
|
|
+#define NMICLR_PIN 0x00000001
|
|
+/* Nothing
|
|
+#define NMICLR_PIN_NULL 0x00000000 */
|
|
+/** Clear */
|
|
+#define NMICLR_PIN_CLR 0x00000001
|
|
+
|
|
+/* Fields of "NMI Test Configuration Register" */
|
|
+/** Enable NMI Test Feature
|
|
+ Enables the operation of the NMI TEST flag. This is the mask for the Non-Maskable-Interrupt dedicated to SW tests. All others cannot be masked. */
|
|
+#define NMITCFG_TEN 0x00000100
|
|
+/* Disable
|
|
+#define NMITCFG_TEN_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define NMITCFG_TEN_EN 0x00000100
|
|
+
|
|
+/* Fields of "NMI VPE1 Control Register" */
|
|
+/** NMI VPE1 State
|
|
+ Reflects the state of the NMI signal towards VPE1. This bit is controlled by software only, there is no hardware NMI source dedicated to VPE1. So VPE0 could trigger an NMI at VPE1 using this bit in its own NMI-routine. */
|
|
+#define NMIVPE1C_NMI 0x00000001
|
|
+/* False
|
|
+#define NMIVPE1C_NMI_FALSE 0x00000000 */
|
|
+/** True */
|
|
+#define NMIVPE1C_NMI_TRUE 0x00000001
|
|
+
|
|
+/* Fields of "IRN Capture Register" */
|
|
+/** DCDCAPD Alarm
|
|
+ The DCDC Converter for the APD Supply submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define IRNCR_DCDCAPD 0x00400000
|
|
+/* Nothing
|
|
+#define IRNCR_DCDCAPD_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define IRNCR_DCDCAPD_INTACK 0x00400000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define IRNCR_DCDCAPD_INTOCC 0x00400000
|
|
+/** DCDCDDR Alarm
|
|
+ The DCDC Converter for the DDR Supply submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define IRNCR_DCDCDDR 0x00200000
|
|
+/* Nothing
|
|
+#define IRNCR_DCDCDDR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define IRNCR_DCDCDDR_INTACK 0x00200000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define IRNCR_DCDCDDR_INTOCC 0x00200000
|
|
+/** DCDC1V0 Alarm
|
|
+ The DCDC Converter for the 1.0 Volts submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define IRNCR_DCDC1V0 0x00100000
|
|
+/* Nothing
|
|
+#define IRNCR_DCDC1V0_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define IRNCR_DCDC1V0_INTACK 0x00100000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define IRNCR_DCDC1V0_INTOCC 0x00100000
|
|
+/** SIF0 wakeup request
|
|
+ SmartSlic Interface 0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define IRNCR_SIF0 0x00010000
|
|
+/* Nothing
|
|
+#define IRNCR_SIF0_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define IRNCR_SIF0_INTACK 0x00010000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define IRNCR_SIF0_INTOCC 0x00010000
|
|
+
|
|
+/* Fields of "IRN Interrupt Control Register" */
|
|
+/** DCDCAPD Alarm
|
|
+ Interrupt control bit for the corresponding bit in the IRNCR register. */
|
|
+#define IRNICR_DCDCAPD 0x00400000
|
|
+/** DCDCDDR Alarm
|
|
+ Interrupt control bit for the corresponding bit in the IRNCR register. */
|
|
+#define IRNICR_DCDCDDR 0x00200000
|
|
+/** DCDC1V0 Alarm
|
|
+ Interrupt control bit for the corresponding bit in the IRNCR register. */
|
|
+#define IRNICR_DCDC1V0 0x00100000
|
|
+/** SIF0 wakeup request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCR register. */
|
|
+#define IRNICR_SIF0 0x00010000
|
|
+
|
|
+/* Fields of "IRN Interrupt Enable Register" */
|
|
+/** DCDCAPD Alarm
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCR register. */
|
|
+#define IRNEN_DCDCAPD 0x00400000
|
|
+/* Disable
|
|
+#define IRNEN_DCDCAPD_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define IRNEN_DCDCAPD_EN 0x00400000
|
|
+/** DCDCDDR Alarm
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCR register. */
|
|
+#define IRNEN_DCDCDDR 0x00200000
|
|
+/* Disable
|
|
+#define IRNEN_DCDCDDR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define IRNEN_DCDCDDR_EN 0x00200000
|
|
+/** DCDC1V0 Alarm
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCR register. */
|
|
+#define IRNEN_DCDC1V0 0x00100000
|
|
+/* Disable
|
|
+#define IRNEN_DCDC1V0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define IRNEN_DCDC1V0_EN 0x00100000
|
|
+/** SIF0 wakeup request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCR register. */
|
|
+#define IRNEN_SIF0 0x00010000
|
|
+/* Disable
|
|
+#define IRNEN_SIF0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define IRNEN_SIF0_EN 0x00010000
|
|
+
|
|
+/*! @} */ /* SYS1_REGISTER */
|
|
+
|
|
+#endif /* _sys1_reg_h */
|
|
--- /dev/null
|
|
+++ b/arch/mips/include/asm/mach-lantiq/falcon/sys_eth_reg.h
|
|
@@ -0,0 +1,1132 @@
|
|
+/******************************************************************************
|
|
+
|
|
+ Copyright (c) 2010
|
|
+ Lantiq Deutschland GmbH
|
|
+
|
|
+ For licensing information, see the file 'LICENSE' in the root folder of
|
|
+ this software module.
|
|
+
|
|
+******************************************************************************/
|
|
+
|
|
+#ifndef _sys_eth_reg_h
|
|
+#define _sys_eth_reg_h
|
|
+
|
|
+/** \addtogroup SYS_ETH_REGISTER
|
|
+ @{
|
|
+*/
|
|
+/* access macros */
|
|
+#define sys_eth_r32(reg) reg_r32(&sys_eth->reg)
|
|
+#define sys_eth_w32(val, reg) reg_w32(val, &sys_eth->reg)
|
|
+#define sys_eth_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys_eth->reg)
|
|
+#define sys_eth_r32_table(reg, idx) reg_r32_table(sys_eth->reg, idx)
|
|
+#define sys_eth_w32_table(val, reg, idx) reg_w32_table(val, sys_eth->reg, idx)
|
|
+#define sys_eth_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys_eth->reg, idx)
|
|
+#define sys_eth_adr_table(reg, idx) adr_table(sys_eth->reg, idx)
|
|
+
|
|
+
|
|
+/** SYS_ETH register structure */
|
|
+struct gpon_reg_sys_eth
|
|
+{
|
|
+ /** Clock Status Register */
|
|
+ unsigned int clks; /* 0x00000000 */
|
|
+ /** Clock Enable Register
|
|
+ Via this register the clocks for the domains can be enabled. */
|
|
+ unsigned int clken; /* 0x00000004 */
|
|
+ /** Clock Clear Register
|
|
+ Via this register the clocks for the domains can be disabled. */
|
|
+ unsigned int clkclr; /* 0x00000008 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_0[5]; /* 0x0000000C */
|
|
+ /** Activation Status Register */
|
|
+ unsigned int acts; /* 0x00000020 */
|
|
+ /** Activation Register
|
|
+ Via this register the domains can be activated. */
|
|
+ unsigned int act; /* 0x00000024 */
|
|
+ /** Deactivation Register
|
|
+ Via this register the domains can be deactivated. */
|
|
+ unsigned int deact; /* 0x00000028 */
|
|
+ /** Reboot Trigger Register
|
|
+ Via this register the domains can be rebooted (sent through reset). */
|
|
+ unsigned int rbt; /* 0x0000002C */
|
|
+ /** Reserved */
|
|
+ unsigned int res_1[32]; /* 0x00000030 */
|
|
+ /** External PHY Control Register */
|
|
+ unsigned int extphyc; /* 0x000000B0 */
|
|
+ /** Power Down Configuration Register
|
|
+ Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be removed. */
|
|
+ unsigned int pdcfg; /* 0x000000B4 */
|
|
+ /** Datarate Control Register
|
|
+ Controls the datarate of the various physical layers. The contents of the writeable fields of this register shall not be changed during operation. */
|
|
+ unsigned int drc; /* 0x000000B8 */
|
|
+ /** GMAC Multiplexer Control Register
|
|
+ Controls the interconnect between GMACs and the various physical layers. All fields need to have a different content. If two GMACs are muxed to the same PHY unpredictable results may occur. The contents of this register shall not be changed during operation. */
|
|
+ unsigned int gmuxc; /* 0x000000BC */
|
|
+ /** Datarate Status Register
|
|
+ Shows the datarate of the GMACs. The datarate of a GMAC is derived from the datarate of the physical layer it is multiplexed to. This register is for debugging only. */
|
|
+ unsigned int drs; /* 0x000000C0 */
|
|
+ /** SGMII Control Register */
|
|
+ unsigned int sgmiic; /* 0x000000C4 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_2[14]; /* 0x000000C8 */
|
|
+};
|
|
+
|
|
+
|
|
+/* Fields of "Clock Status Register" */
|
|
+/** GPHY1MII2 Clock Enable
|
|
+ Shows the clock enable bit for GPHY1MII2. */
|
|
+#define SYS_ETH_CLKS_GPHY1MII2 0x02000000
|
|
+/* Disable
|
|
+#define SYS_ETH_CLKS_GPHY1MII2_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_CLKS_GPHY1MII2_EN 0x02000000
|
|
+/** GPHY0MII2 Clock Enable
|
|
+ Shows the clock enable bit for GPHY0MII2. */
|
|
+#define SYS_ETH_CLKS_GPHY0MII2 0x01000000
|
|
+/* Disable
|
|
+#define SYS_ETH_CLKS_GPHY0MII2_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_CLKS_GPHY0MII2_EN 0x01000000
|
|
+/** PADCTRL2 Clock Enable
|
|
+ Shows the clock enable bit for the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
|
|
+#define SYS_ETH_CLKS_PADCTRL2 0x00200000
|
|
+/* Disable
|
|
+#define SYS_ETH_CLKS_PADCTRL2_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_CLKS_PADCTRL2_EN 0x00200000
|
|
+/** PADCTRL0 Clock Enable
|
|
+ Shows the clock enable bit for the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
|
|
+#define SYS_ETH_CLKS_PADCTRL0 0x00100000
|
|
+/* Disable
|
|
+#define SYS_ETH_CLKS_PADCTRL0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_CLKS_PADCTRL0_EN 0x00100000
|
|
+/** P2 Clock Enable
|
|
+ Shows the clock enable bit for the P2 domain. This domain contains the P2 instance of the GPIO block. */
|
|
+#define SYS_ETH_CLKS_P2 0x00020000
|
|
+/* Disable
|
|
+#define SYS_ETH_CLKS_P2_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_CLKS_P2_EN 0x00020000
|
|
+/** P0 Clock Enable
|
|
+ Shows the clock enable bit for the P0 domain. This domain contains the P0 instance of the GPIO block. */
|
|
+#define SYS_ETH_CLKS_P0 0x00010000
|
|
+/* Disable
|
|
+#define SYS_ETH_CLKS_P0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_CLKS_P0_EN 0x00010000
|
|
+/** xMII Clock Enable
|
|
+ Shows the clock enable bit for the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
|
|
+#define SYS_ETH_CLKS_xMII 0x00000800
|
|
+/* Disable
|
|
+#define SYS_ETH_CLKS_xMII_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_CLKS_xMII_EN 0x00000800
|
|
+/** SGMII Clock Enable
|
|
+ Shows the clock enable bit for the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_CLKS_SGMII 0x00000400
|
|
+/* Disable
|
|
+#define SYS_ETH_CLKS_SGMII_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_CLKS_SGMII_EN 0x00000400
|
|
+/** GPHY1 Clock Enable
|
|
+ Shows the clock enable bit for the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_CLKS_GPHY1 0x00000200
|
|
+/* Disable
|
|
+#define SYS_ETH_CLKS_GPHY1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_CLKS_GPHY1_EN 0x00000200
|
|
+/** GPHY0 Clock Enable
|
|
+ Shows the clock enable bit for the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_CLKS_GPHY0 0x00000100
|
|
+/* Disable
|
|
+#define SYS_ETH_CLKS_GPHY0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_CLKS_GPHY0_EN 0x00000100
|
|
+/** MDIO Clock Enable
|
|
+ Shows the clock enable bit for the MDIO domain. This domain contains the MDIO block. */
|
|
+#define SYS_ETH_CLKS_MDIO 0x00000080
|
|
+/* Disable
|
|
+#define SYS_ETH_CLKS_MDIO_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_CLKS_MDIO_EN 0x00000080
|
|
+/** GMAC3 Clock Enable
|
|
+ Shows the clock enable bit for the GMAC3 domain. This domain contains the GMAC3 block. */
|
|
+#define SYS_ETH_CLKS_GMAC3 0x00000008
|
|
+/* Disable
|
|
+#define SYS_ETH_CLKS_GMAC3_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_CLKS_GMAC3_EN 0x00000008
|
|
+/** GMAC2 Clock Enable
|
|
+ Shows the clock enable bit for the GMAC2 domain. This domain contains the GMAC2 block. */
|
|
+#define SYS_ETH_CLKS_GMAC2 0x00000004
|
|
+/* Disable
|
|
+#define SYS_ETH_CLKS_GMAC2_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_CLKS_GMAC2_EN 0x00000004
|
|
+/** GMAC1 Clock Enable
|
|
+ Shows the clock enable bit for the GMAC1 domain. This domain contains the GMAC1 block. */
|
|
+#define SYS_ETH_CLKS_GMAC1 0x00000002
|
|
+/* Disable
|
|
+#define SYS_ETH_CLKS_GMAC1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_CLKS_GMAC1_EN 0x00000002
|
|
+/** GMAC0 Clock Enable
|
|
+ Shows the clock enable bit for the GMAC0 domain. This domain contains the GMAC0 block. */
|
|
+#define SYS_ETH_CLKS_GMAC0 0x00000001
|
|
+/* Disable
|
|
+#define SYS_ETH_CLKS_GMAC0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_CLKS_GMAC0_EN 0x00000001
|
|
+
|
|
+/* Fields of "Clock Enable Register" */
|
|
+/** Set Clock Enable GPHY1MII2
|
|
+ Sets the clock enable bit of the GPHY1MII2. */
|
|
+#define SYS_ETH_CLKEN_GPHY1MII2 0x02000000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKEN_GPHY1MII2_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_CLKEN_GPHY1MII2_SET 0x02000000
|
|
+/** Set Clock Enable GPHY0MII2
|
|
+ Sets the clock enable bit of the GPHY0MII2. */
|
|
+#define SYS_ETH_CLKEN_GPHY0MII2 0x01000000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKEN_GPHY0MII2_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_CLKEN_GPHY0MII2_SET 0x01000000
|
|
+/** Set Clock Enable PADCTRL2
|
|
+ Sets the clock enable bit of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
|
|
+#define SYS_ETH_CLKEN_PADCTRL2 0x00200000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKEN_PADCTRL2_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_CLKEN_PADCTRL2_SET 0x00200000
|
|
+/** Set Clock Enable PADCTRL0
|
|
+ Sets the clock enable bit of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
|
|
+#define SYS_ETH_CLKEN_PADCTRL0 0x00100000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKEN_PADCTRL0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_CLKEN_PADCTRL0_SET 0x00100000
|
|
+/** Set Clock Enable P2
|
|
+ Sets the clock enable bit of the P2 domain. This domain contains the P2 instance of the GPIO block. */
|
|
+#define SYS_ETH_CLKEN_P2 0x00020000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKEN_P2_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_CLKEN_P2_SET 0x00020000
|
|
+/** Set Clock Enable P0
|
|
+ Sets the clock enable bit of the P0 domain. This domain contains the P0 instance of the GPIO block. */
|
|
+#define SYS_ETH_CLKEN_P0 0x00010000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKEN_P0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_CLKEN_P0_SET 0x00010000
|
|
+/** Set Clock Enable xMII
|
|
+ Sets the clock enable bit of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
|
|
+#define SYS_ETH_CLKEN_xMII 0x00000800
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKEN_xMII_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_CLKEN_xMII_SET 0x00000800
|
|
+/** Set Clock Enable SGMII
|
|
+ Sets the clock enable bit of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_CLKEN_SGMII 0x00000400
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKEN_SGMII_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_CLKEN_SGMII_SET 0x00000400
|
|
+/** Set Clock Enable GPHY1
|
|
+ Sets the clock enable bit of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_CLKEN_GPHY1 0x00000200
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKEN_GPHY1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_CLKEN_GPHY1_SET 0x00000200
|
|
+/** Set Clock Enable GPHY0
|
|
+ Sets the clock enable bit of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_CLKEN_GPHY0 0x00000100
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKEN_GPHY0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_CLKEN_GPHY0_SET 0x00000100
|
|
+/** Set Clock Enable MDIO
|
|
+ Sets the clock enable bit of the MDIO domain. This domain contains the MDIO block. */
|
|
+#define SYS_ETH_CLKEN_MDIO 0x00000080
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKEN_MDIO_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_CLKEN_MDIO_SET 0x00000080
|
|
+/** Set Clock Enable GMAC3
|
|
+ Sets the clock enable bit of the GMAC3 domain. This domain contains the GMAC3 block. */
|
|
+#define SYS_ETH_CLKEN_GMAC3 0x00000008
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKEN_GMAC3_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_CLKEN_GMAC3_SET 0x00000008
|
|
+/** Set Clock Enable GMAC2
|
|
+ Sets the clock enable bit of the GMAC2 domain. This domain contains the GMAC2 block. */
|
|
+#define SYS_ETH_CLKEN_GMAC2 0x00000004
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKEN_GMAC2_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_CLKEN_GMAC2_SET 0x00000004
|
|
+/** Set Clock Enable GMAC1
|
|
+ Sets the clock enable bit of the GMAC1 domain. This domain contains the GMAC1 block. */
|
|
+#define SYS_ETH_CLKEN_GMAC1 0x00000002
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKEN_GMAC1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_CLKEN_GMAC1_SET 0x00000002
|
|
+/** Set Clock Enable GMAC0
|
|
+ Sets the clock enable bit of the GMAC0 domain. This domain contains the GMAC0 block. */
|
|
+#define SYS_ETH_CLKEN_GMAC0 0x00000001
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKEN_GMAC0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_CLKEN_GMAC0_SET 0x00000001
|
|
+
|
|
+/* Fields of "Clock Clear Register" */
|
|
+/** Clear Clock Enable GPHY1MII2
|
|
+ Clears the clock enable bit of the GPHY1MII2. */
|
|
+#define SYS_ETH_CLKCLR_GPHY1MII2 0x02000000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKCLR_GPHY1MII2_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_CLKCLR_GPHY1MII2_CLR 0x02000000
|
|
+/** Clear Clock Enable GPHY0MII2
|
|
+ Clears the clock enable bit of the GPHY0MII2. */
|
|
+#define SYS_ETH_CLKCLR_GPHY0MII2 0x01000000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKCLR_GPHY0MII2_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_CLKCLR_GPHY0MII2_CLR 0x01000000
|
|
+/** Clear Clock Enable PADCTRL2
|
|
+ Clears the clock enable bit of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
|
|
+#define SYS_ETH_CLKCLR_PADCTRL2 0x00200000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKCLR_PADCTRL2_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_CLKCLR_PADCTRL2_CLR 0x00200000
|
|
+/** Clear Clock Enable PADCTRL0
|
|
+ Clears the clock enable bit of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
|
|
+#define SYS_ETH_CLKCLR_PADCTRL0 0x00100000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKCLR_PADCTRL0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_CLKCLR_PADCTRL0_CLR 0x00100000
|
|
+/** Clear Clock Enable P2
|
|
+ Clears the clock enable bit of the P2 domain. This domain contains the P2 instance of the GPIO block. */
|
|
+#define SYS_ETH_CLKCLR_P2 0x00020000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKCLR_P2_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_CLKCLR_P2_CLR 0x00020000
|
|
+/** Clear Clock Enable P0
|
|
+ Clears the clock enable bit of the P0 domain. This domain contains the P0 instance of the GPIO block. */
|
|
+#define SYS_ETH_CLKCLR_P0 0x00010000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKCLR_P0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_CLKCLR_P0_CLR 0x00010000
|
|
+/** Clear Clock Enable xMII
|
|
+ Clears the clock enable bit of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
|
|
+#define SYS_ETH_CLKCLR_xMII 0x00000800
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKCLR_xMII_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_CLKCLR_xMII_CLR 0x00000800
|
|
+/** Clear Clock Enable SGMII
|
|
+ Clears the clock enable bit of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_CLKCLR_SGMII 0x00000400
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKCLR_SGMII_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_CLKCLR_SGMII_CLR 0x00000400
|
|
+/** Clear Clock Enable GPHY1
|
|
+ Clears the clock enable bit of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_CLKCLR_GPHY1 0x00000200
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKCLR_GPHY1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_CLKCLR_GPHY1_CLR 0x00000200
|
|
+/** Clear Clock Enable GPHY0
|
|
+ Clears the clock enable bit of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_CLKCLR_GPHY0 0x00000100
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKCLR_GPHY0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_CLKCLR_GPHY0_CLR 0x00000100
|
|
+/** Clear Clock Enable MDIO
|
|
+ Clears the clock enable bit of the MDIO domain. This domain contains the MDIO block. */
|
|
+#define SYS_ETH_CLKCLR_MDIO 0x00000080
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKCLR_MDIO_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_CLKCLR_MDIO_CLR 0x00000080
|
|
+/** Clear Clock Enable GMAC3
|
|
+ Clears the clock enable bit of the GMAC3 domain. This domain contains the GMAC3 block. */
|
|
+#define SYS_ETH_CLKCLR_GMAC3 0x00000008
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKCLR_GMAC3_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_CLKCLR_GMAC3_CLR 0x00000008
|
|
+/** Clear Clock Enable GMAC2
|
|
+ Clears the clock enable bit of the GMAC2 domain. This domain contains the GMAC2 block. */
|
|
+#define SYS_ETH_CLKCLR_GMAC2 0x00000004
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKCLR_GMAC2_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_CLKCLR_GMAC2_CLR 0x00000004
|
|
+/** Clear Clock Enable GMAC1
|
|
+ Clears the clock enable bit of the GMAC1 domain. This domain contains the GMAC1 block. */
|
|
+#define SYS_ETH_CLKCLR_GMAC1 0x00000002
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKCLR_GMAC1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_CLKCLR_GMAC1_CLR 0x00000002
|
|
+/** Clear Clock Enable GMAC0
|
|
+ Clears the clock enable bit of the GMAC0 domain. This domain contains the GMAC0 block. */
|
|
+#define SYS_ETH_CLKCLR_GMAC0 0x00000001
|
|
+/* No-Operation
|
|
+#define SYS_ETH_CLKCLR_GMAC0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_CLKCLR_GMAC0_CLR 0x00000001
|
|
+
|
|
+/* Fields of "Activation Status Register" */
|
|
+/** PADCTRL2 Status
|
|
+ Shows the activation status of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
|
|
+#define SYS_ETH_ACTS_PADCTRL2 0x00200000
|
|
+/* The block is inactive.
|
|
+#define SYS_ETH_ACTS_PADCTRL2_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_ETH_ACTS_PADCTRL2_ACT 0x00200000
|
|
+/** PADCTRL0 Status
|
|
+ Shows the activation status of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
|
|
+#define SYS_ETH_ACTS_PADCTRL0 0x00100000
|
|
+/* The block is inactive.
|
|
+#define SYS_ETH_ACTS_PADCTRL0_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_ETH_ACTS_PADCTRL0_ACT 0x00100000
|
|
+/** P2 Status
|
|
+ Shows the activation status of the P2 domain. This domain contains the P2 instance of the GPIO block. */
|
|
+#define SYS_ETH_ACTS_P2 0x00020000
|
|
+/* The block is inactive.
|
|
+#define SYS_ETH_ACTS_P2_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_ETH_ACTS_P2_ACT 0x00020000
|
|
+/** P0 Status
|
|
+ Shows the activation status of the P0 domain. This domain contains the P0 instance of the GPIO block. */
|
|
+#define SYS_ETH_ACTS_P0 0x00010000
|
|
+/* The block is inactive.
|
|
+#define SYS_ETH_ACTS_P0_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_ETH_ACTS_P0_ACT 0x00010000
|
|
+/** xMII Status
|
|
+ Shows the activation status of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
|
|
+#define SYS_ETH_ACTS_xMII 0x00000800
|
|
+/* The block is inactive.
|
|
+#define SYS_ETH_ACTS_xMII_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_ETH_ACTS_xMII_ACT 0x00000800
|
|
+/** SGMII Status
|
|
+ Shows the activation status of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_ACTS_SGMII 0x00000400
|
|
+/* The block is inactive.
|
|
+#define SYS_ETH_ACTS_SGMII_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_ETH_ACTS_SGMII_ACT 0x00000400
|
|
+/** GPHY1 Status
|
|
+ Shows the activation status of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_ACTS_GPHY1 0x00000200
|
|
+/* The block is inactive.
|
|
+#define SYS_ETH_ACTS_GPHY1_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_ETH_ACTS_GPHY1_ACT 0x00000200
|
|
+/** GPHY0 Status
|
|
+ Shows the activation status of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_ACTS_GPHY0 0x00000100
|
|
+/* The block is inactive.
|
|
+#define SYS_ETH_ACTS_GPHY0_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_ETH_ACTS_GPHY0_ACT 0x00000100
|
|
+/** MDIO Status
|
|
+ Shows the activation status of the MDIO domain. This domain contains the MDIO block. */
|
|
+#define SYS_ETH_ACTS_MDIO 0x00000080
|
|
+/* The block is inactive.
|
|
+#define SYS_ETH_ACTS_MDIO_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_ETH_ACTS_MDIO_ACT 0x00000080
|
|
+/** GMAC3 Status
|
|
+ Shows the activation status of the GMAC3 domain. This domain contains the GMAC3 block. */
|
|
+#define SYS_ETH_ACTS_GMAC3 0x00000008
|
|
+/* The block is inactive.
|
|
+#define SYS_ETH_ACTS_GMAC3_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_ETH_ACTS_GMAC3_ACT 0x00000008
|
|
+/** GMAC2 Status
|
|
+ Shows the activation status of the GMAC2 domain. This domain contains the GMAC2 block. */
|
|
+#define SYS_ETH_ACTS_GMAC2 0x00000004
|
|
+/* The block is inactive.
|
|
+#define SYS_ETH_ACTS_GMAC2_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_ETH_ACTS_GMAC2_ACT 0x00000004
|
|
+/** GMAC1 Status
|
|
+ Shows the activation status of the GMAC1 domain. This domain contains the GMAC1 block. */
|
|
+#define SYS_ETH_ACTS_GMAC1 0x00000002
|
|
+/* The block is inactive.
|
|
+#define SYS_ETH_ACTS_GMAC1_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_ETH_ACTS_GMAC1_ACT 0x00000002
|
|
+/** GMAC0 Status
|
|
+ Shows the activation status of the GMAC0 domain. This domain contains the GMAC0 block. */
|
|
+#define SYS_ETH_ACTS_GMAC0 0x00000001
|
|
+/* The block is inactive.
|
|
+#define SYS_ETH_ACTS_GMAC0_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_ETH_ACTS_GMAC0_ACT 0x00000001
|
|
+
|
|
+/* Fields of "Activation Register" */
|
|
+/** Activate PADCTRL2
|
|
+ Sets the activation flag of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
|
|
+#define SYS_ETH_ACT_PADCTRL2 0x00200000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_ACT_PADCTRL2_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_ACT_PADCTRL2_SET 0x00200000
|
|
+/** Activate PADCTRL0
|
|
+ Sets the activation flag of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
|
|
+#define SYS_ETH_ACT_PADCTRL0 0x00100000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_ACT_PADCTRL0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_ACT_PADCTRL0_SET 0x00100000
|
|
+/** Activate P2
|
|
+ Sets the activation flag of the P2 domain. This domain contains the P2 instance of the GPIO block. */
|
|
+#define SYS_ETH_ACT_P2 0x00020000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_ACT_P2_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_ACT_P2_SET 0x00020000
|
|
+/** Activate P0
|
|
+ Sets the activation flag of the P0 domain. This domain contains the P0 instance of the GPIO block. */
|
|
+#define SYS_ETH_ACT_P0 0x00010000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_ACT_P0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_ACT_P0_SET 0x00010000
|
|
+/** Activate xMII
|
|
+ Sets the activation flag of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
|
|
+#define SYS_ETH_ACT_xMII 0x00000800
|
|
+/* No-Operation
|
|
+#define SYS_ETH_ACT_xMII_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_ACT_xMII_SET 0x00000800
|
|
+/** Activate SGMII
|
|
+ Sets the activation flag of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_ACT_SGMII 0x00000400
|
|
+/* No-Operation
|
|
+#define SYS_ETH_ACT_SGMII_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_ACT_SGMII_SET 0x00000400
|
|
+/** Activate GPHY1
|
|
+ Sets the activation flag of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_ACT_GPHY1 0x00000200
|
|
+/* No-Operation
|
|
+#define SYS_ETH_ACT_GPHY1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_ACT_GPHY1_SET 0x00000200
|
|
+/** Activate GPHY0
|
|
+ Sets the activation flag of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_ACT_GPHY0 0x00000100
|
|
+/* No-Operation
|
|
+#define SYS_ETH_ACT_GPHY0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_ACT_GPHY0_SET 0x00000100
|
|
+/** Activate MDIO
|
|
+ Sets the activation flag of the MDIO domain. This domain contains the MDIO block. */
|
|
+#define SYS_ETH_ACT_MDIO 0x00000080
|
|
+/* No-Operation
|
|
+#define SYS_ETH_ACT_MDIO_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_ACT_MDIO_SET 0x00000080
|
|
+/** Activate GMAC3
|
|
+ Sets the activation flag of the GMAC3 domain. This domain contains the GMAC3 block. */
|
|
+#define SYS_ETH_ACT_GMAC3 0x00000008
|
|
+/* No-Operation
|
|
+#define SYS_ETH_ACT_GMAC3_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_ACT_GMAC3_SET 0x00000008
|
|
+/** Activate GMAC2
|
|
+ Sets the activation flag of the GMAC2 domain. This domain contains the GMAC2 block. */
|
|
+#define SYS_ETH_ACT_GMAC2 0x00000004
|
|
+/* No-Operation
|
|
+#define SYS_ETH_ACT_GMAC2_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_ACT_GMAC2_SET 0x00000004
|
|
+/** Activate GMAC1
|
|
+ Sets the activation flag of the GMAC1 domain. This domain contains the GMAC1 block. */
|
|
+#define SYS_ETH_ACT_GMAC1 0x00000002
|
|
+/* No-Operation
|
|
+#define SYS_ETH_ACT_GMAC1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_ACT_GMAC1_SET 0x00000002
|
|
+/** Activate GMAC0
|
|
+ Sets the activation flag of the GMAC0 domain. This domain contains the GMAC0 block. */
|
|
+#define SYS_ETH_ACT_GMAC0 0x00000001
|
|
+/* No-Operation
|
|
+#define SYS_ETH_ACT_GMAC0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_ETH_ACT_GMAC0_SET 0x00000001
|
|
+
|
|
+/* Fields of "Deactivation Register" */
|
|
+/** Deactivate PADCTRL2
|
|
+ Clears the activation flag of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
|
|
+#define SYS_ETH_DEACT_PADCTRL2 0x00200000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_DEACT_PADCTRL2_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_DEACT_PADCTRL2_CLR 0x00200000
|
|
+/** Deactivate PADCTRL0
|
|
+ Clears the activation flag of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
|
|
+#define SYS_ETH_DEACT_PADCTRL0 0x00100000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_DEACT_PADCTRL0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_DEACT_PADCTRL0_CLR 0x00100000
|
|
+/** Deactivate P2
|
|
+ Clears the activation flag of the P2 domain. This domain contains the P2 instance of the GPIO block. */
|
|
+#define SYS_ETH_DEACT_P2 0x00020000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_DEACT_P2_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_DEACT_P2_CLR 0x00020000
|
|
+/** Deactivate P0
|
|
+ Clears the activation flag of the P0 domain. This domain contains the P0 instance of the GPIO block. */
|
|
+#define SYS_ETH_DEACT_P0 0x00010000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_DEACT_P0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_DEACT_P0_CLR 0x00010000
|
|
+/** Deactivate xMII
|
|
+ Clears the activation flag of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
|
|
+#define SYS_ETH_DEACT_xMII 0x00000800
|
|
+/* No-Operation
|
|
+#define SYS_ETH_DEACT_xMII_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_DEACT_xMII_CLR 0x00000800
|
|
+/** Deactivate SGMII
|
|
+ Clears the activation flag of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_DEACT_SGMII 0x00000400
|
|
+/* No-Operation
|
|
+#define SYS_ETH_DEACT_SGMII_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_DEACT_SGMII_CLR 0x00000400
|
|
+/** Deactivate GPHY1
|
|
+ Clears the activation flag of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_DEACT_GPHY1 0x00000200
|
|
+/* No-Operation
|
|
+#define SYS_ETH_DEACT_GPHY1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_DEACT_GPHY1_CLR 0x00000200
|
|
+/** Deactivate GPHY0
|
|
+ Clears the activation flag of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_DEACT_GPHY0 0x00000100
|
|
+/* No-Operation
|
|
+#define SYS_ETH_DEACT_GPHY0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_DEACT_GPHY0_CLR 0x00000100
|
|
+/** Deactivate MDIO
|
|
+ Clears the activation flag of the MDIO domain. This domain contains the MDIO block. */
|
|
+#define SYS_ETH_DEACT_MDIO 0x00000080
|
|
+/* No-Operation
|
|
+#define SYS_ETH_DEACT_MDIO_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_DEACT_MDIO_CLR 0x00000080
|
|
+/** Deactivate GMAC3
|
|
+ Clears the activation flag of the GMAC3 domain. This domain contains the GMAC3 block. */
|
|
+#define SYS_ETH_DEACT_GMAC3 0x00000008
|
|
+/* No-Operation
|
|
+#define SYS_ETH_DEACT_GMAC3_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_DEACT_GMAC3_CLR 0x00000008
|
|
+/** Deactivate GMAC2
|
|
+ Clears the activation flag of the GMAC2 domain. This domain contains the GMAC2 block. */
|
|
+#define SYS_ETH_DEACT_GMAC2 0x00000004
|
|
+/* No-Operation
|
|
+#define SYS_ETH_DEACT_GMAC2_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_DEACT_GMAC2_CLR 0x00000004
|
|
+/** Deactivate GMAC1
|
|
+ Clears the activation flag of the GMAC1 domain. This domain contains the GMAC1 block. */
|
|
+#define SYS_ETH_DEACT_GMAC1 0x00000002
|
|
+/* No-Operation
|
|
+#define SYS_ETH_DEACT_GMAC1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_DEACT_GMAC1_CLR 0x00000002
|
|
+/** Deactivate GMAC0
|
|
+ Clears the activation flag of the GMAC0 domain. This domain contains the GMAC0 block. */
|
|
+#define SYS_ETH_DEACT_GMAC0 0x00000001
|
|
+/* No-Operation
|
|
+#define SYS_ETH_DEACT_GMAC0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_ETH_DEACT_GMAC0_CLR 0x00000001
|
|
+
|
|
+/* Fields of "Reboot Trigger Register" */
|
|
+/** Reboot PADCTRL2
|
|
+ Triggers a reboot of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */
|
|
+#define SYS_ETH_RBT_PADCTRL2 0x00200000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_RBT_PADCTRL2_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_ETH_RBT_PADCTRL2_TRIG 0x00200000
|
|
+/** Reboot PADCTRL0
|
|
+ Triggers a reboot of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */
|
|
+#define SYS_ETH_RBT_PADCTRL0 0x00100000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_RBT_PADCTRL0_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_ETH_RBT_PADCTRL0_TRIG 0x00100000
|
|
+/** Reboot P2
|
|
+ Triggers a reboot of the P2 domain. This domain contains the P2 instance of the GPIO block. */
|
|
+#define SYS_ETH_RBT_P2 0x00020000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_RBT_P2_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_ETH_RBT_P2_TRIG 0x00020000
|
|
+/** Reboot P0
|
|
+ Triggers a reboot of the P0 domain. This domain contains the P0 instance of the GPIO block. */
|
|
+#define SYS_ETH_RBT_P0 0x00010000
|
|
+/* No-Operation
|
|
+#define SYS_ETH_RBT_P0_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_ETH_RBT_P0_TRIG 0x00010000
|
|
+/** Reboot xMII
|
|
+ Triggers a reboot of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */
|
|
+#define SYS_ETH_RBT_xMII 0x00000800
|
|
+/* No-Operation
|
|
+#define SYS_ETH_RBT_xMII_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_ETH_RBT_xMII_TRIG 0x00000800
|
|
+/** Reboot SGMII
|
|
+ Triggers a reboot of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_RBT_SGMII 0x00000400
|
|
+/* No-Operation
|
|
+#define SYS_ETH_RBT_SGMII_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_ETH_RBT_SGMII_TRIG 0x00000400
|
|
+/** Reboot GPHY1
|
|
+ Triggers a reboot of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_RBT_GPHY1 0x00000200
|
|
+/* No-Operation
|
|
+#define SYS_ETH_RBT_GPHY1_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_ETH_RBT_GPHY1_TRIG 0x00000200
|
|
+/** Reboot GPHY0
|
|
+ Triggers a reboot of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */
|
|
+#define SYS_ETH_RBT_GPHY0 0x00000100
|
|
+/* No-Operation
|
|
+#define SYS_ETH_RBT_GPHY0_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_ETH_RBT_GPHY0_TRIG 0x00000100
|
|
+/** Reboot MDIO
|
|
+ Triggers a reboot of the MDIO domain. This domain contains the MDIO block. */
|
|
+#define SYS_ETH_RBT_MDIO 0x00000080
|
|
+/* No-Operation
|
|
+#define SYS_ETH_RBT_MDIO_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_ETH_RBT_MDIO_TRIG 0x00000080
|
|
+/** Reboot GMAC3
|
|
+ Triggers a reboot of the GMAC3 domain. This domain contains the GMAC3 block. */
|
|
+#define SYS_ETH_RBT_GMAC3 0x00000008
|
|
+/* No-Operation
|
|
+#define SYS_ETH_RBT_GMAC3_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_ETH_RBT_GMAC3_TRIG 0x00000008
|
|
+/** Reboot GMAC2
|
|
+ Triggers a reboot of the GMAC2 domain. This domain contains the GMAC2 block. */
|
|
+#define SYS_ETH_RBT_GMAC2 0x00000004
|
|
+/* No-Operation
|
|
+#define SYS_ETH_RBT_GMAC2_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_ETH_RBT_GMAC2_TRIG 0x00000004
|
|
+/** Reboot GMAC1
|
|
+ Triggers a reboot of the GMAC1 domain. This domain contains the GMAC1 block. */
|
|
+#define SYS_ETH_RBT_GMAC1 0x00000002
|
|
+/* No-Operation
|
|
+#define SYS_ETH_RBT_GMAC1_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_ETH_RBT_GMAC1_TRIG 0x00000002
|
|
+/** Reboot GMAC0
|
|
+ Triggers a reboot of the GMAC0 domain. This domain contains the GMAC0 block. */
|
|
+#define SYS_ETH_RBT_GMAC0 0x00000001
|
|
+/* No-Operation
|
|
+#define SYS_ETH_RBT_GMAC0_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_ETH_RBT_GMAC0_TRIG 0x00000001
|
|
+
|
|
+/* Fields of "External PHY Control Register" */
|
|
+/** PHY_CLKO Output Enable
|
|
+ Enables the output driver of the PHY_CLKO pin. */
|
|
+#define SYS_ETH_EXTPHYC_CLKEN 0x80000000
|
|
+/* Disable
|
|
+#define SYS_ETH_EXTPHYC_CLKEN_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_EXTPHYC_CLKEN_EN 0x80000000
|
|
+/** PHY_CLKO Frequency Select
|
|
+ Selects the frequency of the PHY_CLKO pin. */
|
|
+#define SYS_ETH_EXTPHYC_CLKSEL_MASK 0x00000007
|
|
+/** field offset */
|
|
+#define SYS_ETH_EXTPHYC_CLKSEL_OFFSET 0
|
|
+/** 25 MHz. */
|
|
+#define SYS_ETH_EXTPHYC_CLKSEL_F25 0x00000001
|
|
+/** 125 MHz. */
|
|
+#define SYS_ETH_EXTPHYC_CLKSEL_F125 0x00000002
|
|
+/** 50 MHz. */
|
|
+#define SYS_ETH_EXTPHYC_CLKSEL_F50 0x00000005
|
|
+
|
|
+/* Fields of "Power Down Configuration Register" */
|
|
+/** Enable Power Down PADCTRL2
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_ETH_PDCFG_PADCTRL2 0x00200000
|
|
+/* Disable
|
|
+#define SYS_ETH_PDCFG_PADCTRL2_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_PDCFG_PADCTRL2_EN 0x00200000
|
|
+/** Enable Power Down PADCTRL0
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_ETH_PDCFG_PADCTRL0 0x00100000
|
|
+/* Disable
|
|
+#define SYS_ETH_PDCFG_PADCTRL0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_PDCFG_PADCTRL0_EN 0x00100000
|
|
+/** Enable Power Down P2
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_ETH_PDCFG_P2 0x00020000
|
|
+/* Disable
|
|
+#define SYS_ETH_PDCFG_P2_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_PDCFG_P2_EN 0x00020000
|
|
+/** Enable Power Down P0
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_ETH_PDCFG_P0 0x00010000
|
|
+/* Disable
|
|
+#define SYS_ETH_PDCFG_P0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_PDCFG_P0_EN 0x00010000
|
|
+/** Enable Power Down xMII
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_ETH_PDCFG_xMII 0x00000800
|
|
+/* Disable
|
|
+#define SYS_ETH_PDCFG_xMII_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_PDCFG_xMII_EN 0x00000800
|
|
+/** Enable Power Down SGMII
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_ETH_PDCFG_SGMII 0x00000400
|
|
+/* Disable
|
|
+#define SYS_ETH_PDCFG_SGMII_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_PDCFG_SGMII_EN 0x00000400
|
|
+/** Enable Power Down GPHY1
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_ETH_PDCFG_GPHY1 0x00000200
|
|
+/* Disable
|
|
+#define SYS_ETH_PDCFG_GPHY1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_PDCFG_GPHY1_EN 0x00000200
|
|
+/** Enable Power Down GPHY0
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_ETH_PDCFG_GPHY0 0x00000100
|
|
+/* Disable
|
|
+#define SYS_ETH_PDCFG_GPHY0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_PDCFG_GPHY0_EN 0x00000100
|
|
+/** Enable Power Down MDIO
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_ETH_PDCFG_MDIO 0x00000080
|
|
+/* Disable
|
|
+#define SYS_ETH_PDCFG_MDIO_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_PDCFG_MDIO_EN 0x00000080
|
|
+/** Enable Power Down GMAC3
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_ETH_PDCFG_GMAC3 0x00000008
|
|
+/* Disable
|
|
+#define SYS_ETH_PDCFG_GMAC3_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_PDCFG_GMAC3_EN 0x00000008
|
|
+/** Enable Power Down GMAC2
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_ETH_PDCFG_GMAC2 0x00000004
|
|
+/* Disable
|
|
+#define SYS_ETH_PDCFG_GMAC2_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_PDCFG_GMAC2_EN 0x00000004
|
|
+/** Enable Power Down GMAC1
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_ETH_PDCFG_GMAC1 0x00000002
|
|
+/* Disable
|
|
+#define SYS_ETH_PDCFG_GMAC1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_PDCFG_GMAC1_EN 0x00000002
|
|
+/** Enable Power Down GMAC0
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_ETH_PDCFG_GMAC0 0x00000001
|
|
+/* Disable
|
|
+#define SYS_ETH_PDCFG_GMAC0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_ETH_PDCFG_GMAC0_EN 0x00000001
|
|
+
|
|
+/* Fields of "Datarate Control Register" */
|
|
+/** MDC Clockrate
|
|
+ Selects the clockrate of the MDIO interface. */
|
|
+#define SYS_ETH_DRC_MDC_MASK 0x30000000
|
|
+/** field offset */
|
|
+#define SYS_ETH_DRC_MDC_OFFSET 28
|
|
+/** 312.5/128 = appr. 2.44 MHz. */
|
|
+#define SYS_ETH_DRC_MDC_F2M44 0x00000000
|
|
+/** 312.5/64 = appr. 4.88 MHz. */
|
|
+#define SYS_ETH_DRC_MDC_F4M88 0x10000000
|
|
+/** 312.5/32 = appr. 9.77 MHz. */
|
|
+#define SYS_ETH_DRC_MDC_F9M77 0x20000000
|
|
+/** 312.5/16 = appr. 19.5 MHz. */
|
|
+#define SYS_ETH_DRC_MDC_F19M5 0x30000000
|
|
+/** xMII1 Datarate
|
|
+ Selects the datarate of the xMII1 interface. */
|
|
+#define SYS_ETH_DRC_xMII1_MASK 0x07000000
|
|
+/** field offset */
|
|
+#define SYS_ETH_DRC_xMII1_OFFSET 24
|
|
+/** 10 MBit/s. */
|
|
+#define SYS_ETH_DRC_xMII1_DR10 0x00000000
|
|
+/** 100 MBit/s. */
|
|
+#define SYS_ETH_DRC_xMII1_DR100 0x01000000
|
|
+/** 1000 MBit/s. */
|
|
+#define SYS_ETH_DRC_xMII1_DR1000 0x02000000
|
|
+/** 200 MBit/s. */
|
|
+#define SYS_ETH_DRC_xMII1_DR200 0x05000000
|
|
+/** xMII0 Datarate
|
|
+ Selects the datarate of the xMII0 interface. */
|
|
+#define SYS_ETH_DRC_xMII0_MASK 0x00700000
|
|
+/** field offset */
|
|
+#define SYS_ETH_DRC_xMII0_OFFSET 20
|
|
+/** 10 MBit/s. */
|
|
+#define SYS_ETH_DRC_xMII0_DR10 0x00000000
|
|
+/** 100 MBit/s. */
|
|
+#define SYS_ETH_DRC_xMII0_DR100 0x00100000
|
|
+/** 1000 MBit/s. */
|
|
+#define SYS_ETH_DRC_xMII0_DR1000 0x00200000
|
|
+/** 200 MBit/s. */
|
|
+#define SYS_ETH_DRC_xMII0_DR200 0x00500000
|
|
+/** SGMII Datarate
|
|
+ Selects the datarate of the SGMII interface. */
|
|
+#define SYS_ETH_DRC_SGMII_MASK 0x00070000
|
|
+/** field offset */
|
|
+#define SYS_ETH_DRC_SGMII_OFFSET 16
|
|
+/** 10 MBit/s. */
|
|
+#define SYS_ETH_DRC_SGMII_DR10 0x00000000
|
|
+/** 100 MBit/s. */
|
|
+#define SYS_ETH_DRC_SGMII_DR100 0x00010000
|
|
+/** 1000 MBit/s. */
|
|
+#define SYS_ETH_DRC_SGMII_DR1000 0x00020000
|
|
+/** 2500 MBit/s. */
|
|
+#define SYS_ETH_DRC_SGMII_DR2500 0x00040000
|
|
+/** GPHY1_MII2 Datarate
|
|
+ Shows the datarate of the GPHY1_MII2 interface. */
|
|
+#define SYS_ETH_DRC_GPHY1_MII2_MASK 0x00007000
|
|
+/** field offset */
|
|
+#define SYS_ETH_DRC_GPHY1_MII2_OFFSET 12
|
|
+/** 10 MBit/s. */
|
|
+#define SYS_ETH_DRC_GPHY1_MII2_DR10 0x00000000
|
|
+/** 100 MBit/s. */
|
|
+#define SYS_ETH_DRC_GPHY1_MII2_DR100 0x00001000
|
|
+/** GPHY1_GMII Datarate
|
|
+ Shows the datarate of the GPHY1_GMII interface. */
|
|
+#define SYS_ETH_DRC_GPHY1_GMII_MASK 0x00000700
|
|
+/** field offset */
|
|
+#define SYS_ETH_DRC_GPHY1_GMII_OFFSET 8
|
|
+/** 10 MBit/s. */
|
|
+#define SYS_ETH_DRC_GPHY1_GMII_DR10 0x00000000
|
|
+/** 100 MBit/s. */
|
|
+#define SYS_ETH_DRC_GPHY1_GMII_DR100 0x00000100
|
|
+/** 1000 MBit/s. */
|
|
+#define SYS_ETH_DRC_GPHY1_GMII_DR1000 0x00000200
|
|
+/** GPHY0_MII2 Datarate
|
|
+ Shows the datarate of the GPHY0_MII2 interface. */
|
|
+#define SYS_ETH_DRC_GPHY0_MII2_MASK 0x00000070
|
|
+/** field offset */
|
|
+#define SYS_ETH_DRC_GPHY0_MII2_OFFSET 4
|
|
+/** 10 MBit/s. */
|
|
+#define SYS_ETH_DRC_GPHY0_MII2_DR10 0x00000000
|
|
+/** 100 MBit/s. */
|
|
+#define SYS_ETH_DRC_GPHY0_MII2_DR100 0x00000010
|
|
+/** GPHY0_GMII Datarate
|
|
+ Shows the datarate of the GPHY0_GMII interface. */
|
|
+#define SYS_ETH_DRC_GPHY0_GMII_MASK 0x00000007
|
|
+/** field offset */
|
|
+#define SYS_ETH_DRC_GPHY0_GMII_OFFSET 0
|
|
+/** 10 MBit/s. */
|
|
+#define SYS_ETH_DRC_GPHY0_GMII_DR10 0x00000000
|
|
+/** 100 MBit/s. */
|
|
+#define SYS_ETH_DRC_GPHY0_GMII_DR100 0x00000001
|
|
+/** 1000 MBit/s. */
|
|
+#define SYS_ETH_DRC_GPHY0_GMII_DR1000 0x00000002
|
|
+
|
|
+/* Fields of "GMAC Multiplexer Control Register" */
|
|
+/** GMAC 3 MUX setting
|
|
+ Selects the physical layer to be connected to GMAC3 */
|
|
+#define SYS_ETH_GMUXC_GMAC3_MASK 0x00007000
|
|
+/** field offset */
|
|
+#define SYS_ETH_GMUXC_GMAC3_OFFSET 12
|
|
+/** GMAC connects to GPHY0_GMII interface */
|
|
+#define SYS_ETH_GMUXC_GMAC3_GPHY0_GMII 0x00000000
|
|
+/** GMAC connects to GPHY0_MII2 interface */
|
|
+#define SYS_ETH_GMUXC_GMAC3_GPHY0_MII2 0x00001000
|
|
+/** GMAC connects to GPHY1_GMII interface */
|
|
+#define SYS_ETH_GMUXC_GMAC3_GPHY1_GMII 0x00002000
|
|
+/** GMAC connects to GPHY1_MII2 interface */
|
|
+#define SYS_ETH_GMUXC_GMAC3_GPHY1_MII2 0x00003000
|
|
+/** GMAC connects to SGMII interface */
|
|
+#define SYS_ETH_GMUXC_GMAC3_SGMII 0x00004000
|
|
+/** GMAC connects to xMII0 interface */
|
|
+#define SYS_ETH_GMUXC_GMAC3_xMII0 0x00005000
|
|
+/** GMAC connects to xMII1 interface */
|
|
+#define SYS_ETH_GMUXC_GMAC3_xMII1 0x00006000
|
|
+/** GMAC 2 MUX setting
|
|
+ Selects the physical layer to be connected to GMAC2 */
|
|
+#define SYS_ETH_GMUXC_GMAC2_MASK 0x00000700
|
|
+/** field offset */
|
|
+#define SYS_ETH_GMUXC_GMAC2_OFFSET 8
|
|
+/** GMAC connects to GPHY0_GMII interface */
|
|
+#define SYS_ETH_GMUXC_GMAC2_GPHY0_GMII 0x00000000
|
|
+/** GMAC connects to GPHY0_MII2 interface */
|
|
+#define SYS_ETH_GMUXC_GMAC2_GPHY0_MII2 0x00000100
|
|
+/** GMAC connects to GPHY1_GMII interface */
|
|
+#define SYS_ETH_GMUXC_GMAC2_GPHY1_GMII 0x00000200
|
|
+/** GMAC connects to GPHY1_MII2 interface */
|
|
+#define SYS_ETH_GMUXC_GMAC2_GPHY1_MII2 0x00000300
|
|
+/** GMAC connects to SGMII interface */
|
|
+#define SYS_ETH_GMUXC_GMAC2_SGMII 0x00000400
|
|
+/** GMAC connects to xMII0 interface */
|
|
+#define SYS_ETH_GMUXC_GMAC2_xMII0 0x00000500
|
|
+/** GMAC connects to xMII1 interface */
|
|
+#define SYS_ETH_GMUXC_GMAC2_xMII1 0x00000600
|
|
+/** GMAC 1 MUX setting
|
|
+ Selects the physical layer to be connected to GMAC1 */
|
|
+#define SYS_ETH_GMUXC_GMAC1_MASK 0x00000070
|
|
+/** field offset */
|
|
+#define SYS_ETH_GMUXC_GMAC1_OFFSET 4
|
|
+/** GMAC connects to GPHY0_GMII interface */
|
|
+#define SYS_ETH_GMUXC_GMAC1_GPHY0_GMII 0x00000000
|
|
+/** GMAC connects to GPHY0_MII2 interface */
|
|
+#define SYS_ETH_GMUXC_GMAC1_GPHY0_MII2 0x00000010
|
|
+/** GMAC connects to GPHY1_GMII interface */
|
|
+#define SYS_ETH_GMUXC_GMAC1_GPHY1_GMII 0x00000020
|
|
+/** GMAC connects to GPHY1_MII2 interface */
|
|
+#define SYS_ETH_GMUXC_GMAC1_GPHY1_MII2 0x00000030
|
|
+/** GMAC connects to SGMII interface */
|
|
+#define SYS_ETH_GMUXC_GMAC1_SGMII 0x00000040
|
|
+/** GMAC connects to xMII0 interface */
|
|
+#define SYS_ETH_GMUXC_GMAC1_xMII0 0x00000050
|
|
+/** GMAC connects to xMII1 interface */
|
|
+#define SYS_ETH_GMUXC_GMAC1_xMII1 0x00000060
|
|
+/** GMAC 0 MUX setting
|
|
+ Selects the physical layer to be connected to GMAC0 */
|
|
+#define SYS_ETH_GMUXC_GMAC0_MASK 0x00000007
|
|
+/** field offset */
|
|
+#define SYS_ETH_GMUXC_GMAC0_OFFSET 0
|
|
+/** GMAC connects to GPHY0_GMII interface */
|
|
+#define SYS_ETH_GMUXC_GMAC0_GPHY0_GMII 0x00000000
|
|
+/** GMAC connects to GPHY0_MII2 interface */
|
|
+#define SYS_ETH_GMUXC_GMAC0_GPHY0_MII2 0x00000001
|
|
+/** GMAC connects to GPHY1_GMII interface */
|
|
+#define SYS_ETH_GMUXC_GMAC0_GPHY1_GMII 0x00000002
|
|
+/** GMAC connects to GPHY1_MII2 interface */
|
|
+#define SYS_ETH_GMUXC_GMAC0_GPHY1_MII2 0x00000003
|
|
+/** GMAC connects to SGMII interface */
|
|
+#define SYS_ETH_GMUXC_GMAC0_SGMII 0x00000004
|
|
+/** GMAC connects to xMII0 interface */
|
|
+#define SYS_ETH_GMUXC_GMAC0_xMII0 0x00000005
|
|
+/** GMAC connects to xMII1 interface */
|
|
+#define SYS_ETH_GMUXC_GMAC0_xMII1 0x00000006
|
|
+
|
|
+/* Fields of "Datarate Status Register" */
|
|
+/** GMAC 3 datarate
|
|
+ Shows the datarate of GMAC3 */
|
|
+#define SYS_ETH_DRS_GMAC3_MASK 0x00007000
|
|
+/** field offset */
|
|
+#define SYS_ETH_DRS_GMAC3_OFFSET 12
|
|
+/** 10 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC3_DR10 0x00000000
|
|
+/** 100 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC3_DR100 0x00001000
|
|
+/** 1000 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC3_DR1000 0x00002000
|
|
+/** 2500 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC3_DR2500 0x00004000
|
|
+/** 200 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC3_DR200 0x00005000
|
|
+/** GMAC 2 datarate
|
|
+ Shows the datarate of GMAC2 */
|
|
+#define SYS_ETH_DRS_GMAC2_MASK 0x00000700
|
|
+/** field offset */
|
|
+#define SYS_ETH_DRS_GMAC2_OFFSET 8
|
|
+/** 10 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC2_DR10 0x00000000
|
|
+/** 100 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC2_DR100 0x00000100
|
|
+/** 1000 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC2_DR1000 0x00000200
|
|
+/** 2500 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC2_DR2500 0x00000400
|
|
+/** 200 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC2_DR200 0x00000500
|
|
+/** GMAC 1 datarate
|
|
+ Shows the datarate of GMAC1 */
|
|
+#define SYS_ETH_DRS_GMAC1_MASK 0x00000070
|
|
+/** field offset */
|
|
+#define SYS_ETH_DRS_GMAC1_OFFSET 4
|
|
+/** 10 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC1_DR10 0x00000000
|
|
+/** 100 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC1_DR100 0x00000010
|
|
+/** 1000 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC1_DR1000 0x00000020
|
|
+/** 2500 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC1_DR2500 0x00000040
|
|
+/** 200 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC1_DR200 0x00000050
|
|
+/** GMAC 0 datarate
|
|
+ Shows the datarate of GMAC0 */
|
|
+#define SYS_ETH_DRS_GMAC0_MASK 0x00000007
|
|
+/** field offset */
|
|
+#define SYS_ETH_DRS_GMAC0_OFFSET 0
|
|
+/** 10 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC0_DR10 0x00000000
|
|
+/** 100 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC0_DR100 0x00000001
|
|
+/** 1000 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC0_DR1000 0x00000002
|
|
+/** 2500 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC0_DR2500 0x00000004
|
|
+/** 200 MBit/s. */
|
|
+#define SYS_ETH_DRS_GMAC0_DR200 0x00000005
|
|
+
|
|
+/* Fields of "SGMII Control Register" */
|
|
+/** Auto Negotiation Protocol
|
|
+ Selects the TBX/SGMII mode for the autonegotiation of the SGMII interface. */
|
|
+#define SYS_ETH_SGMIIC_ANP 0x00000002
|
|
+/* TBX Mode (IEEE 802.3 Clause 37 ANEG)
|
|
+#define SYS_ETH_SGMIIC_ANP_TBXM 0x00000000 */
|
|
+/** SGMII Mode (Cisco Aneg) */
|
|
+#define SYS_ETH_SGMIIC_ANP_SGMIIM 0x00000002
|
|
+/** Auto Negotiation MAC/PHY
|
|
+ Selects the MAC/PHY mode for the autonegotiation of the SGMII interface. */
|
|
+#define SYS_ETH_SGMIIC_ANMP 0x00000001
|
|
+/* MAC Mode
|
|
+#define SYS_ETH_SGMIIC_ANMP_MAC 0x00000000 */
|
|
+/** PHY Mode */
|
|
+#define SYS_ETH_SGMIIC_ANMP_PHY 0x00000001
|
|
+
|
|
+/*! @} */ /* SYS_ETH_REGISTER */
|
|
+
|
|
+#endif /* _sys_eth_reg_h */
|
|
--- /dev/null
|
|
+++ b/arch/mips/include/asm/mach-lantiq/falcon/sys_gpe_reg.h
|
|
@@ -0,0 +1,2829 @@
|
|
+/******************************************************************************
|
|
+
|
|
+ Copyright (c) 2010
|
|
+ Lantiq Deutschland GmbH
|
|
+
|
|
+ For licensing information, see the file 'LICENSE' in the root folder of
|
|
+ this software module.
|
|
+
|
|
+******************************************************************************/
|
|
+
|
|
+#ifndef _sys_gpe_reg_h
|
|
+#define _sys_gpe_reg_h
|
|
+
|
|
+/** \addtogroup SYS_GPE_REGISTER
|
|
+ @{
|
|
+*/
|
|
+/* access macros */
|
|
+#define sys_gpe_r32(reg) reg_r32(&sys_gpe->reg)
|
|
+#define sys_gpe_w32(val, reg) reg_w32(val, &sys_gpe->reg)
|
|
+#define sys_gpe_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys_gpe->reg)
|
|
+#define sys_gpe_r32_table(reg, idx) reg_r32_table(sys_gpe->reg, idx)
|
|
+#define sys_gpe_w32_table(val, reg, idx) reg_w32_table(val, sys_gpe->reg, idx)
|
|
+#define sys_gpe_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys_gpe->reg, idx)
|
|
+#define sys_gpe_adr_table(reg, idx) adr_table(sys_gpe->reg, idx)
|
|
+
|
|
+
|
|
+/** SYS_GPE register structure */
|
|
+struct gpon_reg_sys_gpe
|
|
+{
|
|
+ /** Clock Status Register
|
|
+ The clock status reflects the actual clocking mode as a function of the SW settings and the hardware sleep mode. */
|
|
+ unsigned int clks; /* 0x00000000 */
|
|
+ /** Clock Enable Register
|
|
+ Via this register the clocks for the domains can be enabled. */
|
|
+ unsigned int clken; /* 0x00000004 */
|
|
+ /** Clock Clear Register
|
|
+ Via this register the clocks for the domains can be disabled. */
|
|
+ unsigned int clkclr; /* 0x00000008 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_0[5]; /* 0x0000000C */
|
|
+ /** Activation Status Register */
|
|
+ unsigned int acts; /* 0x00000020 */
|
|
+ /** Activation Register
|
|
+ Via this register the domains can be activated. */
|
|
+ unsigned int act; /* 0x00000024 */
|
|
+ /** Deactivation Register
|
|
+ Via this register the domains can be deactivated. */
|
|
+ unsigned int deact; /* 0x00000028 */
|
|
+ /** Reboot Trigger Register
|
|
+ Via this register the domains can be rebooted (sent through reset). */
|
|
+ unsigned int rbt; /* 0x0000002C */
|
|
+ /** Reserved */
|
|
+ unsigned int res_1[33]; /* 0x00000030 */
|
|
+ /** Power Down Configuration Register
|
|
+ Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be removed. */
|
|
+ unsigned int pdcfg; /* 0x000000B4 */
|
|
+ /** Sleep Source Configuration Register
|
|
+ All sleep/wakeup conditions selected in this register contribute to the generation of the hardware sleep/wakeup request. Unselected conditions are ignored for sleep and wakeup. If no bit is selected, HW sleep is disabled. */
|
|
+ unsigned int sscfg; /* 0x000000B8 */
|
|
+ /** Sleep Source Timer Register */
|
|
+ unsigned int sst; /* 0x000000BC */
|
|
+ /** Sleep Destination Status Register
|
|
+ Shows the status of the sleep destination vector. All clock domains selected in this register will be shutoff in case of a hardware sleep request. These clocks will be automatically reenabled in case of a hardware wakeup request. */
|
|
+ unsigned int sds; /* 0x000000C0 */
|
|
+ /** Sleep Destination Set Register
|
|
+ Via this register the the domains to be shutoff in case of a hardware sleep request can be selected. */
|
|
+ unsigned int sdset; /* 0x000000C4 */
|
|
+ /** Sleep Destination Clear Register
|
|
+ Via this register the the domains to be shutoff in case of a hardware sleep request can be deselected. */
|
|
+ unsigned int sdclr; /* 0x000000C8 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_2[9]; /* 0x000000CC */
|
|
+ /** IRNCS Capture Register
|
|
+ This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNCSEN register. The interrupts can be acknowledged by a write operation. */
|
|
+ unsigned int irncscr; /* 0x000000F0 */
|
|
+ /** IRNCS Interrupt Control Register
|
|
+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */
|
|
+ unsigned int irncsicr; /* 0x000000F4 */
|
|
+ /** IRNCS Interrupt Enable Register
|
|
+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCSCR register and are not signalled via the interrupt line towards the controller. */
|
|
+ unsigned int irncsen; /* 0x000000F8 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_3; /* 0x000000FC */
|
|
+};
|
|
+
|
|
+
|
|
+/* Fields of "Clock Status Register" */
|
|
+/** COP7 Clock Enable
|
|
+ Shows the clock enable bit for the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
|
|
+#define SYS_GPE_CLKS_COP7 0x80000000
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_COP7_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_COP7_EN 0x80000000
|
|
+/** COP6 Clock Enable
|
|
+ Shows the clock enable bit for the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
|
|
+#define SYS_GPE_CLKS_COP6 0x40000000
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_COP6_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_COP6_EN 0x40000000
|
|
+/** COP5 Clock Enable
|
|
+ Shows the clock enable bit for the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
|
|
+#define SYS_GPE_CLKS_COP5 0x20000000
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_COP5_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_COP5_EN 0x20000000
|
|
+/** COP4 Clock Enable
|
|
+ Shows the clock enable bit for the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
|
|
+#define SYS_GPE_CLKS_COP4 0x10000000
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_COP4_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_COP4_EN 0x10000000
|
|
+/** COP3 Clock Enable
|
|
+ Shows the clock enable bit for the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
|
|
+#define SYS_GPE_CLKS_COP3 0x08000000
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_COP3_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_COP3_EN 0x08000000
|
|
+/** COP2 Clock Enable
|
|
+ Shows the clock enable bit for the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
|
|
+#define SYS_GPE_CLKS_COP2 0x04000000
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_COP2_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_COP2_EN 0x04000000
|
|
+/** COP1 Clock Enable
|
|
+ Shows the clock enable bit for the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
|
|
+#define SYS_GPE_CLKS_COP1 0x02000000
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_COP1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_COP1_EN 0x02000000
|
|
+/** COP0 Clock Enable
|
|
+ Shows the clock enable bit for the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
|
|
+#define SYS_GPE_CLKS_COP0 0x01000000
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_COP0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_COP0_EN 0x01000000
|
|
+/** PE5 Clock Enable
|
|
+ Shows the clock enable bit for the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
|
|
+#define SYS_GPE_CLKS_PE5 0x00200000
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_PE5_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_PE5_EN 0x00200000
|
|
+/** PE4 Clock Enable
|
|
+ Shows the clock enable bit for the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
|
|
+#define SYS_GPE_CLKS_PE4 0x00100000
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_PE4_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_PE4_EN 0x00100000
|
|
+/** PE3 Clock Enable
|
|
+ Shows the clock enable bit for the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
|
|
+#define SYS_GPE_CLKS_PE3 0x00080000
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_PE3_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_PE3_EN 0x00080000
|
|
+/** PE2 Clock Enable
|
|
+ Shows the clock enable bit for the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
|
|
+#define SYS_GPE_CLKS_PE2 0x00040000
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_PE2_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_PE2_EN 0x00040000
|
|
+/** PE1 Clock Enable
|
|
+ Shows the clock enable bit for the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
|
|
+#define SYS_GPE_CLKS_PE1 0x00020000
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_PE1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_PE1_EN 0x00020000
|
|
+/** PE0 Clock Enable
|
|
+ Shows the clock enable bit for the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
|
|
+#define SYS_GPE_CLKS_PE0 0x00010000
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_PE0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_PE0_EN 0x00010000
|
|
+/** ARB Clock Enable
|
|
+ Shows the clock enable bit for the ARB domain. This domain contains the Arbiter. */
|
|
+#define SYS_GPE_CLKS_ARB 0x00002000
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_ARB_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_ARB_EN 0x00002000
|
|
+/** FSQM Clock Enable
|
|
+ Shows the clock enable bit for the FSQM domain. This domain contains the FSQM. */
|
|
+#define SYS_GPE_CLKS_FSQM 0x00001000
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_FSQM_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_FSQM_EN 0x00001000
|
|
+/** TMU Clock Enable
|
|
+ Shows the clock enable bit for the TMU domain. This domain contains the TMU. */
|
|
+#define SYS_GPE_CLKS_TMU 0x00000800
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_TMU_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_TMU_EN 0x00000800
|
|
+/** MRG Clock Enable
|
|
+ Shows the clock enable bit for the MRG domain. This domain contains the Merger. */
|
|
+#define SYS_GPE_CLKS_MRG 0x00000400
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_MRG_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_MRG_EN 0x00000400
|
|
+/** DISP Clock Enable
|
|
+ Shows the clock enable bit for the DISP domain. This domain contains the Dispatcher. */
|
|
+#define SYS_GPE_CLKS_DISP 0x00000200
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_DISP_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_DISP_EN 0x00000200
|
|
+/** IQM Clock Enable
|
|
+ Shows the clock enable bit for the IQM domain. This domain contains the IQM. */
|
|
+#define SYS_GPE_CLKS_IQM 0x00000100
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_IQM_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_IQM_EN 0x00000100
|
|
+/** CPUE Clock Enable
|
|
+ Shows the clock enable bit for the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
|
|
+#define SYS_GPE_CLKS_CPUE 0x00000080
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_CPUE_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_CPUE_EN 0x00000080
|
|
+/** CPUI Clock Enable
|
|
+ Shows the clock enable bit for the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
|
|
+#define SYS_GPE_CLKS_CPUI 0x00000040
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_CPUI_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_CPUI_EN 0x00000040
|
|
+/** GPONE Clock Enable
|
|
+ Shows the clock enable bit for the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
|
|
+#define SYS_GPE_CLKS_GPONE 0x00000020
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_GPONE_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_GPONE_EN 0x00000020
|
|
+/** GPONI Clock Enable
|
|
+ Shows the clock enable bit for the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
|
|
+#define SYS_GPE_CLKS_GPONI 0x00000010
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_GPONI_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_GPONI_EN 0x00000010
|
|
+/** LAN3 Clock Enable
|
|
+ Shows the clock enable bit for the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
|
|
+#define SYS_GPE_CLKS_LAN3 0x00000008
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_LAN3_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_LAN3_EN 0x00000008
|
|
+/** LAN2 Clock Enable
|
|
+ Shows the clock enable bit for the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
|
|
+#define SYS_GPE_CLKS_LAN2 0x00000004
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_LAN2_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_LAN2_EN 0x00000004
|
|
+/** LAN1 Clock Enable
|
|
+ Shows the clock enable bit for the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
|
|
+#define SYS_GPE_CLKS_LAN1 0x00000002
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_LAN1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_LAN1_EN 0x00000002
|
|
+/** LAN0 Clock Enable
|
|
+ Shows the clock enable bit for the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
|
|
+#define SYS_GPE_CLKS_LAN0 0x00000001
|
|
+/* Disable
|
|
+#define SYS_GPE_CLKS_LAN0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_CLKS_LAN0_EN 0x00000001
|
|
+
|
|
+/* Fields of "Clock Enable Register" */
|
|
+/** Set Clock Enable COP7
|
|
+ Sets the clock enable bit of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
|
|
+#define SYS_GPE_CLKEN_COP7 0x80000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_COP7_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_COP7_SET 0x80000000
|
|
+/** Set Clock Enable COP6
|
|
+ Sets the clock enable bit of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
|
|
+#define SYS_GPE_CLKEN_COP6 0x40000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_COP6_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_COP6_SET 0x40000000
|
|
+/** Set Clock Enable COP5
|
|
+ Sets the clock enable bit of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
|
|
+#define SYS_GPE_CLKEN_COP5 0x20000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_COP5_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_COP5_SET 0x20000000
|
|
+/** Set Clock Enable COP4
|
|
+ Sets the clock enable bit of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
|
|
+#define SYS_GPE_CLKEN_COP4 0x10000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_COP4_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_COP4_SET 0x10000000
|
|
+/** Set Clock Enable COP3
|
|
+ Sets the clock enable bit of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
|
|
+#define SYS_GPE_CLKEN_COP3 0x08000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_COP3_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_COP3_SET 0x08000000
|
|
+/** Set Clock Enable COP2
|
|
+ Sets the clock enable bit of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
|
|
+#define SYS_GPE_CLKEN_COP2 0x04000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_COP2_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_COP2_SET 0x04000000
|
|
+/** Set Clock Enable COP1
|
|
+ Sets the clock enable bit of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
|
|
+#define SYS_GPE_CLKEN_COP1 0x02000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_COP1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_COP1_SET 0x02000000
|
|
+/** Set Clock Enable COP0
|
|
+ Sets the clock enable bit of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
|
|
+#define SYS_GPE_CLKEN_COP0 0x01000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_COP0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_COP0_SET 0x01000000
|
|
+/** Set Clock Enable PE5
|
|
+ Sets the clock enable bit of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
|
|
+#define SYS_GPE_CLKEN_PE5 0x00200000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_PE5_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_PE5_SET 0x00200000
|
|
+/** Set Clock Enable PE4
|
|
+ Sets the clock enable bit of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
|
|
+#define SYS_GPE_CLKEN_PE4 0x00100000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_PE4_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_PE4_SET 0x00100000
|
|
+/** Set Clock Enable PE3
|
|
+ Sets the clock enable bit of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
|
|
+#define SYS_GPE_CLKEN_PE3 0x00080000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_PE3_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_PE3_SET 0x00080000
|
|
+/** Set Clock Enable PE2
|
|
+ Sets the clock enable bit of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
|
|
+#define SYS_GPE_CLKEN_PE2 0x00040000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_PE2_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_PE2_SET 0x00040000
|
|
+/** Set Clock Enable PE1
|
|
+ Sets the clock enable bit of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
|
|
+#define SYS_GPE_CLKEN_PE1 0x00020000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_PE1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_PE1_SET 0x00020000
|
|
+/** Set Clock Enable PE0
|
|
+ Sets the clock enable bit of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
|
|
+#define SYS_GPE_CLKEN_PE0 0x00010000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_PE0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_PE0_SET 0x00010000
|
|
+/** Set Clock Enable ARB
|
|
+ Sets the clock enable bit of the ARB domain. This domain contains the Arbiter. */
|
|
+#define SYS_GPE_CLKEN_ARB 0x00002000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_ARB_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_ARB_SET 0x00002000
|
|
+/** Set Clock Enable FSQM
|
|
+ Sets the clock enable bit of the FSQM domain. This domain contains the FSQM. */
|
|
+#define SYS_GPE_CLKEN_FSQM 0x00001000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_FSQM_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_FSQM_SET 0x00001000
|
|
+/** Set Clock Enable TMU
|
|
+ Sets the clock enable bit of the TMU domain. This domain contains the TMU. */
|
|
+#define SYS_GPE_CLKEN_TMU 0x00000800
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_TMU_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_TMU_SET 0x00000800
|
|
+/** Set Clock Enable MRG
|
|
+ Sets the clock enable bit of the MRG domain. This domain contains the Merger. */
|
|
+#define SYS_GPE_CLKEN_MRG 0x00000400
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_MRG_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_MRG_SET 0x00000400
|
|
+/** Set Clock Enable DISP
|
|
+ Sets the clock enable bit of the DISP domain. This domain contains the Dispatcher. */
|
|
+#define SYS_GPE_CLKEN_DISP 0x00000200
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_DISP_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_DISP_SET 0x00000200
|
|
+/** Set Clock Enable IQM
|
|
+ Sets the clock enable bit of the IQM domain. This domain contains the IQM. */
|
|
+#define SYS_GPE_CLKEN_IQM 0x00000100
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_IQM_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_IQM_SET 0x00000100
|
|
+/** Set Clock Enable CPUE
|
|
+ Sets the clock enable bit of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
|
|
+#define SYS_GPE_CLKEN_CPUE 0x00000080
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_CPUE_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_CPUE_SET 0x00000080
|
|
+/** Set Clock Enable CPUI
|
|
+ Sets the clock enable bit of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
|
|
+#define SYS_GPE_CLKEN_CPUI 0x00000040
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_CPUI_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_CPUI_SET 0x00000040
|
|
+/** Set Clock Enable GPONE
|
|
+ Sets the clock enable bit of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
|
|
+#define SYS_GPE_CLKEN_GPONE 0x00000020
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_GPONE_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_GPONE_SET 0x00000020
|
|
+/** Set Clock Enable GPONI
|
|
+ Sets the clock enable bit of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
|
|
+#define SYS_GPE_CLKEN_GPONI 0x00000010
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_GPONI_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_GPONI_SET 0x00000010
|
|
+/** Set Clock Enable LAN3
|
|
+ Sets the clock enable bit of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
|
|
+#define SYS_GPE_CLKEN_LAN3 0x00000008
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_LAN3_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_LAN3_SET 0x00000008
|
|
+/** Set Clock Enable LAN2
|
|
+ Sets the clock enable bit of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
|
|
+#define SYS_GPE_CLKEN_LAN2 0x00000004
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_LAN2_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_LAN2_SET 0x00000004
|
|
+/** Set Clock Enable LAN1
|
|
+ Sets the clock enable bit of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
|
|
+#define SYS_GPE_CLKEN_LAN1 0x00000002
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_LAN1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_LAN1_SET 0x00000002
|
|
+/** Set Clock Enable LAN0
|
|
+ Sets the clock enable bit of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
|
|
+#define SYS_GPE_CLKEN_LAN0 0x00000001
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKEN_LAN0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_CLKEN_LAN0_SET 0x00000001
|
|
+
|
|
+/* Fields of "Clock Clear Register" */
|
|
+/** Clear Clock Enable COP7
|
|
+ Clears the clock enable bit of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
|
|
+#define SYS_GPE_CLKCLR_COP7 0x80000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_COP7_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_COP7_CLR 0x80000000
|
|
+/** Clear Clock Enable COP6
|
|
+ Clears the clock enable bit of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
|
|
+#define SYS_GPE_CLKCLR_COP6 0x40000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_COP6_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_COP6_CLR 0x40000000
|
|
+/** Clear Clock Enable COP5
|
|
+ Clears the clock enable bit of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
|
|
+#define SYS_GPE_CLKCLR_COP5 0x20000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_COP5_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_COP5_CLR 0x20000000
|
|
+/** Clear Clock Enable COP4
|
|
+ Clears the clock enable bit of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
|
|
+#define SYS_GPE_CLKCLR_COP4 0x10000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_COP4_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_COP4_CLR 0x10000000
|
|
+/** Clear Clock Enable COP3
|
|
+ Clears the clock enable bit of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
|
|
+#define SYS_GPE_CLKCLR_COP3 0x08000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_COP3_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_COP3_CLR 0x08000000
|
|
+/** Clear Clock Enable COP2
|
|
+ Clears the clock enable bit of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
|
|
+#define SYS_GPE_CLKCLR_COP2 0x04000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_COP2_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_COP2_CLR 0x04000000
|
|
+/** Clear Clock Enable COP1
|
|
+ Clears the clock enable bit of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
|
|
+#define SYS_GPE_CLKCLR_COP1 0x02000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_COP1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_COP1_CLR 0x02000000
|
|
+/** Clear Clock Enable COP0
|
|
+ Clears the clock enable bit of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
|
|
+#define SYS_GPE_CLKCLR_COP0 0x01000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_COP0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_COP0_CLR 0x01000000
|
|
+/** Clear Clock Enable PE5
|
|
+ Clears the clock enable bit of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
|
|
+#define SYS_GPE_CLKCLR_PE5 0x00200000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_PE5_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_PE5_CLR 0x00200000
|
|
+/** Clear Clock Enable PE4
|
|
+ Clears the clock enable bit of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
|
|
+#define SYS_GPE_CLKCLR_PE4 0x00100000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_PE4_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_PE4_CLR 0x00100000
|
|
+/** Clear Clock Enable PE3
|
|
+ Clears the clock enable bit of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
|
|
+#define SYS_GPE_CLKCLR_PE3 0x00080000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_PE3_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_PE3_CLR 0x00080000
|
|
+/** Clear Clock Enable PE2
|
|
+ Clears the clock enable bit of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
|
|
+#define SYS_GPE_CLKCLR_PE2 0x00040000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_PE2_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_PE2_CLR 0x00040000
|
|
+/** Clear Clock Enable PE1
|
|
+ Clears the clock enable bit of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
|
|
+#define SYS_GPE_CLKCLR_PE1 0x00020000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_PE1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_PE1_CLR 0x00020000
|
|
+/** Clear Clock Enable PE0
|
|
+ Clears the clock enable bit of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
|
|
+#define SYS_GPE_CLKCLR_PE0 0x00010000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_PE0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_PE0_CLR 0x00010000
|
|
+/** Clear Clock Enable ARB
|
|
+ Clears the clock enable bit of the ARB domain. This domain contains the Arbiter. */
|
|
+#define SYS_GPE_CLKCLR_ARB 0x00002000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_ARB_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_ARB_CLR 0x00002000
|
|
+/** Clear Clock Enable FSQM
|
|
+ Clears the clock enable bit of the FSQM domain. This domain contains the FSQM. */
|
|
+#define SYS_GPE_CLKCLR_FSQM 0x00001000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_FSQM_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_FSQM_CLR 0x00001000
|
|
+/** Clear Clock Enable TMU
|
|
+ Clears the clock enable bit of the TMU domain. This domain contains the TMU. */
|
|
+#define SYS_GPE_CLKCLR_TMU 0x00000800
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_TMU_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_TMU_CLR 0x00000800
|
|
+/** Clear Clock Enable MRG
|
|
+ Clears the clock enable bit of the MRG domain. This domain contains the Merger. */
|
|
+#define SYS_GPE_CLKCLR_MRG 0x00000400
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_MRG_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_MRG_CLR 0x00000400
|
|
+/** Clear Clock Enable DISP
|
|
+ Clears the clock enable bit of the DISP domain. This domain contains the Dispatcher. */
|
|
+#define SYS_GPE_CLKCLR_DISP 0x00000200
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_DISP_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_DISP_CLR 0x00000200
|
|
+/** Clear Clock Enable IQM
|
|
+ Clears the clock enable bit of the IQM domain. This domain contains the IQM. */
|
|
+#define SYS_GPE_CLKCLR_IQM 0x00000100
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_IQM_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_IQM_CLR 0x00000100
|
|
+/** Clear Clock Enable CPUE
|
|
+ Clears the clock enable bit of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
|
|
+#define SYS_GPE_CLKCLR_CPUE 0x00000080
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_CPUE_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_CPUE_CLR 0x00000080
|
|
+/** Clear Clock Enable CPUI
|
|
+ Clears the clock enable bit of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
|
|
+#define SYS_GPE_CLKCLR_CPUI 0x00000040
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_CPUI_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_CPUI_CLR 0x00000040
|
|
+/** Clear Clock Enable GPONE
|
|
+ Clears the clock enable bit of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
|
|
+#define SYS_GPE_CLKCLR_GPONE 0x00000020
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_GPONE_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_GPONE_CLR 0x00000020
|
|
+/** Clear Clock Enable GPONI
|
|
+ Clears the clock enable bit of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
|
|
+#define SYS_GPE_CLKCLR_GPONI 0x00000010
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_GPONI_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_GPONI_CLR 0x00000010
|
|
+/** Clear Clock Enable LAN3
|
|
+ Clears the clock enable bit of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
|
|
+#define SYS_GPE_CLKCLR_LAN3 0x00000008
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_LAN3_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_LAN3_CLR 0x00000008
|
|
+/** Clear Clock Enable LAN2
|
|
+ Clears the clock enable bit of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
|
|
+#define SYS_GPE_CLKCLR_LAN2 0x00000004
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_LAN2_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_LAN2_CLR 0x00000004
|
|
+/** Clear Clock Enable LAN1
|
|
+ Clears the clock enable bit of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
|
|
+#define SYS_GPE_CLKCLR_LAN1 0x00000002
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_LAN1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_LAN1_CLR 0x00000002
|
|
+/** Clear Clock Enable LAN0
|
|
+ Clears the clock enable bit of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
|
|
+#define SYS_GPE_CLKCLR_LAN0 0x00000001
|
|
+/* No-Operation
|
|
+#define SYS_GPE_CLKCLR_LAN0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_CLKCLR_LAN0_CLR 0x00000001
|
|
+
|
|
+/* Fields of "Activation Status Register" */
|
|
+/** COP7 Status
|
|
+ Shows the activation status of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
|
|
+#define SYS_GPE_ACTS_COP7 0x80000000
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_COP7_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_COP7_ACT 0x80000000
|
|
+/** COP6 Status
|
|
+ Shows the activation status of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
|
|
+#define SYS_GPE_ACTS_COP6 0x40000000
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_COP6_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_COP6_ACT 0x40000000
|
|
+/** COP5 Status
|
|
+ Shows the activation status of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
|
|
+#define SYS_GPE_ACTS_COP5 0x20000000
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_COP5_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_COP5_ACT 0x20000000
|
|
+/** COP4 Status
|
|
+ Shows the activation status of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
|
|
+#define SYS_GPE_ACTS_COP4 0x10000000
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_COP4_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_COP4_ACT 0x10000000
|
|
+/** COP3 Status
|
|
+ Shows the activation status of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
|
|
+#define SYS_GPE_ACTS_COP3 0x08000000
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_COP3_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_COP3_ACT 0x08000000
|
|
+/** COP2 Status
|
|
+ Shows the activation status of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
|
|
+#define SYS_GPE_ACTS_COP2 0x04000000
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_COP2_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_COP2_ACT 0x04000000
|
|
+/** COP1 Status
|
|
+ Shows the activation status of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
|
|
+#define SYS_GPE_ACTS_COP1 0x02000000
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_COP1_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_COP1_ACT 0x02000000
|
|
+/** COP0 Status
|
|
+ Shows the activation status of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
|
|
+#define SYS_GPE_ACTS_COP0 0x01000000
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_COP0_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_COP0_ACT 0x01000000
|
|
+/** PE5 Status
|
|
+ Shows the activation status of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
|
|
+#define SYS_GPE_ACTS_PE5 0x00200000
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_PE5_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_PE5_ACT 0x00200000
|
|
+/** PE4 Status
|
|
+ Shows the activation status of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
|
|
+#define SYS_GPE_ACTS_PE4 0x00100000
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_PE4_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_PE4_ACT 0x00100000
|
|
+/** PE3 Status
|
|
+ Shows the activation status of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
|
|
+#define SYS_GPE_ACTS_PE3 0x00080000
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_PE3_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_PE3_ACT 0x00080000
|
|
+/** PE2 Status
|
|
+ Shows the activation status of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
|
|
+#define SYS_GPE_ACTS_PE2 0x00040000
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_PE2_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_PE2_ACT 0x00040000
|
|
+/** PE1 Status
|
|
+ Shows the activation status of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
|
|
+#define SYS_GPE_ACTS_PE1 0x00020000
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_PE1_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_PE1_ACT 0x00020000
|
|
+/** PE0 Status
|
|
+ Shows the activation status of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
|
|
+#define SYS_GPE_ACTS_PE0 0x00010000
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_PE0_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_PE0_ACT 0x00010000
|
|
+/** ARB Status
|
|
+ Shows the activation status of the ARB domain. This domain contains the Arbiter. */
|
|
+#define SYS_GPE_ACTS_ARB 0x00002000
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_ARB_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_ARB_ACT 0x00002000
|
|
+/** FSQM Status
|
|
+ Shows the activation status of the FSQM domain. This domain contains the FSQM. */
|
|
+#define SYS_GPE_ACTS_FSQM 0x00001000
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_FSQM_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_FSQM_ACT 0x00001000
|
|
+/** TMU Status
|
|
+ Shows the activation status of the TMU domain. This domain contains the TMU. */
|
|
+#define SYS_GPE_ACTS_TMU 0x00000800
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_TMU_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_TMU_ACT 0x00000800
|
|
+/** MRG Status
|
|
+ Shows the activation status of the MRG domain. This domain contains the Merger. */
|
|
+#define SYS_GPE_ACTS_MRG 0x00000400
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_MRG_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_MRG_ACT 0x00000400
|
|
+/** DISP Status
|
|
+ Shows the activation status of the DISP domain. This domain contains the Dispatcher. */
|
|
+#define SYS_GPE_ACTS_DISP 0x00000200
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_DISP_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_DISP_ACT 0x00000200
|
|
+/** IQM Status
|
|
+ Shows the activation status of the IQM domain. This domain contains the IQM. */
|
|
+#define SYS_GPE_ACTS_IQM 0x00000100
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_IQM_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_IQM_ACT 0x00000100
|
|
+/** CPUE Status
|
|
+ Shows the activation status of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
|
|
+#define SYS_GPE_ACTS_CPUE 0x00000080
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_CPUE_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_CPUE_ACT 0x00000080
|
|
+/** CPUI Status
|
|
+ Shows the activation status of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
|
|
+#define SYS_GPE_ACTS_CPUI 0x00000040
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_CPUI_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_CPUI_ACT 0x00000040
|
|
+/** GPONE Status
|
|
+ Shows the activation status of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
|
|
+#define SYS_GPE_ACTS_GPONE 0x00000020
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_GPONE_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_GPONE_ACT 0x00000020
|
|
+/** GPONI Status
|
|
+ Shows the activation status of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
|
|
+#define SYS_GPE_ACTS_GPONI 0x00000010
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_GPONI_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_GPONI_ACT 0x00000010
|
|
+/** LAN3 Status
|
|
+ Shows the activation status of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
|
|
+#define SYS_GPE_ACTS_LAN3 0x00000008
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_LAN3_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_LAN3_ACT 0x00000008
|
|
+/** LAN2 Status
|
|
+ Shows the activation status of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
|
|
+#define SYS_GPE_ACTS_LAN2 0x00000004
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_LAN2_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_LAN2_ACT 0x00000004
|
|
+/** LAN1 Status
|
|
+ Shows the activation status of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
|
|
+#define SYS_GPE_ACTS_LAN1 0x00000002
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_LAN1_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_LAN1_ACT 0x00000002
|
|
+/** LAN0 Status
|
|
+ Shows the activation status of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
|
|
+#define SYS_GPE_ACTS_LAN0 0x00000001
|
|
+/* The block is inactive.
|
|
+#define SYS_GPE_ACTS_LAN0_INACT 0x00000000 */
|
|
+/** The block is active. */
|
|
+#define SYS_GPE_ACTS_LAN0_ACT 0x00000001
|
|
+
|
|
+/* Fields of "Activation Register" */
|
|
+/** Activate COP7
|
|
+ Sets the activation flag of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
|
|
+#define SYS_GPE_ACT_COP7 0x80000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_COP7_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_COP7_SET 0x80000000
|
|
+/** Activate COP6
|
|
+ Sets the activation flag of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
|
|
+#define SYS_GPE_ACT_COP6 0x40000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_COP6_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_COP6_SET 0x40000000
|
|
+/** Activate COP5
|
|
+ Sets the activation flag of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
|
|
+#define SYS_GPE_ACT_COP5 0x20000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_COP5_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_COP5_SET 0x20000000
|
|
+/** Activate COP4
|
|
+ Sets the activation flag of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
|
|
+#define SYS_GPE_ACT_COP4 0x10000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_COP4_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_COP4_SET 0x10000000
|
|
+/** Activate COP3
|
|
+ Sets the activation flag of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
|
|
+#define SYS_GPE_ACT_COP3 0x08000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_COP3_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_COP3_SET 0x08000000
|
|
+/** Activate COP2
|
|
+ Sets the activation flag of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
|
|
+#define SYS_GPE_ACT_COP2 0x04000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_COP2_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_COP2_SET 0x04000000
|
|
+/** Activate COP1
|
|
+ Sets the activation flag of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
|
|
+#define SYS_GPE_ACT_COP1 0x02000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_COP1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_COP1_SET 0x02000000
|
|
+/** Activate COP0
|
|
+ Sets the activation flag of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
|
|
+#define SYS_GPE_ACT_COP0 0x01000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_COP0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_COP0_SET 0x01000000
|
|
+/** Activate PE5
|
|
+ Sets the activation flag of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
|
|
+#define SYS_GPE_ACT_PE5 0x00200000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_PE5_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_PE5_SET 0x00200000
|
|
+/** Activate PE4
|
|
+ Sets the activation flag of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
|
|
+#define SYS_GPE_ACT_PE4 0x00100000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_PE4_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_PE4_SET 0x00100000
|
|
+/** Activate PE3
|
|
+ Sets the activation flag of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
|
|
+#define SYS_GPE_ACT_PE3 0x00080000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_PE3_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_PE3_SET 0x00080000
|
|
+/** Activate PE2
|
|
+ Sets the activation flag of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
|
|
+#define SYS_GPE_ACT_PE2 0x00040000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_PE2_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_PE2_SET 0x00040000
|
|
+/** Activate PE1
|
|
+ Sets the activation flag of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
|
|
+#define SYS_GPE_ACT_PE1 0x00020000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_PE1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_PE1_SET 0x00020000
|
|
+/** Activate PE0
|
|
+ Sets the activation flag of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
|
|
+#define SYS_GPE_ACT_PE0 0x00010000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_PE0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_PE0_SET 0x00010000
|
|
+/** Activate ARB
|
|
+ Sets the activation flag of the ARB domain. This domain contains the Arbiter. */
|
|
+#define SYS_GPE_ACT_ARB 0x00002000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_ARB_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_ARB_SET 0x00002000
|
|
+/** Activate FSQM
|
|
+ Sets the activation flag of the FSQM domain. This domain contains the FSQM. */
|
|
+#define SYS_GPE_ACT_FSQM 0x00001000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_FSQM_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_FSQM_SET 0x00001000
|
|
+/** Activate TMU
|
|
+ Sets the activation flag of the TMU domain. This domain contains the TMU. */
|
|
+#define SYS_GPE_ACT_TMU 0x00000800
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_TMU_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_TMU_SET 0x00000800
|
|
+/** Activate MRG
|
|
+ Sets the activation flag of the MRG domain. This domain contains the Merger. */
|
|
+#define SYS_GPE_ACT_MRG 0x00000400
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_MRG_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_MRG_SET 0x00000400
|
|
+/** Activate DISP
|
|
+ Sets the activation flag of the DISP domain. This domain contains the Dispatcher. */
|
|
+#define SYS_GPE_ACT_DISP 0x00000200
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_DISP_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_DISP_SET 0x00000200
|
|
+/** Activate IQM
|
|
+ Sets the activation flag of the IQM domain. This domain contains the IQM. */
|
|
+#define SYS_GPE_ACT_IQM 0x00000100
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_IQM_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_IQM_SET 0x00000100
|
|
+/** Activate CPUE
|
|
+ Sets the activation flag of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
|
|
+#define SYS_GPE_ACT_CPUE 0x00000080
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_CPUE_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_CPUE_SET 0x00000080
|
|
+/** Activate CPUI
|
|
+ Sets the activation flag of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
|
|
+#define SYS_GPE_ACT_CPUI 0x00000040
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_CPUI_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_CPUI_SET 0x00000040
|
|
+/** Activate GPONE
|
|
+ Sets the activation flag of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
|
|
+#define SYS_GPE_ACT_GPONE 0x00000020
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_GPONE_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_GPONE_SET 0x00000020
|
|
+/** Activate GPONI
|
|
+ Sets the activation flag of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
|
|
+#define SYS_GPE_ACT_GPONI 0x00000010
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_GPONI_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_GPONI_SET 0x00000010
|
|
+/** Activate LAN3
|
|
+ Sets the activation flag of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
|
|
+#define SYS_GPE_ACT_LAN3 0x00000008
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_LAN3_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_LAN3_SET 0x00000008
|
|
+/** Activate LAN2
|
|
+ Sets the activation flag of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
|
|
+#define SYS_GPE_ACT_LAN2 0x00000004
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_LAN2_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_LAN2_SET 0x00000004
|
|
+/** Activate LAN1
|
|
+ Sets the activation flag of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
|
|
+#define SYS_GPE_ACT_LAN1 0x00000002
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_LAN1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_LAN1_SET 0x00000002
|
|
+/** Activate LAN0
|
|
+ Sets the activation flag of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
|
|
+#define SYS_GPE_ACT_LAN0 0x00000001
|
|
+/* No-Operation
|
|
+#define SYS_GPE_ACT_LAN0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_ACT_LAN0_SET 0x00000001
|
|
+
|
|
+/* Fields of "Deactivation Register" */
|
|
+/** Deactivate COP7
|
|
+ Clears the activation flag of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
|
|
+#define SYS_GPE_DEACT_COP7 0x80000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_COP7_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_COP7_CLR 0x80000000
|
|
+/** Deactivate COP6
|
|
+ Clears the activation flag of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
|
|
+#define SYS_GPE_DEACT_COP6 0x40000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_COP6_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_COP6_CLR 0x40000000
|
|
+/** Deactivate COP5
|
|
+ Clears the activation flag of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
|
|
+#define SYS_GPE_DEACT_COP5 0x20000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_COP5_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_COP5_CLR 0x20000000
|
|
+/** Deactivate COP4
|
|
+ Clears the activation flag of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
|
|
+#define SYS_GPE_DEACT_COP4 0x10000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_COP4_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_COP4_CLR 0x10000000
|
|
+/** Deactivate COP3
|
|
+ Clears the activation flag of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
|
|
+#define SYS_GPE_DEACT_COP3 0x08000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_COP3_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_COP3_CLR 0x08000000
|
|
+/** Deactivate COP2
|
|
+ Clears the activation flag of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
|
|
+#define SYS_GPE_DEACT_COP2 0x04000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_COP2_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_COP2_CLR 0x04000000
|
|
+/** Deactivate COP1
|
|
+ Clears the activation flag of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
|
|
+#define SYS_GPE_DEACT_COP1 0x02000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_COP1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_COP1_CLR 0x02000000
|
|
+/** Deactivate COP0
|
|
+ Clears the activation flag of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
|
|
+#define SYS_GPE_DEACT_COP0 0x01000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_COP0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_COP0_CLR 0x01000000
|
|
+/** Deactivate PE5
|
|
+ Clears the activation flag of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
|
|
+#define SYS_GPE_DEACT_PE5 0x00200000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_PE5_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_PE5_CLR 0x00200000
|
|
+/** Deactivate PE4
|
|
+ Clears the activation flag of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
|
|
+#define SYS_GPE_DEACT_PE4 0x00100000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_PE4_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_PE4_CLR 0x00100000
|
|
+/** Deactivate PE3
|
|
+ Clears the activation flag of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
|
|
+#define SYS_GPE_DEACT_PE3 0x00080000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_PE3_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_PE3_CLR 0x00080000
|
|
+/** Deactivate PE2
|
|
+ Clears the activation flag of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
|
|
+#define SYS_GPE_DEACT_PE2 0x00040000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_PE2_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_PE2_CLR 0x00040000
|
|
+/** Deactivate PE1
|
|
+ Clears the activation flag of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
|
|
+#define SYS_GPE_DEACT_PE1 0x00020000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_PE1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_PE1_CLR 0x00020000
|
|
+/** Deactivate PE0
|
|
+ Clears the activation flag of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
|
|
+#define SYS_GPE_DEACT_PE0 0x00010000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_PE0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_PE0_CLR 0x00010000
|
|
+/** Deactivate ARB
|
|
+ Clears the activation flag of the ARB domain. This domain contains the Arbiter. */
|
|
+#define SYS_GPE_DEACT_ARB 0x00002000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_ARB_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_ARB_CLR 0x00002000
|
|
+/** Deactivate FSQM
|
|
+ Clears the activation flag of the FSQM domain. This domain contains the FSQM. */
|
|
+#define SYS_GPE_DEACT_FSQM 0x00001000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_FSQM_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_FSQM_CLR 0x00001000
|
|
+/** Deactivate TMU
|
|
+ Clears the activation flag of the TMU domain. This domain contains the TMU. */
|
|
+#define SYS_GPE_DEACT_TMU 0x00000800
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_TMU_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_TMU_CLR 0x00000800
|
|
+/** Deactivate MRG
|
|
+ Clears the activation flag of the MRG domain. This domain contains the Merger. */
|
|
+#define SYS_GPE_DEACT_MRG 0x00000400
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_MRG_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_MRG_CLR 0x00000400
|
|
+/** Deactivate DISP
|
|
+ Clears the activation flag of the DISP domain. This domain contains the Dispatcher. */
|
|
+#define SYS_GPE_DEACT_DISP 0x00000200
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_DISP_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_DISP_CLR 0x00000200
|
|
+/** Deactivate IQM
|
|
+ Clears the activation flag of the IQM domain. This domain contains the IQM. */
|
|
+#define SYS_GPE_DEACT_IQM 0x00000100
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_IQM_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_IQM_CLR 0x00000100
|
|
+/** Deactivate CPUE
|
|
+ Clears the activation flag of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
|
|
+#define SYS_GPE_DEACT_CPUE 0x00000080
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_CPUE_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_CPUE_CLR 0x00000080
|
|
+/** Deactivate CPUI
|
|
+ Clears the activation flag of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
|
|
+#define SYS_GPE_DEACT_CPUI 0x00000040
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_CPUI_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_CPUI_CLR 0x00000040
|
|
+/** Deactivate GPONE
|
|
+ Clears the activation flag of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
|
|
+#define SYS_GPE_DEACT_GPONE 0x00000020
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_GPONE_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_GPONE_CLR 0x00000020
|
|
+/** Deactivate GPONI
|
|
+ Clears the activation flag of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
|
|
+#define SYS_GPE_DEACT_GPONI 0x00000010
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_GPONI_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_GPONI_CLR 0x00000010
|
|
+/** Deactivate LAN3
|
|
+ Clears the activation flag of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
|
|
+#define SYS_GPE_DEACT_LAN3 0x00000008
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_LAN3_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_LAN3_CLR 0x00000008
|
|
+/** Deactivate LAN2
|
|
+ Clears the activation flag of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
|
|
+#define SYS_GPE_DEACT_LAN2 0x00000004
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_LAN2_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_LAN2_CLR 0x00000004
|
|
+/** Deactivate LAN1
|
|
+ Clears the activation flag of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
|
|
+#define SYS_GPE_DEACT_LAN1 0x00000002
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_LAN1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_LAN1_CLR 0x00000002
|
|
+/** Deactivate LAN0
|
|
+ Clears the activation flag of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
|
|
+#define SYS_GPE_DEACT_LAN0 0x00000001
|
|
+/* No-Operation
|
|
+#define SYS_GPE_DEACT_LAN0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_DEACT_LAN0_CLR 0x00000001
|
|
+
|
|
+/* Fields of "Reboot Trigger Register" */
|
|
+/** Reboot COP7
|
|
+ Triggers a reboot of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */
|
|
+#define SYS_GPE_RBT_COP7 0x80000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_COP7_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_COP7_TRIG 0x80000000
|
|
+/** Reboot COP6
|
|
+ Triggers a reboot of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */
|
|
+#define SYS_GPE_RBT_COP6 0x40000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_COP6_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_COP6_TRIG 0x40000000
|
|
+/** Reboot COP5
|
|
+ Triggers a reboot of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */
|
|
+#define SYS_GPE_RBT_COP5 0x20000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_COP5_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_COP5_TRIG 0x20000000
|
|
+/** Reboot COP4
|
|
+ Triggers a reboot of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */
|
|
+#define SYS_GPE_RBT_COP4 0x10000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_COP4_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_COP4_TRIG 0x10000000
|
|
+/** Reboot COP3
|
|
+ Triggers a reboot of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */
|
|
+#define SYS_GPE_RBT_COP3 0x08000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_COP3_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_COP3_TRIG 0x08000000
|
|
+/** Reboot COP2
|
|
+ Triggers a reboot of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */
|
|
+#define SYS_GPE_RBT_COP2 0x04000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_COP2_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_COP2_TRIG 0x04000000
|
|
+/** Reboot COP1
|
|
+ Triggers a reboot of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */
|
|
+#define SYS_GPE_RBT_COP1 0x02000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_COP1_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_COP1_TRIG 0x02000000
|
|
+/** Reboot COP0
|
|
+ Triggers a reboot of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */
|
|
+#define SYS_GPE_RBT_COP0 0x01000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_COP0_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_COP0_TRIG 0x01000000
|
|
+/** Reboot PE5
|
|
+ Triggers a reboot of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */
|
|
+#define SYS_GPE_RBT_PE5 0x00200000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_PE5_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_PE5_TRIG 0x00200000
|
|
+/** Reboot PE4
|
|
+ Triggers a reboot of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */
|
|
+#define SYS_GPE_RBT_PE4 0x00100000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_PE4_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_PE4_TRIG 0x00100000
|
|
+/** Reboot PE3
|
|
+ Triggers a reboot of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */
|
|
+#define SYS_GPE_RBT_PE3 0x00080000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_PE3_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_PE3_TRIG 0x00080000
|
|
+/** Reboot PE2
|
|
+ Triggers a reboot of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */
|
|
+#define SYS_GPE_RBT_PE2 0x00040000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_PE2_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_PE2_TRIG 0x00040000
|
|
+/** Reboot PE1
|
|
+ Triggers a reboot of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */
|
|
+#define SYS_GPE_RBT_PE1 0x00020000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_PE1_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_PE1_TRIG 0x00020000
|
|
+/** Reboot PE0
|
|
+ Triggers a reboot of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */
|
|
+#define SYS_GPE_RBT_PE0 0x00010000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_PE0_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_PE0_TRIG 0x00010000
|
|
+/** Reboot ARB
|
|
+ Triggers a reboot of the ARB domain. This domain contains the Arbiter. */
|
|
+#define SYS_GPE_RBT_ARB 0x00002000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_ARB_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_ARB_TRIG 0x00002000
|
|
+/** Reboot FSQM
|
|
+ Triggers a reboot of the FSQM domain. This domain contains the FSQM. */
|
|
+#define SYS_GPE_RBT_FSQM 0x00001000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_FSQM_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_FSQM_TRIG 0x00001000
|
|
+/** Reboot TMU
|
|
+ Triggers a reboot of the TMU domain. This domain contains the TMU. */
|
|
+#define SYS_GPE_RBT_TMU 0x00000800
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_TMU_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_TMU_TRIG 0x00000800
|
|
+/** Reboot MRG
|
|
+ Triggers a reboot of the MRG domain. This domain contains the Merger. */
|
|
+#define SYS_GPE_RBT_MRG 0x00000400
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_MRG_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_MRG_TRIG 0x00000400
|
|
+/** Reboot DISP
|
|
+ Triggers a reboot of the DISP domain. This domain contains the Dispatcher. */
|
|
+#define SYS_GPE_RBT_DISP 0x00000200
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_DISP_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_DISP_TRIG 0x00000200
|
|
+/** Reboot IQM
|
|
+ Triggers a reboot of the IQM domain. This domain contains the IQM. */
|
|
+#define SYS_GPE_RBT_IQM 0x00000100
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_IQM_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_IQM_TRIG 0x00000100
|
|
+/** Reboot CPUE
|
|
+ Triggers a reboot of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */
|
|
+#define SYS_GPE_RBT_CPUE 0x00000080
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_CPUE_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_CPUE_TRIG 0x00000080
|
|
+/** Reboot CPUI
|
|
+ Triggers a reboot of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */
|
|
+#define SYS_GPE_RBT_CPUI 0x00000040
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_CPUI_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_CPUI_TRIG 0x00000040
|
|
+/** Reboot GPONE
|
|
+ Triggers a reboot of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
|
|
+#define SYS_GPE_RBT_GPONE 0x00000020
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_GPONE_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_GPONE_TRIG 0x00000020
|
|
+/** Reboot GPONI
|
|
+ Triggers a reboot of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
|
|
+#define SYS_GPE_RBT_GPONI 0x00000010
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_GPONI_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_GPONI_TRIG 0x00000010
|
|
+/** Reboot LAN3
|
|
+ Triggers a reboot of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */
|
|
+#define SYS_GPE_RBT_LAN3 0x00000008
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_LAN3_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_LAN3_TRIG 0x00000008
|
|
+/** Reboot LAN2
|
|
+ Triggers a reboot of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */
|
|
+#define SYS_GPE_RBT_LAN2 0x00000004
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_LAN2_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_LAN2_TRIG 0x00000004
|
|
+/** Reboot LAN1
|
|
+ Triggers a reboot of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */
|
|
+#define SYS_GPE_RBT_LAN1 0x00000002
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_LAN1_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_LAN1_TRIG 0x00000002
|
|
+/** Reboot LAN0
|
|
+ Triggers a reboot of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */
|
|
+#define SYS_GPE_RBT_LAN0 0x00000001
|
|
+/* No-Operation
|
|
+#define SYS_GPE_RBT_LAN0_NOP 0x00000000 */
|
|
+/** Trigger */
|
|
+#define SYS_GPE_RBT_LAN0_TRIG 0x00000001
|
|
+
|
|
+/* Fields of "Power Down Configuration Register" */
|
|
+/** Enable Power Down COP7
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_COP7 0x80000000
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_COP7_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_COP7_EN 0x80000000
|
|
+/** Enable Power Down COP6
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_COP6 0x40000000
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_COP6_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_COP6_EN 0x40000000
|
|
+/** Enable Power Down COP5
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_COP5 0x20000000
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_COP5_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_COP5_EN 0x20000000
|
|
+/** Enable Power Down COP4
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_COP4 0x10000000
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_COP4_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_COP4_EN 0x10000000
|
|
+/** Enable Power Down COP3
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_COP3 0x08000000
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_COP3_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_COP3_EN 0x08000000
|
|
+/** Enable Power Down COP2
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_COP2 0x04000000
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_COP2_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_COP2_EN 0x04000000
|
|
+/** Enable Power Down COP1
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_COP1 0x02000000
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_COP1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_COP1_EN 0x02000000
|
|
+/** Enable Power Down COP0
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_COP0 0x01000000
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_COP0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_COP0_EN 0x01000000
|
|
+/** Enable Power Down PE5
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_PE5 0x00200000
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_PE5_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_PE5_EN 0x00200000
|
|
+/** Enable Power Down PE4
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_PE4 0x00100000
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_PE4_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_PE4_EN 0x00100000
|
|
+/** Enable Power Down PE3
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_PE3 0x00080000
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_PE3_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_PE3_EN 0x00080000
|
|
+/** Enable Power Down PE2
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_PE2 0x00040000
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_PE2_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_PE2_EN 0x00040000
|
|
+/** Enable Power Down PE1
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_PE1 0x00020000
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_PE1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_PE1_EN 0x00020000
|
|
+/** Enable Power Down PE0
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_PE0 0x00010000
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_PE0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_PE0_EN 0x00010000
|
|
+/** Enable Power Down ARB
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_ARB 0x00002000
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_ARB_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_ARB_EN 0x00002000
|
|
+/** Enable Power Down FSQM
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_FSQM 0x00001000
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_FSQM_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_FSQM_EN 0x00001000
|
|
+/** Enable Power Down TMU
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_TMU 0x00000800
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_TMU_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_TMU_EN 0x00000800
|
|
+/** Enable Power Down MRG
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_MRG 0x00000400
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_MRG_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_MRG_EN 0x00000400
|
|
+/** Enable Power Down DISP
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_DISP 0x00000200
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_DISP_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_DISP_EN 0x00000200
|
|
+/** Enable Power Down IQM
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_IQM 0x00000100
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_IQM_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_IQM_EN 0x00000100
|
|
+/** Enable Power Down CPUE
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_CPUE 0x00000080
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_CPUE_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_CPUE_EN 0x00000080
|
|
+/** Enable Power Down CPUI
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_CPUI 0x00000040
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_CPUI_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_CPUI_EN 0x00000040
|
|
+/** Enable Power Down GPONE
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_GPONE 0x00000020
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_GPONE_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_GPONE_EN 0x00000020
|
|
+/** Enable Power Down GPONI
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_GPONI 0x00000010
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_GPONI_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_GPONI_EN 0x00000010
|
|
+/** Enable Power Down LAN3
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_LAN3 0x00000008
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_LAN3_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_LAN3_EN 0x00000008
|
|
+/** Enable Power Down LAN2
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_LAN2 0x00000004
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_LAN2_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_LAN2_EN 0x00000004
|
|
+/** Enable Power Down LAN1
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_LAN1 0x00000002
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_LAN1_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_LAN1_EN 0x00000002
|
|
+/** Enable Power Down LAN0
|
|
+ Ignore this bit as power-gating is not supported for this chip. */
|
|
+#define SYS_GPE_PDCFG_LAN0 0x00000001
|
|
+/* Disable
|
|
+#define SYS_GPE_PDCFG_LAN0_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_PDCFG_LAN0_EN 0x00000001
|
|
+
|
|
+/* Fields of "Sleep Source Configuration Register" */
|
|
+/** Sleep/Wakeup Source CPU
|
|
+ Selects the CPU access signal as sleep/wakeup source. */
|
|
+#define SYS_GPE_SSCFG_CPU 0x00020000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SSCFG_CPU_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SSCFG_CPU_SEL 0x00020000
|
|
+/** Sleep/Wakeup Source FSQM
|
|
+ Selects the FSQM signal as sleep/wakeup source. */
|
|
+#define SYS_GPE_SSCFG_FSQM 0x00008000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SSCFG_FSQM_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SSCFG_FSQM_SEL 0x00008000
|
|
+/** Sleep/Wakeup Source GPONT
|
|
+ Selects the FIFO empty signal of the TCONT Request FIFO of port GPON as sleep/wakeup source. */
|
|
+#define SYS_GPE_SSCFG_GPONT 0x00002000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SSCFG_GPONT_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SSCFG_GPONT_SEL 0x00002000
|
|
+/** Sleep/Wakeup Source GPONE
|
|
+ Selects the FIFO empty signal of the EGRESS FIFO of port GPON as sleep/wakeup source. */
|
|
+#define SYS_GPE_SSCFG_GPONE 0x00001000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SSCFG_GPONE_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SSCFG_GPONE_SEL 0x00001000
|
|
+/** Sleep/Wakeup Source LAN3E
|
|
+ Selects the FIFO empty signal of the EGRESS FIFO of port LAN3 as sleep/wakeup source. */
|
|
+#define SYS_GPE_SSCFG_LAN3E 0x00000800
|
|
+/* Not selected
|
|
+#define SYS_GPE_SSCFG_LAN3E_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SSCFG_LAN3E_SEL 0x00000800
|
|
+/** Sleep/Wakeup Source LAN2E
|
|
+ Selects the FIFO empty signal of the EGRESS FIFO of port LAN2 as sleep/wakeup source. */
|
|
+#define SYS_GPE_SSCFG_LAN2E 0x00000400
|
|
+/* Not selected
|
|
+#define SYS_GPE_SSCFG_LAN2E_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SSCFG_LAN2E_SEL 0x00000400
|
|
+/** Sleep/Wakeup Source LAN1E
|
|
+ Selects the FIFO empty signal of the EGRESS FIFO of port LAN1 as sleep/wakeup source. */
|
|
+#define SYS_GPE_SSCFG_LAN1E 0x00000200
|
|
+/* Not selected
|
|
+#define SYS_GPE_SSCFG_LAN1E_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SSCFG_LAN1E_SEL 0x00000200
|
|
+/** Sleep/Wakeup Source LAN0E
|
|
+ Selects the FIFO empty signal of the EGRESS FIFO of port LAN0 as sleep/wakeup source. */
|
|
+#define SYS_GPE_SSCFG_LAN0E 0x00000100
|
|
+/* Not selected
|
|
+#define SYS_GPE_SSCFG_LAN0E_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SSCFG_LAN0E_SEL 0x00000100
|
|
+/** Sleep/Wakeup Source GPONI
|
|
+ Selects the FIFO empty signal of the INGRESS FIFO of port GPON as sleep/wakeup source. */
|
|
+#define SYS_GPE_SSCFG_GPONI 0x00000010
|
|
+/* Not selected
|
|
+#define SYS_GPE_SSCFG_GPONI_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SSCFG_GPONI_SEL 0x00000010
|
|
+/** Sleep/Wakeup Source LAN3I
|
|
+ Selects the FIFO empty signal of the INGRESS FIFO of port LAN3 as sleep/wakeup source. */
|
|
+#define SYS_GPE_SSCFG_LAN3I 0x00000008
|
|
+/* Not selected
|
|
+#define SYS_GPE_SSCFG_LAN3I_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SSCFG_LAN3I_SEL 0x00000008
|
|
+/** Sleep/Wakeup Source LAN2I
|
|
+ Selects the FIFO empty signal of the INGRESS FIFO of port LAN2 as sleep/wakeup source. */
|
|
+#define SYS_GPE_SSCFG_LAN2I 0x00000004
|
|
+/* Not selected
|
|
+#define SYS_GPE_SSCFG_LAN2I_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SSCFG_LAN2I_SEL 0x00000004
|
|
+/** Sleep/Wakeup Source LAN1I
|
|
+ Selects the FIFO empty signal of the INGRESS FIFO of port LAN1 as sleep/wakeup source. */
|
|
+#define SYS_GPE_SSCFG_LAN1I 0x00000002
|
|
+/* Not selected
|
|
+#define SYS_GPE_SSCFG_LAN1I_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SSCFG_LAN1I_SEL 0x00000002
|
|
+/** Sleep/Wakeup Source LAN0I
|
|
+ Selects the FIFO empty signal of the INGRESS FIFO of port LAN0 as sleep/wakeup source. */
|
|
+#define SYS_GPE_SSCFG_LAN0I 0x00000001
|
|
+/* Not selected
|
|
+#define SYS_GPE_SSCFG_LAN0I_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SSCFG_LAN0I_SEL 0x00000001
|
|
+
|
|
+/* Fields of "Sleep Source Timer Register" */
|
|
+/** Sleep Delay Value
|
|
+ A HW sleep request is delayed by this value multiplied by 3.2ns before it takes effect. A wakeup request is not delayed but takes effect immediately. Values lower than 256 are limited to 256. */
|
|
+#define SYS_GPE_SST_SDV_MASK 0x7FFFFFFF
|
|
+/** field offset */
|
|
+#define SYS_GPE_SST_SDV_OFFSET 0
|
|
+
|
|
+/* Fields of "Sleep Destination Status Register" */
|
|
+/** Shutoff COP7 on HW Sleep
|
|
+ If selected the domain COP7 is shutoff on a hardware sleep request. This domain contains the Coprocessor 7 of the SCE. */
|
|
+#define SYS_GPE_SDS_COP7 0x80000000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_COP7_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_COP7_SEL 0x80000000
|
|
+/** Shutoff COP6 on HW Sleep
|
|
+ If selected the domain COP6 is shutoff on a hardware sleep request. This domain contains the Coprocessor 6 of the SCE. */
|
|
+#define SYS_GPE_SDS_COP6 0x40000000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_COP6_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_COP6_SEL 0x40000000
|
|
+/** Shutoff COP5 on HW Sleep
|
|
+ If selected the domain COP5 is shutoff on a hardware sleep request. This domain contains the Coprocessor 5 of the SCE. */
|
|
+#define SYS_GPE_SDS_COP5 0x20000000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_COP5_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_COP5_SEL 0x20000000
|
|
+/** Shutoff COP4 on HW Sleep
|
|
+ If selected the domain COP4 is shutoff on a hardware sleep request. This domain contains the Coprocessor 4 of the SCE. */
|
|
+#define SYS_GPE_SDS_COP4 0x10000000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_COP4_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_COP4_SEL 0x10000000
|
|
+/** Shutoff COP3 on HW Sleep
|
|
+ If selected the domain COP3 is shutoff on a hardware sleep request. This domain contains the Coprocessor 3 of the SCE. */
|
|
+#define SYS_GPE_SDS_COP3 0x08000000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_COP3_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_COP3_SEL 0x08000000
|
|
+/** Shutoff COP2 on HW Sleep
|
|
+ If selected the domain COP2 is shutoff on a hardware sleep request. This domain contains the Coprocessor 2 of the SCE. */
|
|
+#define SYS_GPE_SDS_COP2 0x04000000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_COP2_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_COP2_SEL 0x04000000
|
|
+/** Shutoff COP1 on HW Sleep
|
|
+ If selected the domain COP1 is shutoff on a hardware sleep request. This domain contains the Coprocessor 1 of the SCE. */
|
|
+#define SYS_GPE_SDS_COP1 0x02000000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_COP1_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_COP1_SEL 0x02000000
|
|
+/** Shutoff COP0 on HW Sleep
|
|
+ If selected the domain COP0 is shutoff on a hardware sleep request. This domain contains the Coprocessor 0 of the SCE. */
|
|
+#define SYS_GPE_SDS_COP0 0x01000000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_COP0_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_COP0_SEL 0x01000000
|
|
+/** Shutoff PE5 on HW Sleep
|
|
+ If selected the domain PE5 is shutoff on a hardware sleep request. This domain contains the Processing Element 5 of the SCE. */
|
|
+#define SYS_GPE_SDS_PE5 0x00200000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_PE5_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_PE5_SEL 0x00200000
|
|
+/** Shutoff PE4 on HW Sleep
|
|
+ If selected the domain PE4 is shutoff on a hardware sleep request. This domain contains the Processing Element 4 of the SCE. */
|
|
+#define SYS_GPE_SDS_PE4 0x00100000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_PE4_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_PE4_SEL 0x00100000
|
|
+/** Shutoff PE3 on HW Sleep
|
|
+ If selected the domain PE3 is shutoff on a hardware sleep request. This domain contains the Processing Element 3 of the SCE. */
|
|
+#define SYS_GPE_SDS_PE3 0x00080000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_PE3_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_PE3_SEL 0x00080000
|
|
+/** Shutoff PE2 on HW Sleep
|
|
+ If selected the domain PE2 is shutoff on a hardware sleep request. This domain contains the Processing Element 2 of the SCE. */
|
|
+#define SYS_GPE_SDS_PE2 0x00040000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_PE2_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_PE2_SEL 0x00040000
|
|
+/** Shutoff PE1 on HW Sleep
|
|
+ If selected the domain PE1 is shutoff on a hardware sleep request. This domain contains the Processing Element 1 of the SCE. */
|
|
+#define SYS_GPE_SDS_PE1 0x00020000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_PE1_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_PE1_SEL 0x00020000
|
|
+/** Shutoff PE0 on HW Sleep
|
|
+ If selected the domain PE0 is shutoff on a hardware sleep request. This domain contains the Processing Element 0 of the SCE. */
|
|
+#define SYS_GPE_SDS_PE0 0x00010000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_PE0_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_PE0_SEL 0x00010000
|
|
+/** Shutoff ARB on HW Sleep
|
|
+ If selected the domain ARB is shutoff on a hardware sleep request. This domain contains the Arbiter. */
|
|
+#define SYS_GPE_SDS_ARB 0x00002000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_ARB_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_ARB_SEL 0x00002000
|
|
+/** Shutoff FSQM on HW Sleep
|
|
+ If selected the domain FSQM is shutoff on a hardware sleep request. This domain contains the FSQM. */
|
|
+#define SYS_GPE_SDS_FSQM 0x00001000
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_FSQM_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_FSQM_SEL 0x00001000
|
|
+/** Shutoff TMU on HW Sleep
|
|
+ If selected the domain TMU is shutoff on a hardware sleep request. This domain contains the TMU. */
|
|
+#define SYS_GPE_SDS_TMU 0x00000800
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_TMU_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_TMU_SEL 0x00000800
|
|
+/** Shutoff MRG on HW Sleep
|
|
+ If selected the domain MRG is shutoff on a hardware sleep request. This domain contains the Merger. */
|
|
+#define SYS_GPE_SDS_MRG 0x00000400
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_MRG_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_MRG_SEL 0x00000400
|
|
+/** Shutoff DISP on HW Sleep
|
|
+ If selected the domain DISP is shutoff on a hardware sleep request. This domain contains the Dispatcher. */
|
|
+#define SYS_GPE_SDS_DISP 0x00000200
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_DISP_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_DISP_SEL 0x00000200
|
|
+/** Shutoff IQM on HW Sleep
|
|
+ If selected the domain IQM is shutoff on a hardware sleep request. This domain contains the IQM. */
|
|
+#define SYS_GPE_SDS_IQM 0x00000100
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_IQM_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_IQM_SEL 0x00000100
|
|
+/** Shutoff CPUE on HW Sleep
|
|
+ If selected the domain CPUE is shutoff on a hardware sleep request. This domain contains all parts related to the CPU EGRESS interface. */
|
|
+#define SYS_GPE_SDS_CPUE 0x00000080
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_CPUE_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_CPUE_SEL 0x00000080
|
|
+/** Shutoff CPUI on HW Sleep
|
|
+ If selected the domain CPUI is shutoff on a hardware sleep request. This domain contains all parts related to the CPU INGRESS interface. */
|
|
+#define SYS_GPE_SDS_CPUI 0x00000040
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_CPUI_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_CPUI_SEL 0x00000040
|
|
+/** Shutoff GPONE on HW Sleep
|
|
+ If selected the domain GPONE is shutoff on a hardware sleep request. This domain contains all parts related to the GPON (GTC) EGRESS interface. */
|
|
+#define SYS_GPE_SDS_GPONE 0x00000020
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_GPONE_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_GPONE_SEL 0x00000020
|
|
+/** Shutoff GPONI on HW Sleep
|
|
+ If selected the domain GPONI is shutoff on a hardware sleep request. This domain contains all parts related to the GPON (GTC) INGRESS interface. */
|
|
+#define SYS_GPE_SDS_GPONI 0x00000010
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_GPONI_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_GPONI_SEL 0x00000010
|
|
+/** Shutoff LAN3 on HW Sleep
|
|
+ If selected the domain LAN3 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN3 interface. */
|
|
+#define SYS_GPE_SDS_LAN3 0x00000008
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_LAN3_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_LAN3_SEL 0x00000008
|
|
+/** Shutoff LAN2 on HW Sleep
|
|
+ If selected the domain LAN2 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN2 interface. */
|
|
+#define SYS_GPE_SDS_LAN2 0x00000004
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_LAN2_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_LAN2_SEL 0x00000004
|
|
+/** Shutoff LAN1 on HW Sleep
|
|
+ If selected the domain LAN1 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN1 interface. */
|
|
+#define SYS_GPE_SDS_LAN1 0x00000002
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_LAN1_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_LAN1_SEL 0x00000002
|
|
+/** Shutoff LAN0 on HW Sleep
|
|
+ If selected the domain LAN0 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN0 interface. */
|
|
+#define SYS_GPE_SDS_LAN0 0x00000001
|
|
+/* Not selected
|
|
+#define SYS_GPE_SDS_LAN0_NSEL 0x00000000 */
|
|
+/** Selected */
|
|
+#define SYS_GPE_SDS_LAN0_SEL 0x00000001
|
|
+
|
|
+/* Fields of "Sleep Destination Set Register" */
|
|
+/** Set Sleep Selection COP7
|
|
+ Sets the selection bit for domain COP7This domain contains the Coprocessor 7 of the SCE. */
|
|
+#define SYS_GPE_SDSET_COP7 0x80000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_COP7_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_COP7_SET 0x80000000
|
|
+/** Set Sleep Selection COP6
|
|
+ Sets the selection bit for domain COP6This domain contains the Coprocessor 6 of the SCE. */
|
|
+#define SYS_GPE_SDSET_COP6 0x40000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_COP6_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_COP6_SET 0x40000000
|
|
+/** Set Sleep Selection COP5
|
|
+ Sets the selection bit for domain COP5This domain contains the Coprocessor 5 of the SCE. */
|
|
+#define SYS_GPE_SDSET_COP5 0x20000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_COP5_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_COP5_SET 0x20000000
|
|
+/** Set Sleep Selection COP4
|
|
+ Sets the selection bit for domain COP4This domain contains the Coprocessor 4 of the SCE. */
|
|
+#define SYS_GPE_SDSET_COP4 0x10000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_COP4_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_COP4_SET 0x10000000
|
|
+/** Set Sleep Selection COP3
|
|
+ Sets the selection bit for domain COP3This domain contains the Coprocessor 3 of the SCE. */
|
|
+#define SYS_GPE_SDSET_COP3 0x08000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_COP3_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_COP3_SET 0x08000000
|
|
+/** Set Sleep Selection COP2
|
|
+ Sets the selection bit for domain COP2This domain contains the Coprocessor 2 of the SCE. */
|
|
+#define SYS_GPE_SDSET_COP2 0x04000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_COP2_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_COP2_SET 0x04000000
|
|
+/** Set Sleep Selection COP1
|
|
+ Sets the selection bit for domain COP1This domain contains the Coprocessor 1 of the SCE. */
|
|
+#define SYS_GPE_SDSET_COP1 0x02000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_COP1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_COP1_SET 0x02000000
|
|
+/** Set Sleep Selection COP0
|
|
+ Sets the selection bit for domain COP0This domain contains the Coprocessor 0 of the SCE. */
|
|
+#define SYS_GPE_SDSET_COP0 0x01000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_COP0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_COP0_SET 0x01000000
|
|
+/** Set Sleep Selection PE5
|
|
+ Sets the selection bit for domain PE5This domain contains the Processing Element 5 of the SCE. */
|
|
+#define SYS_GPE_SDSET_PE5 0x00200000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_PE5_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_PE5_SET 0x00200000
|
|
+/** Set Sleep Selection PE4
|
|
+ Sets the selection bit for domain PE4This domain contains the Processing Element 4 of the SCE. */
|
|
+#define SYS_GPE_SDSET_PE4 0x00100000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_PE4_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_PE4_SET 0x00100000
|
|
+/** Set Sleep Selection PE3
|
|
+ Sets the selection bit for domain PE3This domain contains the Processing Element 3 of the SCE. */
|
|
+#define SYS_GPE_SDSET_PE3 0x00080000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_PE3_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_PE3_SET 0x00080000
|
|
+/** Set Sleep Selection PE2
|
|
+ Sets the selection bit for domain PE2This domain contains the Processing Element 2 of the SCE. */
|
|
+#define SYS_GPE_SDSET_PE2 0x00040000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_PE2_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_PE2_SET 0x00040000
|
|
+/** Set Sleep Selection PE1
|
|
+ Sets the selection bit for domain PE1This domain contains the Processing Element 1 of the SCE. */
|
|
+#define SYS_GPE_SDSET_PE1 0x00020000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_PE1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_PE1_SET 0x00020000
|
|
+/** Set Sleep Selection PE0
|
|
+ Sets the selection bit for domain PE0This domain contains the Processing Element 0 of the SCE. */
|
|
+#define SYS_GPE_SDSET_PE0 0x00010000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_PE0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_PE0_SET 0x00010000
|
|
+/** Set Sleep Selection ARB
|
|
+ Sets the selection bit for domain ARBThis domain contains the Arbiter. */
|
|
+#define SYS_GPE_SDSET_ARB 0x00002000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_ARB_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_ARB_SET 0x00002000
|
|
+/** Set Sleep Selection FSQM
|
|
+ Sets the selection bit for domain FSQMThis domain contains the FSQM. */
|
|
+#define SYS_GPE_SDSET_FSQM 0x00001000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_FSQM_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_FSQM_SET 0x00001000
|
|
+/** Set Sleep Selection TMU
|
|
+ Sets the selection bit for domain TMUThis domain contains the TMU. */
|
|
+#define SYS_GPE_SDSET_TMU 0x00000800
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_TMU_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_TMU_SET 0x00000800
|
|
+/** Set Sleep Selection MRG
|
|
+ Sets the selection bit for domain MRGThis domain contains the Merger. */
|
|
+#define SYS_GPE_SDSET_MRG 0x00000400
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_MRG_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_MRG_SET 0x00000400
|
|
+/** Set Sleep Selection DISP
|
|
+ Sets the selection bit for domain DISPThis domain contains the Dispatcher. */
|
|
+#define SYS_GPE_SDSET_DISP 0x00000200
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_DISP_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_DISP_SET 0x00000200
|
|
+/** Set Sleep Selection IQM
|
|
+ Sets the selection bit for domain IQMThis domain contains the IQM. */
|
|
+#define SYS_GPE_SDSET_IQM 0x00000100
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_IQM_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_IQM_SET 0x00000100
|
|
+/** Set Sleep Selection CPUE
|
|
+ Sets the selection bit for domain CPUEThis domain contains all parts related to the CPU EGRESS interface. */
|
|
+#define SYS_GPE_SDSET_CPUE 0x00000080
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_CPUE_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_CPUE_SET 0x00000080
|
|
+/** Set Sleep Selection CPUI
|
|
+ Sets the selection bit for domain CPUIThis domain contains all parts related to the CPU INGRESS interface. */
|
|
+#define SYS_GPE_SDSET_CPUI 0x00000040
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_CPUI_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_CPUI_SET 0x00000040
|
|
+/** Set Sleep Selection GPONE
|
|
+ Sets the selection bit for domain GPONEThis domain contains all parts related to the GPON (GTC) EGRESS interface. */
|
|
+#define SYS_GPE_SDSET_GPONE 0x00000020
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_GPONE_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_GPONE_SET 0x00000020
|
|
+/** Set Sleep Selection GPONI
|
|
+ Sets the selection bit for domain GPONIThis domain contains all parts related to the GPON (GTC) INGRESS interface. */
|
|
+#define SYS_GPE_SDSET_GPONI 0x00000010
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_GPONI_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_GPONI_SET 0x00000010
|
|
+/** Set Sleep Selection LAN3
|
|
+ Sets the selection bit for domain LAN3This domain contains all parts related to the LAN3 interface. */
|
|
+#define SYS_GPE_SDSET_LAN3 0x00000008
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_LAN3_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_LAN3_SET 0x00000008
|
|
+/** Set Sleep Selection LAN2
|
|
+ Sets the selection bit for domain LAN2This domain contains all parts related to the LAN2 interface. */
|
|
+#define SYS_GPE_SDSET_LAN2 0x00000004
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_LAN2_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_LAN2_SET 0x00000004
|
|
+/** Set Sleep Selection LAN1
|
|
+ Sets the selection bit for domain LAN1This domain contains all parts related to the LAN1 interface. */
|
|
+#define SYS_GPE_SDSET_LAN1 0x00000002
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_LAN1_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_LAN1_SET 0x00000002
|
|
+/** Set Sleep Selection LAN0
|
|
+ Sets the selection bit for domain LAN0This domain contains all parts related to the LAN0 interface. */
|
|
+#define SYS_GPE_SDSET_LAN0 0x00000001
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDSET_LAN0_NOP 0x00000000 */
|
|
+/** Set */
|
|
+#define SYS_GPE_SDSET_LAN0_SET 0x00000001
|
|
+
|
|
+/* Fields of "Sleep Destination Clear Register" */
|
|
+/** Clear Sleep Selection COP7
|
|
+ Clears the selection bit for domain COP7This domain contains the Coprocessor 7 of the SCE. */
|
|
+#define SYS_GPE_SDCLR_COP7 0x80000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_COP7_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_COP7_CLR 0x80000000
|
|
+/** Clear Sleep Selection COP6
|
|
+ Clears the selection bit for domain COP6This domain contains the Coprocessor 6 of the SCE. */
|
|
+#define SYS_GPE_SDCLR_COP6 0x40000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_COP6_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_COP6_CLR 0x40000000
|
|
+/** Clear Sleep Selection COP5
|
|
+ Clears the selection bit for domain COP5This domain contains the Coprocessor 5 of the SCE. */
|
|
+#define SYS_GPE_SDCLR_COP5 0x20000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_COP5_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_COP5_CLR 0x20000000
|
|
+/** Clear Sleep Selection COP4
|
|
+ Clears the selection bit for domain COP4This domain contains the Coprocessor 4 of the SCE. */
|
|
+#define SYS_GPE_SDCLR_COP4 0x10000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_COP4_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_COP4_CLR 0x10000000
|
|
+/** Clear Sleep Selection COP3
|
|
+ Clears the selection bit for domain COP3This domain contains the Coprocessor 3 of the SCE. */
|
|
+#define SYS_GPE_SDCLR_COP3 0x08000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_COP3_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_COP3_CLR 0x08000000
|
|
+/** Clear Sleep Selection COP2
|
|
+ Clears the selection bit for domain COP2This domain contains the Coprocessor 2 of the SCE. */
|
|
+#define SYS_GPE_SDCLR_COP2 0x04000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_COP2_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_COP2_CLR 0x04000000
|
|
+/** Clear Sleep Selection COP1
|
|
+ Clears the selection bit for domain COP1This domain contains the Coprocessor 1 of the SCE. */
|
|
+#define SYS_GPE_SDCLR_COP1 0x02000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_COP1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_COP1_CLR 0x02000000
|
|
+/** Clear Sleep Selection COP0
|
|
+ Clears the selection bit for domain COP0This domain contains the Coprocessor 0 of the SCE. */
|
|
+#define SYS_GPE_SDCLR_COP0 0x01000000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_COP0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_COP0_CLR 0x01000000
|
|
+/** Clear Sleep Selection PE5
|
|
+ Clears the selection bit for domain PE5This domain contains the Processing Element 5 of the SCE. */
|
|
+#define SYS_GPE_SDCLR_PE5 0x00200000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_PE5_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_PE5_CLR 0x00200000
|
|
+/** Clear Sleep Selection PE4
|
|
+ Clears the selection bit for domain PE4This domain contains the Processing Element 4 of the SCE. */
|
|
+#define SYS_GPE_SDCLR_PE4 0x00100000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_PE4_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_PE4_CLR 0x00100000
|
|
+/** Clear Sleep Selection PE3
|
|
+ Clears the selection bit for domain PE3This domain contains the Processing Element 3 of the SCE. */
|
|
+#define SYS_GPE_SDCLR_PE3 0x00080000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_PE3_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_PE3_CLR 0x00080000
|
|
+/** Clear Sleep Selection PE2
|
|
+ Clears the selection bit for domain PE2This domain contains the Processing Element 2 of the SCE. */
|
|
+#define SYS_GPE_SDCLR_PE2 0x00040000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_PE2_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_PE2_CLR 0x00040000
|
|
+/** Clear Sleep Selection PE1
|
|
+ Clears the selection bit for domain PE1This domain contains the Processing Element 1 of the SCE. */
|
|
+#define SYS_GPE_SDCLR_PE1 0x00020000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_PE1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_PE1_CLR 0x00020000
|
|
+/** Clear Sleep Selection PE0
|
|
+ Clears the selection bit for domain PE0This domain contains the Processing Element 0 of the SCE. */
|
|
+#define SYS_GPE_SDCLR_PE0 0x00010000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_PE0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_PE0_CLR 0x00010000
|
|
+/** Clear Sleep Selection ARB
|
|
+ Clears the selection bit for domain ARBThis domain contains the Arbiter. */
|
|
+#define SYS_GPE_SDCLR_ARB 0x00002000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_ARB_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_ARB_CLR 0x00002000
|
|
+/** Clear Sleep Selection FSQM
|
|
+ Clears the selection bit for domain FSQMThis domain contains the FSQM. */
|
|
+#define SYS_GPE_SDCLR_FSQM 0x00001000
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_FSQM_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_FSQM_CLR 0x00001000
|
|
+/** Clear Sleep Selection TMU
|
|
+ Clears the selection bit for domain TMUThis domain contains the TMU. */
|
|
+#define SYS_GPE_SDCLR_TMU 0x00000800
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_TMU_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_TMU_CLR 0x00000800
|
|
+/** Clear Sleep Selection MRG
|
|
+ Clears the selection bit for domain MRGThis domain contains the Merger. */
|
|
+#define SYS_GPE_SDCLR_MRG 0x00000400
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_MRG_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_MRG_CLR 0x00000400
|
|
+/** Clear Sleep Selection DISP
|
|
+ Clears the selection bit for domain DISPThis domain contains the Dispatcher. */
|
|
+#define SYS_GPE_SDCLR_DISP 0x00000200
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_DISP_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_DISP_CLR 0x00000200
|
|
+/** Clear Sleep Selection IQM
|
|
+ Clears the selection bit for domain IQMThis domain contains the IQM. */
|
|
+#define SYS_GPE_SDCLR_IQM 0x00000100
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_IQM_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_IQM_CLR 0x00000100
|
|
+/** Clear Sleep Selection CPUE
|
|
+ Clears the selection bit for domain CPUEThis domain contains all parts related to the CPU EGRESS interface. */
|
|
+#define SYS_GPE_SDCLR_CPUE 0x00000080
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_CPUE_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_CPUE_CLR 0x00000080
|
|
+/** Clear Sleep Selection CPUI
|
|
+ Clears the selection bit for domain CPUIThis domain contains all parts related to the CPU INGRESS interface. */
|
|
+#define SYS_GPE_SDCLR_CPUI 0x00000040
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_CPUI_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_CPUI_CLR 0x00000040
|
|
+/** Clear Sleep Selection GPONE
|
|
+ Clears the selection bit for domain GPONEThis domain contains all parts related to the GPON (GTC) EGRESS interface. */
|
|
+#define SYS_GPE_SDCLR_GPONE 0x00000020
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_GPONE_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_GPONE_CLR 0x00000020
|
|
+/** Clear Sleep Selection GPONI
|
|
+ Clears the selection bit for domain GPONIThis domain contains all parts related to the GPON (GTC) INGRESS interface. */
|
|
+#define SYS_GPE_SDCLR_GPONI 0x00000010
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_GPONI_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_GPONI_CLR 0x00000010
|
|
+/** Clear Sleep Selection LAN3
|
|
+ Clears the selection bit for domain LAN3This domain contains all parts related to the LAN3 interface. */
|
|
+#define SYS_GPE_SDCLR_LAN3 0x00000008
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_LAN3_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_LAN3_CLR 0x00000008
|
|
+/** Clear Sleep Selection LAN2
|
|
+ Clears the selection bit for domain LAN2This domain contains all parts related to the LAN2 interface. */
|
|
+#define SYS_GPE_SDCLR_LAN2 0x00000004
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_LAN2_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_LAN2_CLR 0x00000004
|
|
+/** Clear Sleep Selection LAN1
|
|
+ Clears the selection bit for domain LAN1This domain contains all parts related to the LAN1 interface. */
|
|
+#define SYS_GPE_SDCLR_LAN1 0x00000002
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_LAN1_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_LAN1_CLR 0x00000002
|
|
+/** Clear Sleep Selection LAN0
|
|
+ Clears the selection bit for domain LAN0This domain contains all parts related to the LAN0 interface. */
|
|
+#define SYS_GPE_SDCLR_LAN0 0x00000001
|
|
+/* No-Operation
|
|
+#define SYS_GPE_SDCLR_LAN0_NOP 0x00000000 */
|
|
+/** Clear */
|
|
+#define SYS_GPE_SDCLR_LAN0_CLR 0x00000001
|
|
+
|
|
+/* Fields of "IRNCS Capture Register" */
|
|
+/** FSQM wakeup request
|
|
+ The FSQM submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_FSQMWR 0x80000000
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_FSQMWR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_FSQMWR_INTACK 0x80000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_FSQMWR_INTOCC 0x80000000
|
|
+/** GPONT wakeup request
|
|
+ The TCONT Request FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_GPONTWR 0x20000000
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_GPONTWR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_GPONTWR_INTACK 0x20000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_GPONTWR_INTOCC 0x20000000
|
|
+/** GPONE wakeup request
|
|
+ The EGRESS FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_GPONEWR 0x10000000
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_GPONEWR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_GPONEWR_INTACK 0x10000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_GPONEWR_INTOCC 0x10000000
|
|
+/** LAN3E wakeup request
|
|
+ The EGRESS FIFO of port LAN3 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN3EWR 0x08000000
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_LAN3EWR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN3EWR_INTACK 0x08000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_LAN3EWR_INTOCC 0x08000000
|
|
+/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request.
|
|
+ This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN2EWR 0x04000000
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_LAN2EWR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN2EWR_INTACK 0x04000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_LAN2EWR_INTOCC 0x04000000
|
|
+/** LAN1E wakeup request
|
|
+ The EGRESS FIFO of port LAN1 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN1EWR 0x02000000
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_LAN1EWR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN1EWR_INTACK 0x02000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_LAN1EWR_INTOCC 0x02000000
|
|
+/** LAN0E wakeup request
|
|
+ The EGRESS FIFO of port LAN0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN0EWR 0x01000000
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_LAN0EWR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN0EWR_INTACK 0x01000000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_LAN0EWR_INTOCC 0x01000000
|
|
+/** GPONI wakeup request
|
|
+ The INGRESS FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_GPONIWR 0x00100000
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_GPONIWR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_GPONIWR_INTACK 0x00100000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_GPONIWR_INTOCC 0x00100000
|
|
+/** LAN3I wakeup request
|
|
+ The INGRESS FIFO of port LAN3 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN3IWR 0x00080000
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_LAN3IWR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN3IWR_INTACK 0x00080000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_LAN3IWR_INTOCC 0x00080000
|
|
+/** LAN2I wakeup request
|
|
+ The INGRESS FIFO of port LAN2 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN2IWR 0x00040000
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_LAN2IWR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN2IWR_INTACK 0x00040000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_LAN2IWR_INTOCC 0x00040000
|
|
+/** LAN1I wakeup request
|
|
+ The INGRESS FIFO of port LAN1 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN1IWR 0x00020000
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_LAN1IWR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN1IWR_INTACK 0x00020000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_LAN1IWR_INTOCC 0x00020000
|
|
+/** LAN0I wakeup request
|
|
+ The INGRESS FIFO of port LAN0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN0IWR 0x00010000
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_LAN0IWR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN0IWR_INTACK 0x00010000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_LAN0IWR_INTOCC 0x00010000
|
|
+/** FSQM sleep request
|
|
+ The FSQM submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_FSQMSR 0x00008000
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_FSQMSR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_FSQMSR_INTACK 0x00008000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_FSQMSR_INTOCC 0x00008000
|
|
+/** GPONT sleep request
|
|
+ The TCONT Request FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_GPONTSR 0x00002000
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_GPONTSR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_GPONTSR_INTACK 0x00002000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_GPONTSR_INTOCC 0x00002000
|
|
+/** GPONE sleep request
|
|
+ The EGRESS FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_GPONESR 0x00001000
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_GPONESR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_GPONESR_INTACK 0x00001000
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_GPONESR_INTOCC 0x00001000
|
|
+/** LAN3E sleep request
|
|
+ The EGRESS FIFO of port LAN3 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN3ESR 0x00000800
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_LAN3ESR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN3ESR_INTACK 0x00000800
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_LAN3ESR_INTOCC 0x00000800
|
|
+/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request.
|
|
+ This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN2ESR 0x00000400
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_LAN2ESR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN2ESR_INTACK 0x00000400
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_LAN2ESR_INTOCC 0x00000400
|
|
+/** LAN1E sleep request
|
|
+ The EGRESS FIFO of port LAN1 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN1ESR 0x00000200
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_LAN1ESR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN1ESR_INTACK 0x00000200
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_LAN1ESR_INTOCC 0x00000200
|
|
+/** LAN0E sleep request
|
|
+ The EGRESS FIFO of port LAN0 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN0ESR 0x00000100
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_LAN0ESR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN0ESR_INTACK 0x00000100
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_LAN0ESR_INTOCC 0x00000100
|
|
+/** GPONI sleep request
|
|
+ The INGRESS FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_GPONISR 0x00000010
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_GPONISR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_GPONISR_INTACK 0x00000010
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_GPONISR_INTOCC 0x00000010
|
|
+/** LAN3I sleep request
|
|
+ The INGRESS FIFO of port LAN3 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN3ISR 0x00000008
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_LAN3ISR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN3ISR_INTACK 0x00000008
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_LAN3ISR_INTOCC 0x00000008
|
|
+/** LAN2I sleep request
|
|
+ The INGRESS FIFO of port LAN2 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN2ISR 0x00000004
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_LAN2ISR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN2ISR_INTACK 0x00000004
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_LAN2ISR_INTOCC 0x00000004
|
|
+/** LAN1I sleep request
|
|
+ The INGRESS FIFO of port LAN1 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN1ISR 0x00000002
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_LAN1ISR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN1ISR_INTACK 0x00000002
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_LAN1ISR_INTOCC 0x00000002
|
|
+/** LAN0I sleep request
|
|
+ The INGRESS FIFO of port LAN0 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN0ISR 0x00000001
|
|
+/* Nothing
|
|
+#define SYS_GPE_IRNCSCR_LAN0ISR_NULL 0x00000000 */
|
|
+/** Write: Acknowledge the interrupt. */
|
|
+#define SYS_GPE_IRNCSCR_LAN0ISR_INTACK 0x00000001
|
|
+/** Read: Interrupt occurred. */
|
|
+#define SYS_GPE_IRNCSCR_LAN0ISR_INTOCC 0x00000001
|
|
+
|
|
+/* Fields of "IRNCS Interrupt Control Register" */
|
|
+/** FSQM wakeup request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_FSQMWR 0x80000000
|
|
+/** GPONT wakeup request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_GPONTWR 0x20000000
|
|
+/** GPONE wakeup request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_GPONEWR 0x10000000
|
|
+/** LAN3E wakeup request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_LAN3EWR 0x08000000
|
|
+/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request.
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_LAN2EWR 0x04000000
|
|
+/** LAN1E wakeup request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_LAN1EWR 0x02000000
|
|
+/** LAN0E wakeup request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_LAN0EWR 0x01000000
|
|
+/** GPONI wakeup request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_GPONIWR 0x00100000
|
|
+/** LAN3I wakeup request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_LAN3IWR 0x00080000
|
|
+/** LAN2I wakeup request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_LAN2IWR 0x00040000
|
|
+/** LAN1I wakeup request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_LAN1IWR 0x00020000
|
|
+/** LAN0I wakeup request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_LAN0IWR 0x00010000
|
|
+/** FSQM sleep request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_FSQMSR 0x00008000
|
|
+/** GPONT sleep request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_GPONTSR 0x00002000
|
|
+/** GPONE sleep request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_GPONESR 0x00001000
|
|
+/** LAN3E sleep request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_LAN3ESR 0x00000800
|
|
+/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request.
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_LAN2ESR 0x00000400
|
|
+/** LAN1E sleep request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_LAN1ESR 0x00000200
|
|
+/** LAN0E sleep request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_LAN0ESR 0x00000100
|
|
+/** GPONI sleep request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_GPONISR 0x00000010
|
|
+/** LAN3I sleep request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_LAN3ISR 0x00000008
|
|
+/** LAN2I sleep request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_LAN2ISR 0x00000004
|
|
+/** LAN1I sleep request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_LAN1ISR 0x00000002
|
|
+/** LAN0I sleep request
|
|
+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSICR_LAN0ISR 0x00000001
|
|
+
|
|
+/* Fields of "IRNCS Interrupt Enable Register" */
|
|
+/** FSQM wakeup request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_FSQMWR 0x80000000
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_FSQMWR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_FSQMWR_EN 0x80000000
|
|
+/** GPONT wakeup request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_GPONTWR 0x20000000
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_GPONTWR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_GPONTWR_EN 0x20000000
|
|
+/** GPONE wakeup request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_GPONEWR 0x10000000
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_GPONEWR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_GPONEWR_EN 0x10000000
|
|
+/** LAN3E wakeup request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_LAN3EWR 0x08000000
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_LAN3EWR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_LAN3EWR_EN 0x08000000
|
|
+/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request.
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_LAN2EWR 0x04000000
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_LAN2EWR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_LAN2EWR_EN 0x04000000
|
|
+/** LAN1E wakeup request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_LAN1EWR 0x02000000
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_LAN1EWR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_LAN1EWR_EN 0x02000000
|
|
+/** LAN0E wakeup request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_LAN0EWR 0x01000000
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_LAN0EWR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_LAN0EWR_EN 0x01000000
|
|
+/** GPONI wakeup request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_GPONIWR 0x00100000
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_GPONIWR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_GPONIWR_EN 0x00100000
|
|
+/** LAN3I wakeup request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_LAN3IWR 0x00080000
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_LAN3IWR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_LAN3IWR_EN 0x00080000
|
|
+/** LAN2I wakeup request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_LAN2IWR 0x00040000
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_LAN2IWR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_LAN2IWR_EN 0x00040000
|
|
+/** LAN1I wakeup request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_LAN1IWR 0x00020000
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_LAN1IWR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_LAN1IWR_EN 0x00020000
|
|
+/** LAN0I wakeup request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_LAN0IWR 0x00010000
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_LAN0IWR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_LAN0IWR_EN 0x00010000
|
|
+/** FSQM sleep request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_FSQMSR 0x00008000
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_FSQMSR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_FSQMSR_EN 0x00008000
|
|
+/** GPONT sleep request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_GPONTSR 0x00002000
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_GPONTSR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_GPONTSR_EN 0x00002000
|
|
+/** GPONE sleep request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_GPONESR 0x00001000
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_GPONESR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_GPONESR_EN 0x00001000
|
|
+/** LAN3E sleep request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_LAN3ESR 0x00000800
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_LAN3ESR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_LAN3ESR_EN 0x00000800
|
|
+/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request.
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_LAN2ESR 0x00000400
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_LAN2ESR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_LAN2ESR_EN 0x00000400
|
|
+/** LAN1E sleep request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_LAN1ESR 0x00000200
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_LAN1ESR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_LAN1ESR_EN 0x00000200
|
|
+/** LAN0E sleep request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_LAN0ESR 0x00000100
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_LAN0ESR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_LAN0ESR_EN 0x00000100
|
|
+/** GPONI sleep request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_GPONISR 0x00000010
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_GPONISR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_GPONISR_EN 0x00000010
|
|
+/** LAN3I sleep request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_LAN3ISR 0x00000008
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_LAN3ISR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_LAN3ISR_EN 0x00000008
|
|
+/** LAN2I sleep request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_LAN2ISR 0x00000004
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_LAN2ISR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_LAN2ISR_EN 0x00000004
|
|
+/** LAN1I sleep request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_LAN1ISR 0x00000002
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_LAN1ISR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_LAN1ISR_EN 0x00000002
|
|
+/** LAN0I sleep request
|
|
+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */
|
|
+#define SYS_GPE_IRNCSEN_LAN0ISR 0x00000001
|
|
+/* Disable
|
|
+#define SYS_GPE_IRNCSEN_LAN0ISR_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define SYS_GPE_IRNCSEN_LAN0ISR_EN 0x00000001
|
|
+
|
|
+/*! @} */ /* SYS_GPE_REGISTER */
|
|
+
|
|
+#endif /* _sys_gpe_reg_h */
|
|
--- /dev/null
|
|
+++ b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h
|
|
@@ -0,0 +1,58 @@
|
|
+/*
|
|
+ * Lantiq FALCON specific CPU feature overrides
|
|
+ *
|
|
+ * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
|
|
+ *
|
|
+ * This file was derived from: include/asm-mips/cpu-features.h
|
|
+ * Copyright (C) 2003, 2004 Ralf Baechle
|
|
+ * Copyright (C) 2004 Maciej W. Rozycki
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published
|
|
+ * by the Free Software Foundation.
|
|
+ *
|
|
+ */
|
|
+#ifndef __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
|
|
+#define __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H
|
|
+
|
|
+#define cpu_has_tlb 1
|
|
+#define cpu_has_4kex 1
|
|
+#define cpu_has_3k_cache 0
|
|
+#define cpu_has_4k_cache 1
|
|
+#define cpu_has_tx39_cache 0
|
|
+#define cpu_has_sb1_cache 0
|
|
+#define cpu_has_fpu 0
|
|
+#define cpu_has_32fpr 0
|
|
+#define cpu_has_counter 1
|
|
+#define cpu_has_watch 1
|
|
+#define cpu_has_divec 1
|
|
+
|
|
+#define cpu_has_prefetch 1
|
|
+#define cpu_has_ejtag 1
|
|
+#define cpu_has_llsc 1
|
|
+
|
|
+#define cpu_has_mips16 1
|
|
+#define cpu_has_mdmx 0
|
|
+#define cpu_has_mips3d 0
|
|
+#define cpu_has_smartmips 0
|
|
+
|
|
+#define cpu_has_mips32r1 1
|
|
+#define cpu_has_mips32r2 1
|
|
+#define cpu_has_mips64r1 0
|
|
+#define cpu_has_mips64r2 0
|
|
+
|
|
+#define cpu_has_dsp 1
|
|
+#define cpu_has_mipsmt 1
|
|
+
|
|
+#define cpu_has_vint 1
|
|
+#define cpu_has_veic 1
|
|
+
|
|
+#define cpu_has_64bits 0
|
|
+#define cpu_has_64bit_zero_reg 0
|
|
+#define cpu_has_64bit_gp_regs 0
|
|
+#define cpu_has_64bit_addresses 0
|
|
+
|
|
+#define cpu_dcache_line_size() 32
|
|
+#define cpu_icache_line_size() 32
|
|
+
|
|
+#endif /* __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H */
|
|
--- /dev/null
|
|
+++ b/arch/mips/include/asm/mach-lantiq/falcon/ebu_reg.h
|
|
@@ -0,0 +1,1520 @@
|
|
+/******************************************************************************
|
|
+
|
|
+ Copyright (c) 2010
|
|
+ Lantiq Deutschland GmbH
|
|
+
|
|
+ For licensing information, see the file 'LICENSE' in the root folder of
|
|
+ this software module.
|
|
+
|
|
+******************************************************************************/
|
|
+
|
|
+#ifndef _ebu_reg_h
|
|
+#define _ebu_reg_h
|
|
+
|
|
+/** \addtogroup EBU_REGISTER
|
|
+ @{
|
|
+*/
|
|
+/* access macros */
|
|
+#define ebu_r32(reg) reg_r32(&ebu->reg)
|
|
+#define ebu_w32(val, reg) reg_w32(val, &ebu->reg)
|
|
+#define ebu_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &ebu->reg)
|
|
+#define ebu_r32_table(reg, idx) reg_r32_table(ebu->reg, idx)
|
|
+#define ebu_w32_table(val, reg, idx) reg_w32_table(val, ebu->reg, idx)
|
|
+#define ebu_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, ebu->reg, idx)
|
|
+#define ebu_adr_table(reg, idx) adr_table(ebu->reg, idx)
|
|
+
|
|
+
|
|
+/** EBU register structure */
|
|
+struct gpon_reg_ebu
|
|
+{
|
|
+ /** Reserved */
|
|
+ unsigned int res_0[2]; /* 0x00000000 */
|
|
+ /** Module ID Register
|
|
+ Module type and version identifier */
|
|
+ unsigned int modid; /* 0x00000008 */
|
|
+ /** Module Control Register
|
|
+ This register contains general configuration information observed for all CS regions or dealing with EBU functionality that is not directly related to external memory access. */
|
|
+ unsigned int modcon; /* 0x0000000C */
|
|
+ /** Bus Read Configuration Register0
|
|
+ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */
|
|
+ unsigned int busrcon0; /* 0x00000010 */
|
|
+ /** Bus Read Parameters Register0 */
|
|
+ unsigned int busrp0; /* 0x00000014 */
|
|
+ /** Bus Write Configuration Register0
|
|
+ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */
|
|
+ unsigned int buswcon0; /* 0x00000018 */
|
|
+ /** Bus Write Parameters Register0 */
|
|
+ unsigned int buswp0; /* 0x0000001C */
|
|
+ /** Bus Read Configuration Register1
|
|
+ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */
|
|
+ unsigned int busrcon1; /* 0x00000020 */
|
|
+ /** Bus Read Parameters Register1 */
|
|
+ unsigned int busrp1; /* 0x00000024 */
|
|
+ /** Bus Write Configuration Register1
|
|
+ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */
|
|
+ unsigned int buswcon1; /* 0x00000028 */
|
|
+ /** Bus Write Parameters Register1 */
|
|
+ unsigned int buswp1; /* 0x0000002C */
|
|
+ /** Reserved */
|
|
+ unsigned int res_1[8]; /* 0x00000030 */
|
|
+ /** Bus Protocol Configuration Extension Register 0 */
|
|
+ unsigned int busconext0; /* 0x00000050 */
|
|
+ /** Bus Protocol Configuration Extension Register 1 */
|
|
+ unsigned int busconext1; /* 0x00000054 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_2[10]; /* 0x00000058 */
|
|
+ /** Serial Flash Configuration Register
|
|
+ The content of this register configures the EBU's Serial Flash protocol engine. */
|
|
+ unsigned int sfcon; /* 0x00000080 */
|
|
+ /** Serial Flash Timing Register
|
|
+ This register defines the signal timing for the Serial Flash Access. See Section 3.18.3 on page 112 for details. */
|
|
+ unsigned int sftime; /* 0x00000084 */
|
|
+ /** Serial Flash Status Register
|
|
+ This register holds status information on the Serial Flash device(s) attached and the EBU's Serial Flash protocol engine. */
|
|
+ unsigned int sfstat; /* 0x00000088 */
|
|
+ /** Serial Flash Command Register
|
|
+ When writing to this register's opcode field, a command is started in the EBU's Serial Flash controller. */
|
|
+ unsigned int sfcmd; /* 0x0000008C */
|
|
+ /** Serial Flash Address Register
|
|
+ This register holds the address to be sent (if any) with accesses to/from a Serial Flash started by writing to EBU_SFCMD (Indirect Access Mode, see Section 3.18.2.4.1 on page 103). */
|
|
+ unsigned int sfaddr; /* 0x00000090 */
|
|
+ /** Serial Flash Data Register
|
|
+ This register holds the data being transferred (if any) with accesses to/from a Serial Flash started by writing to EBU_SFCMD (Indirect Access Mode, see Section 4.18.2.4.1 on page 116). */
|
|
+ unsigned int sfdata; /* 0x00000094 */
|
|
+ /** Serial Flash I/O Control Register
|
|
+ This register provides additional configuration for controlling the IO pads of the Serial Flash interface. */
|
|
+ unsigned int sfio; /* 0x00000098 */
|
|
+ /** Reserved */
|
|
+ unsigned int res_3[25]; /* 0x0000009C */
|
|
+};
|
|
+
|
|
+
|
|
+/* Fields of "Module ID Register" */
|
|
+/** Feature Select
|
|
+ This field indicates the types of external devices/protocols supported by the GPON version of the EBU. */
|
|
+#define MODID_FSEL_MASK 0xE0000000
|
|
+/** field offset */
|
|
+#define MODID_FSEL_OFFSET 29
|
|
+/** Support for SRAM, NAND/NOR/OneNand Flash and Cellular RAM is implemented. */
|
|
+#define MODID_FSEL_SRAM_FLASH_CRAM 0x00000000
|
|
+/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM and SDR SDRAM is implemented. */
|
|
+#define MODID_FSEL_SRAM_FLASH_CRAM_SDR 0x20000000
|
|
+/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM and SDR/DDR SDRAM is implemented. */
|
|
+#define MODID_FSEL_SRAM_FLASH_CRAM_DDR 0x40000000
|
|
+/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM, SDR/DDR SDRAM 0nd LPDDR-Flash is implemented. */
|
|
+#define MODID_FSEL_SRAM_FLASH_CRAM_DDR_LPNVM 0x60000000
|
|
+/** Serial Flash Support
|
|
+ Indicates whether or not the support of Serial Flash devices is available. */
|
|
+#define MODID_SF 0x10000000
|
|
+/* Not Available
|
|
+#define MODID_SF_NAV 0x00000000 */
|
|
+/** Available */
|
|
+#define MODID_SF_AV 0x10000000
|
|
+/** AAD-mux Support
|
|
+ Indicates whether or not the GPON EBU supports AAD-mux protocol for Burst Flash and Cellular RAM. */
|
|
+#define MODID_AAD 0x08000000
|
|
+/* Not Available
|
|
+#define MODID_AAD_NAV 0x00000000 */
|
|
+/** Available */
|
|
+#define MODID_AAD_AV 0x08000000
|
|
+/** Indicates whether or not the GPON EBU implements a DLL which is e.g. used for 50% duty cycle external clock generation. Note that a DLL is always implemented if DDR-SDRAM support is selected. */
|
|
+#define MODID_DLL 0x04000000
|
|
+/* Not Available
|
|
+#define MODID_DLL_NAV 0x00000000 */
|
|
+/** Available */
|
|
+#define MODID_DLL_AV 0x04000000
|
|
+/** Pad Multiplexing Scheme */
|
|
+#define MODID_PMS_MASK 0x03000000
|
|
+/** field offset */
|
|
+#define MODID_PMS_OFFSET 24
|
|
+/** The EBU comprises of dedicated address pins A[EXTAW-1=:16]. */
|
|
+#define MODID_PMS_PMS_CLASSIC 0x00000000
|
|
+/** Revision
|
|
+ Revision Number */
|
|
+#define MODID_REV_MASK 0x000F0000
|
|
+/** field offset */
|
|
+#define MODID_REV_OFFSET 16
|
|
+/** Module ID
|
|
+ This field contains the EBU's unique peripheral ID. */
|
|
+#define MODID_ID_MASK 0x0000FF00
|
|
+/** field offset */
|
|
+#define MODID_ID_OFFSET 8
|
|
+/** Version
|
|
+ This field gives the EBU version number. */
|
|
+#define MODID_VERSION_MASK 0x000000FF
|
|
+/** field offset */
|
|
+#define MODID_VERSION_OFFSET 0
|
|
+
|
|
+/* Fields of "Module Control Register" */
|
|
+/** Reserved */
|
|
+#define MODCON_DLLUPDINT_MASK 0xC0000000
|
|
+/** field offset */
|
|
+#define MODCON_DLLUPDINT_OFFSET 30
|
|
+/** Access Inhibit Acknowledge
|
|
+ After suspension of all accesses to the External Bus has been requested by setting bit acc_inh, acc_inh_ack acknowledges the request and inidcates that access suspension is now in effect. The bit is cleared when acc_inh gets deasserted. */
|
|
+#define MODCON_AIA 0x02000000
|
|
+/* no access restriction are active in the EBU subsystem
|
|
+#define MODCON_AIA_NO_INHIBIT 0x00000000 */
|
|
+/** accesses are restricted to selected (configuration) system bus port(s) */
|
|
+#define MODCON_AIA_INHIBIT 0x02000000
|
|
+/** Access Inhibit request
|
|
+ Setting this bit will suspend all non-CPU system bus ports and the EBU itself from accessing the External Bus. This feature is usually used when the CPU needs to reconfigure protocol parameters in the EBU in order to avoid external accesses with invalid settings. The EBU acknowledges that the access suspension is in effect by asserting acc_inh_ack. */
|
|
+#define MODCON_AI 0x01000000
|
|
+/* no access restriction are active in the EBU subsystem
|
|
+#define MODCON_AI_NO_INHIBIT 0x00000000 */
|
|
+/** accesses are restricted to selected (configuration) system bus port(s) */
|
|
+#define MODCON_AI_INHIBIT 0x01000000
|
|
+/** Lock Timeout */
|
|
+#define MODCON_LTO_MASK 0x00FF0000
|
|
+/** field offset */
|
|
+#define MODCON_LTO_OFFSET 16
|
|
+/** Reserved */
|
|
+#define MODCON_DDREN 0x00008000
|
|
+/** Pad Drive Control
|
|
+ Intended to be used to control the EBU pad''s drive strength. Refer to the GPON chip specification to see which drive strnegth options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */
|
|
+#define MODCON_PEXT 0x00004000
|
|
+/* Normal drive
|
|
+#define MODCON_PEXT_NORMAL 0x00000000 */
|
|
+/** Strong drive */
|
|
+#define MODCON_PEXT_STRONG 0x00004000
|
|
+/** Pad Slew Falling Edge Control
|
|
+ Intended to be used to trim the External Bus pad's falling edge slew rate. Refer to the GPON chip specification to see which slew rate options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */
|
|
+#define MODCON_SLF 0x00002000
|
|
+/* Slow slew rate
|
|
+#define MODCON_SLF_SLOW 0x00000000 */
|
|
+/** Fast slew rate */
|
|
+#define MODCON_SLF_FAST 0x00002000
|
|
+/** Pad Slew Rising Edge Control
|
|
+ Intended to be used to trim the External Bus pad's rising edge slew rate. Refer to the GPON chip specification to see which slew rate options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */
|
|
+#define MODCON_SLR 0x00001000
|
|
+/* Slow slew rate
|
|
+#define MODCON_SLR_SLOW 0x00000000 */
|
|
+/** Fast slew rate */
|
|
+#define MODCON_SLR_FAST 0x00001000
|
|
+/** Write Buffering Mode
|
|
+ This bit controls when the EBU starts a new write burst transaction from the Memport interface. */
|
|
+#define MODCON_WBM 0x00000040
|
|
+/* The EBU starts a write transaction on the External Bus as early as possible, expecting that the n beats of the write burst will be transferred within n or n+1 clock cycles over the EBU's Memport interface. Use this mode if the EBU is clocked at the same or a slower frequency than the system bus interconnect.
|
|
+#define MODCON_WBM_START_WRITE_EARLY 0x00000000 */
|
|
+/** The EBU start a write transaction only after all data of a write burst have been received over the EBU's Memport interface. Use this mode if the EBU is clocked at a higher frequency than the system bus interrconnect. */
|
|
+#define MODCON_WBM_START_WRITE_LATE 0x00000040
|
|
+/** Reserved */
|
|
+#define MODCON_SDCLKEN 0x00000020
|
|
+/** Standby Mode Enable
|
|
+ When set allows the EBU subsystem to enter standby mode in response to a rising edge on input signal standby_req_i. See Section 3.9.3 for details. */
|
|
+#define MODCON_STBYEN 0x00000010
|
|
+/* Disable
|
|
+#define MODCON_STBYEN_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define MODCON_STBYEN_EN 0x00000010
|
|
+/** Enable BFCLK1
|
|
+ This field will enables or disables mirroring the clock that is output on BFCLKO_0 also on pad BFCLKO_1 to double the drive strength. See also Section 3.17.3) */
|
|
+#define MODCON_BFCLK1EN 0x00000008
|
|
+/* Disable
|
|
+#define MODCON_BFCLK1EN_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define MODCON_BFCLK1EN_EN 0x00000008
|
|
+/** Ready/Busy Status Edge
|
|
+ This is a read-only bit which shows a change of the logic level shown in the sts field since last read. It is reset by a read access. */
|
|
+#define MODCON_STSEDGE 0x00000004
|
|
+/** Ready/Busy Status
|
|
+ This is a read-only bit which reflects the current logic level present on the RDY/BSY or STS input pin which is (optionally) fed-in from a General Purpose I/O pad which is not part of the EBU via the EBU's input pin signal gpio_nand_rdy_ */
|
|
+#define MODCON_STS 0x00000002
|
|
+/** External Bus Arbitration Mode
|
|
+ This bit allows to disconnect the EBU from the External Bus. While EBU_MODCON.acc_inh_ack is 0, the value of arb_mode is forced to OWN_BUS. */
|
|
+#define MODCON_AM 0x00000001
|
|
+/* The EBU does not own the bus (multi-master)
|
|
+#define MODCON_AM_SHAREDBUS 0x00000000 */
|
|
+/** The EBU owns the external bus. */
|
|
+#define MODCON_AM_OWNBUS 0x00000001
|
|
+
|
|
+/* Fields of "Bus Read Configuration Register0" */
|
|
+/** Device Type For Region
|
|
+ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */
|
|
+#define BUSRCON0_AGEN_MASK 0xF0000000
|
|
+/** field offset */
|
|
+#define BUSRCON0_AGEN_OFFSET 28
|
|
+/** Muxed Asynchronous Type External Memory */
|
|
+#define BUSRCON0_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000
|
|
+/** Muxed Burst Type External Memory */
|
|
+#define BUSRCON0_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000
|
|
+/** NAND Flash (page optimised) */
|
|
+#define BUSRCON0_AGEN_NAND_FLASH 0x20000000
|
|
+/** Muxed Cellular RAM External Memory */
|
|
+#define BUSRCON0_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000
|
|
+/** Demuxed Asynchronous Type External Memory */
|
|
+#define BUSRCON0_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000
|
|
+/** Demuxed Burst Type External Memory */
|
|
+#define BUSRCON0_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000
|
|
+/** Demuxed Page Mode External Memory */
|
|
+#define BUSRCON0_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000
|
|
+/** Demuxed Cellular RAM External Memory */
|
|
+#define BUSRCON0_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000
|
|
+/** Serial Flash */
|
|
+#define BUSRCON0_AGEN_SERIAL_FLASH 0xF0000000
|
|
+/** Device Addressing Mode
|
|
+ t.b.d. */
|
|
+#define BUSRCON0_PORTW_MASK 0x0C000000
|
|
+/** field offset */
|
|
+#define BUSRCON0_PORTW_OFFSET 26
|
|
+/** 8-bit multiplexed */
|
|
+#define BUSRCON0_PORTW_8_BIT_MUX 0x00000000
|
|
+/** 16-bit multiplexed */
|
|
+#define BUSRCON0_PORTW_16_BIT_MUX 0x04000000
|
|
+/** Twin, 16-bit multiplexed */
|
|
+#define BUSRCON0_PORTW_TWIN_16_BIT_MUX 0x08000000
|
|
+/** 32-bit multiplexed */
|
|
+#define BUSRCON0_PORTW_32_BIT_MUX 0x0C000000
|
|
+/** External Wait Control
|
|
+ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */
|
|
+#define BUSRCON0_WAIT_MASK 0x03000000
|
|
+/** field offset */
|
|
+#define BUSRCON0_WAIT_OFFSET 24
|
|
+/** WAIT is ignored (default after reset). */
|
|
+#define BUSRCON0_WAIT_OFF 0x00000000
|
|
+/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */
|
|
+#define BUSRCON0_WAIT_EARLY_WAIT 0x01000000
|
|
+/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */
|
|
+#define BUSRCON0_WAIT_TWO_STAGE_SYNC 0x01000000
|
|
+/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */
|
|
+#define BUSRCON0_WAIT_WAIT_WITH_DATA 0x02000000
|
|
+/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */
|
|
+#define BUSRCON0_WAIT_SINGLE_STAGE_SYNC 0x02000000
|
|
+/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */
|
|
+#define BUSRCON0_WAIT_ABORT_AND_RETRY 0x03000000
|
|
+/** Disable Burst Address Wrapping */
|
|
+#define BUSRCON0_DBA 0x00800000
|
|
+/** Reversed polarity at wait */
|
|
+#define BUSRCON0_WAITINV 0x00400000
|
|
+/* Low active.
|
|
+#define BUSRCON0_WAITINV_ACTLOW 0x00000000 */
|
|
+/** High active */
|
|
+#define BUSRCON0_WAITINV_ACTHI 0x00400000
|
|
+/** Early ADV Enable for Synchronous Bursts */
|
|
+#define BUSRCON0_EBSE 0x00200000
|
|
+/* Low active.
|
|
+#define BUSRCON0_EBSE_DELAYED 0x00000000 */
|
|
+/** High active */
|
|
+#define BUSRCON0_EBSE_NOT_DELAYED 0x00200000
|
|
+/** Early Control Signals for Synchronous Bursts */
|
|
+#define BUSRCON0_ECSE 0x00100000
|
|
+/* Low active.
|
|
+#define BUSRCON0_ECSE_DELAYED 0x00000000 */
|
|
+/** High active */
|
|
+#define BUSRCON0_ECSE_NOT_DELAYED 0x00100000
|
|
+/** Synchronous Burst Buffer Mode Select */
|
|
+#define BUSRCON0_FBBMSEL 0x00080000
|
|
+/* FIXED_LENGTH
|
|
+#define BUSRCON0_FBBMSEL_FIXED_LENGTH 0x00000000 */
|
|
+/** CONTINUOUS */
|
|
+#define BUSRCON0_FBBMSEL_CONTINUOUS 0x00080000
|
|
+/** Burst Length for Synchronous Burst */
|
|
+#define BUSRCON0_FETBLEN_MASK 0x00070000
|
|
+/** field offset */
|
|
+#define BUSRCON0_FETBLEN_OFFSET 16
|
|
+/** Up to 1 data cycle (default after reset). */
|
|
+#define BUSRCON0_FETBLEN_SINGLE 0x00000000
|
|
+/** Up to 2 data cycles. */
|
|
+#define BUSRCON0_FETBLEN_BURST2 0x00010000
|
|
+/** Up to 4 data cycles. */
|
|
+#define BUSRCON0_FETBLEN_BURST4 0x00020000
|
|
+/** Up to 8 data cycles. */
|
|
+#define BUSRCON0_FETBLEN_BURST8 0x00030000
|
|
+/** Up to 16 data cycles. */
|
|
+#define BUSRCON0_FETBLEN_BURST16 0x00040000
|
|
+/** Reserved
|
|
+ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */
|
|
+#define BUSRCON0_NANDAMAP_MASK 0x0000C000
|
|
+/** field offset */
|
|
+#define BUSRCON0_NANDAMAP_OFFSET 14
|
|
+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
|
|
+#define BUSRCON0_NANDAMAP_NAND_A17_16 0x00000000
|
|
+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
|
|
+#define BUSRCON0_NANDAMAP_NAND_WAIT_ADV 0x00004000
|
|
+/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */
|
|
+#define BUSRCON0_NANDAMAP_NAND_AD9_8 0x00008000
|
|
+/** Reserved for future use. Do not use or unpredictable results may occur. */
|
|
+#define BUSRCON0_NANDAMAP_NAND_RFU 0x0000C000
|
|
+/** AAD-mux Protocol
|
|
+ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */
|
|
+#define BUSRCON0_AADMUX 0x00002000
|
|
+/* Muxed device is write accessed in AD-mux mode.
|
|
+#define BUSRCON0_AADMUX_AD_MUX 0x00000000 */
|
|
+/** Muxed device is write accessed in AAD-mux mode. */
|
|
+#define BUSRCON0_AADMUX_AAD_MUX 0x00002000
|
|
+/** Asynchronous Address Phase */
|
|
+#define BUSRCON0_AAP 0x00001000
|
|
+/* Clock is enabled at beginning of access.
|
|
+#define BUSRCON0_AAP_EARLY 0x00000000 */
|
|
+/** Clock is enabled after address phase. */
|
|
+#define BUSRCON0_AAP_LATE 0x00001000
|
|
+/** Burst Flash Read Single Stage Synchronisation */
|
|
+#define BUSRCON0_BFSSS 0x00000800
|
|
+/* Two stages of synchronisation used.
|
|
+#define BUSRCON0_BFSSS_TWO_STAGE 0x00000000 */
|
|
+/** Single stage of synchronisation used. */
|
|
+#define BUSRCON0_BFSSS_SINGLE_STAGE 0x00000800
|
|
+/** Burst Flash Clock Feedback Enable */
|
|
+#define BUSRCON0_FDBKEN 0x00000400
|
|
+/* Disable
|
|
+#define BUSRCON0_FDBKEN_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define BUSRCON0_FDBKEN_EN 0x00000400
|
|
+/** Auxiliary Chip Select Enable
|
|
+ Not supported in GPON-EBU, field must be set to 0. */
|
|
+#define BUSRCON0_CSA 0x00000200
|
|
+/* Disable
|
|
+#define BUSRCON0_CSA_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define BUSRCON0_CSA_EN 0x00000200
|
|
+/** Flash Non-Array Access Enable
|
|
+ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */
|
|
+#define BUSRCON0_NAA 0x00000100
|
|
+/* Disable
|
|
+#define BUSRCON0_NAA_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define BUSRCON0_NAA_EN 0x00000100
|
|
+/** Module Enable */
|
|
+#define BUSRCON0_ENABLE 0x00000001
|
|
+/* Disable
|
|
+#define BUSRCON0_ENABLE_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define BUSRCON0_ENABLE_EN 0x00000001
|
|
+
|
|
+/* Fields of "Bus Read Parameters Register0" */
|
|
+/** Address Cycles
|
|
+ Number of cycles for address phase. */
|
|
+#define BUSRP0_ADDRC_MASK 0xF0000000
|
|
+/** field offset */
|
|
+#define BUSRP0_ADDRC_OFFSET 28
|
|
+/** Address Hold Cycles For Multiplexed Address
|
|
+ Number of address hold cycles during multiplexed accesses. */
|
|
+#define BUSRP0_ADHOLC_MASK 0x0F000000
|
|
+/** field offset */
|
|
+#define BUSRP0_ADHOLC_OFFSET 24
|
|
+/** Programmed Command Delay Cycles
|
|
+ Number of delay cycles during command delay phase. */
|
|
+#define BUSRP0_CMDDELAY_MASK 0x00F00000
|
|
+/** field offset */
|
|
+#define BUSRP0_CMDDELAY_OFFSET 20
|
|
+/** Extended Data */
|
|
+#define BUSRP0_EXTDATA_MASK 0x000C0000
|
|
+/** field offset */
|
|
+#define BUSRP0_EXTDATA_OFFSET 18
|
|
+/** External device outputs data every BFCLK cycle */
|
|
+#define BUSRP0_EXTDATA_ONE 0x00000000
|
|
+/** External device outputs data every 2nd BFCLK cycles */
|
|
+#define BUSRP0_EXTDATA_TWO 0x00040000
|
|
+/** External device outputs data every 4th BFCLK cycles */
|
|
+#define BUSRP0_EXTDATA_FOUR 0x00080000
|
|
+/** External device outputs data every 8th BFCLK cycles */
|
|
+#define BUSRP0_EXTDATA_EIGHT 0x000C0000
|
|
+/** Frequency of external clock at pin BFCLKO */
|
|
+#define BUSRP0_EXTCLOCK_MASK 0x00030000
|
|
+/** field offset */
|
|
+#define BUSRP0_EXTCLOCK_OFFSET 16
|
|
+/** Equal to ebu_clk frequency. */
|
|
+#define BUSRP0_EXTCLOCK_ONE_TO_ONE 0x00000000
|
|
+/** 1/2 of ebu_clk frequency. */
|
|
+#define BUSRP0_EXTCLOCK_ONE_TO_TWO 0x00010000
|
|
+/** 1/3 of ebu_clk frequency. */
|
|
+#define BUSRP0_EXTCLOCK_ONE_TO_THREE 0x00020000
|
|
+/** 1/4 of ebu_clk frequency (default after reset). */
|
|
+#define BUSRP0_EXTCLOCK_ONE_TO_FOUR 0x00030000
|
|
+/** Data Hold Cycles For read Accesses
|
|
+ Number of data hold cycles during read accesses. Applies to spinner support only where the address is guaranteed stable for datac clocks after RD high */
|
|
+#define BUSRP0_DATAC_MASK 0x0000F000
|
|
+/** field offset */
|
|
+#define BUSRP0_DATAC_OFFSET 12
|
|
+/** Programmed Wait States for read accesses
|
|
+ Number of programmed wait states for read accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */
|
|
+#define BUSRP0_WAITRDC_MASK 0x00000F80
|
|
+/** field offset */
|
|
+#define BUSRP0_WAITRDC_OFFSET 7
|
|
+/** Recovery Cycles After read Accesses, same CS
|
|
+ Number of idle cycles after read accesses when the next access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */
|
|
+#define BUSRP0_RECOVC_MASK 0x00000070
|
|
+/** field offset */
|
|
+#define BUSRP0_RECOVC_OFFSET 4
|
|
+/** Recovery Cycles After read Accesses, other CS
|
|
+ Number of idle cycles after read accesses when the next access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */
|
|
+#define BUSRP0_DTACS_MASK 0x0000000F
|
|
+/** field offset */
|
|
+#define BUSRP0_DTACS_OFFSET 0
|
|
+
|
|
+/* Fields of "Bus Write Configuration Register0" */
|
|
+/** Device Type For Region
|
|
+ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */
|
|
+#define BUSWCON0_AGEN_MASK 0xF0000000
|
|
+/** field offset */
|
|
+#define BUSWCON0_AGEN_OFFSET 28
|
|
+/** Muxed Asynchronous Type External Memory */
|
|
+#define BUSWCON0_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000
|
|
+/** Muxed Burst Type External Memory */
|
|
+#define BUSWCON0_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000
|
|
+/** NAND Flash (page optimised) */
|
|
+#define BUSWCON0_AGEN_NAND_FLASH 0x20000000
|
|
+/** Muxed Cellular RAM External Memory */
|
|
+#define BUSWCON0_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000
|
|
+/** Demuxed Asynchronous Type External Memory */
|
|
+#define BUSWCON0_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000
|
|
+/** Demuxed Burst Type External Memory */
|
|
+#define BUSWCON0_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000
|
|
+/** Demuxed Page Mode External Memory */
|
|
+#define BUSWCON0_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000
|
|
+/** Demuxed Cellular RAM External Memory */
|
|
+#define BUSWCON0_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000
|
|
+/** Serial Flash */
|
|
+#define BUSWCON0_AGEN_SERIAL_FLASH 0xF0000000
|
|
+/** Device Addressing Mode
|
|
+ t.b.d. */
|
|
+#define BUSWCON0_PORTW_MASK 0x0C000000
|
|
+/** field offset */
|
|
+#define BUSWCON0_PORTW_OFFSET 26
|
|
+/** External Wait Control
|
|
+ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */
|
|
+#define BUSWCON0_WAIT_MASK 0x03000000
|
|
+/** field offset */
|
|
+#define BUSWCON0_WAIT_OFFSET 24
|
|
+/** WAIT is ignored (default after reset). */
|
|
+#define BUSWCON0_WAIT_OFF 0x00000000
|
|
+/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */
|
|
+#define BUSWCON0_WAIT_EARLY_WAIT 0x01000000
|
|
+/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */
|
|
+#define BUSWCON0_WAIT_TWO_STAGE_SYNC 0x01000000
|
|
+/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */
|
|
+#define BUSWCON0_WAIT_WAIT_WITH_DATA 0x02000000
|
|
+/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */
|
|
+#define BUSWCON0_WAIT_SINGLE_STAGE_SYNC 0x02000000
|
|
+/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */
|
|
+#define BUSWCON0_WAIT_ABORT_AND_RETRY 0x03000000
|
|
+/** Reserved */
|
|
+#define BUSWCON0_LOCKCS 0x00800000
|
|
+/** Reversed polarity at wait */
|
|
+#define BUSWCON0_WAITINV 0x00400000
|
|
+/* Low active.
|
|
+#define BUSWCON0_WAITINV_ACTLOW 0x00000000 */
|
|
+/** High active */
|
|
+#define BUSWCON0_WAITINV_ACTHI 0x00400000
|
|
+/** Early ADV Enable for Synchronous Bursts */
|
|
+#define BUSWCON0_EBSE 0x00200000
|
|
+/* Low active.
|
|
+#define BUSWCON0_EBSE_DELAYED 0x00000000 */
|
|
+/** High active */
|
|
+#define BUSWCON0_EBSE_NOT_DELAYED 0x00200000
|
|
+/** Early Control Signals for Synchronous Bursts */
|
|
+#define BUSWCON0_ECSE 0x00100000
|
|
+/* Low active.
|
|
+#define BUSWCON0_ECSE_DELAYED 0x00000000 */
|
|
+/** High active */
|
|
+#define BUSWCON0_ECSE_NOT_DELAYED 0x00100000
|
|
+/** Synchronous Burst Buffer Mode Select */
|
|
+#define BUSWCON0_FBBMSEL 0x00080000
|
|
+/* FIXED_LENGTH
|
|
+#define BUSWCON0_FBBMSEL_FIXED_LENGTH 0x00000000 */
|
|
+/** CONTINUOUS */
|
|
+#define BUSWCON0_FBBMSEL_CONTINUOUS 0x00080000
|
|
+/** Burst Length for Synchronous Burst */
|
|
+#define BUSWCON0_FETBLEN_MASK 0x00070000
|
|
+/** field offset */
|
|
+#define BUSWCON0_FETBLEN_OFFSET 16
|
|
+/** Up to 1 data cycle (default after reset). */
|
|
+#define BUSWCON0_FETBLEN_SINGLE 0x00000000
|
|
+/** Up to 2 data cycles. */
|
|
+#define BUSWCON0_FETBLEN_BURST2 0x00010000
|
|
+/** Up to 4 data cycles. */
|
|
+#define BUSWCON0_FETBLEN_BURST4 0x00020000
|
|
+/** Up to 8 data cycles. */
|
|
+#define BUSWCON0_FETBLEN_BURST8 0x00030000
|
|
+/** Up to 16 data cycles. */
|
|
+#define BUSWCON0_FETBLEN_BURST16 0x00040000
|
|
+/** Reserved
|
|
+ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */
|
|
+#define BUSWCON0_NANDAMAP_MASK 0x0000C000
|
|
+/** field offset */
|
|
+#define BUSWCON0_NANDAMAP_OFFSET 14
|
|
+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
|
|
+#define BUSWCON0_NANDAMAP_NAND_A17_16 0x00000000
|
|
+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
|
|
+#define BUSWCON0_NANDAMAP_NAND_WAIT_ADV 0x00004000
|
|
+/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */
|
|
+#define BUSWCON0_NANDAMAP_NAND_AD9_8 0x00008000
|
|
+/** Reserved for future use. Do not use or unpredictable results may occur. */
|
|
+#define BUSWCON0_NANDAMAP_NAND_RFU 0x0000C000
|
|
+/** AAD-mux Protocol
|
|
+ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */
|
|
+#define BUSWCON0_AADMUX 0x00002000
|
|
+/* Muxed device is write accessed in AD-mux mode.
|
|
+#define BUSWCON0_AADMUX_AD_MUX 0x00000000 */
|
|
+/** Muxed device is write accessed in AAD-mux mode. */
|
|
+#define BUSWCON0_AADMUX_AAD_MUX 0x00002000
|
|
+/** Asynchronous Address Phase */
|
|
+#define BUSWCON0_AAP 0x00001000
|
|
+/* Clock is enabled at beginning of access.
|
|
+#define BUSWCON0_AAP_EARLY 0x00000000 */
|
|
+/** Clock is enabled after address phase. */
|
|
+#define BUSWCON0_AAP_LATE 0x00001000
|
|
+/** Auxiliary Chip Select Enable
|
|
+ Not supported in GPON-EBU, field must be set to 0. */
|
|
+#define BUSWCON0_CSA 0x00000200
|
|
+/* Disable
|
|
+#define BUSWCON0_CSA_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define BUSWCON0_CSA_EN 0x00000200
|
|
+/** Flash Non-Array Access Enable
|
|
+ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */
|
|
+#define BUSWCON0_NAA 0x00000100
|
|
+/* Disable
|
|
+#define BUSWCON0_NAA_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define BUSWCON0_NAA_EN 0x00000100
|
|
+/** Module Enable */
|
|
+#define BUSWCON0_ENABLE 0x00000001
|
|
+/* Disable
|
|
+#define BUSWCON0_ENABLE_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define BUSWCON0_ENABLE_EN 0x00000001
|
|
+
|
|
+/* Fields of "Bus Write Parameters Register0" */
|
|
+/** Address Cycles
|
|
+ Number of cycles for address phase. */
|
|
+#define BUSWP0_ADDRC_MASK 0xF0000000
|
|
+/** field offset */
|
|
+#define BUSWP0_ADDRC_OFFSET 28
|
|
+/** Address Hold Cycles For Multiplexed Address
|
|
+ Number of address hold cycles during multiplexed accesses. */
|
|
+#define BUSWP0_ADHOLC_MASK 0x0F000000
|
|
+/** field offset */
|
|
+#define BUSWP0_ADHOLC_OFFSET 24
|
|
+/** Programmed Command Delay Cycles
|
|
+ Number of delay cycles during command delay phase. */
|
|
+#define BUSWP0_CMDDELAY_MASK 0x00F00000
|
|
+/** field offset */
|
|
+#define BUSWP0_CMDDELAY_OFFSET 20
|
|
+/** Extended Data */
|
|
+#define BUSWP0_EXTDATA_MASK 0x000C0000
|
|
+/** field offset */
|
|
+#define BUSWP0_EXTDATA_OFFSET 18
|
|
+/** External device outputs data every BFCLK cycle */
|
|
+#define BUSWP0_EXTDATA_ONE 0x00000000
|
|
+/** External device outputs data every 2nd BFCLK cycles */
|
|
+#define BUSWP0_EXTDATA_TWO 0x00040000
|
|
+/** External device outputs data every 4th BFCLK cycles */
|
|
+#define BUSWP0_EXTDATA_FOUR 0x00080000
|
|
+/** External device outputs data every 8th BFCLK cycles */
|
|
+#define BUSWP0_EXTDATA_EIGHT 0x000C0000
|
|
+/** Frequency of external clock at pin BFCLKO */
|
|
+#define BUSWP0_EXTCLOCK_MASK 0x00030000
|
|
+/** field offset */
|
|
+#define BUSWP0_EXTCLOCK_OFFSET 16
|
|
+/** Equal to ebu_clk frequency. */
|
|
+#define BUSWP0_EXTCLOCK_ONE_TO_ONE 0x00000000
|
|
+/** 1/2 of ebu_clk frequency. */
|
|
+#define BUSWP0_EXTCLOCK_ONE_TO_TWO 0x00010000
|
|
+/** 1/3 of ebu_clk frequency. */
|
|
+#define BUSWP0_EXTCLOCK_ONE_TO_THREE 0x00020000
|
|
+/** 1/4 of ebu_clk frequency (default after reset). */
|
|
+#define BUSWP0_EXTCLOCK_ONE_TO_FOUR 0x00030000
|
|
+/** Data Hold Cycles For write Accesses
|
|
+ Number of data hold cycles during write accesses. */
|
|
+#define BUSWP0_DATAC_MASK 0x0000F000
|
|
+/** field offset */
|
|
+#define BUSWP0_DATAC_OFFSET 12
|
|
+/** Programmed Wait States For write Accesses
|
|
+ Number of programmed wait states for write accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */
|
|
+#define BUSWP0_WAITWDC_MASK 0x00000F80
|
|
+/** field offset */
|
|
+#define BUSWP0_WAITWDC_OFFSET 7
|
|
+/** Recovery Cycles After write Accesses, same CS
|
|
+ Number of idle cycles after write accesses when following access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */
|
|
+#define BUSWP0_RECOVC_MASK 0x00000070
|
|
+/** field offset */
|
|
+#define BUSWP0_RECOVC_OFFSET 4
|
|
+/** Recovery Cycles After write Accesses, other CS
|
|
+ Number of idle cycles after write accesses when the following access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */
|
|
+#define BUSWP0_DTACS_MASK 0x0000000F
|
|
+/** field offset */
|
|
+#define BUSWP0_DTACS_OFFSET 0
|
|
+
|
|
+/* Fields of "Bus Read Configuration Register1" */
|
|
+/** Device Type For Region
|
|
+ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */
|
|
+#define BUSRCON1_AGEN_MASK 0xF0000000
|
|
+/** field offset */
|
|
+#define BUSRCON1_AGEN_OFFSET 28
|
|
+/** Muxed Asynchronous Type External Memory */
|
|
+#define BUSRCON1_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000
|
|
+/** Muxed Burst Type External Memory */
|
|
+#define BUSRCON1_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000
|
|
+/** NAND Flash (page optimised) */
|
|
+#define BUSRCON1_AGEN_NAND_FLASH 0x20000000
|
|
+/** Muxed Cellular RAM External Memory */
|
|
+#define BUSRCON1_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000
|
|
+/** Demuxed Asynchronous Type External Memory */
|
|
+#define BUSRCON1_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000
|
|
+/** Demuxed Burst Type External Memory */
|
|
+#define BUSRCON1_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000
|
|
+/** Demuxed Page Mode External Memory */
|
|
+#define BUSRCON1_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000
|
|
+/** Demuxed Cellular RAM External Memory */
|
|
+#define BUSRCON1_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000
|
|
+/** Serial Flash */
|
|
+#define BUSRCON1_AGEN_SERIAL_FLASH 0xF0000000
|
|
+/** Device Addressing Mode
|
|
+ t.b.d. */
|
|
+#define BUSRCON1_PORTW_MASK 0x0C000000
|
|
+/** field offset */
|
|
+#define BUSRCON1_PORTW_OFFSET 26
|
|
+/** 8-bit multiplexed */
|
|
+#define BUSRCON1_PORTW_8_BIT_MUX 0x00000000
|
|
+/** 16-bit multiplexed */
|
|
+#define BUSRCON1_PORTW_16_BIT_MUX 0x04000000
|
|
+/** Twin, 16-bit multiplexed */
|
|
+#define BUSRCON1_PORTW_TWIN_16_BIT_MUX 0x08000000
|
|
+/** 32-bit multiplexed */
|
|
+#define BUSRCON1_PORTW_32_BIT_MUX 0x0C000000
|
|
+/** External Wait Control
|
|
+ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */
|
|
+#define BUSRCON1_WAIT_MASK 0x03000000
|
|
+/** field offset */
|
|
+#define BUSRCON1_WAIT_OFFSET 24
|
|
+/** WAIT is ignored (default after reset). */
|
|
+#define BUSRCON1_WAIT_OFF 0x00000000
|
|
+/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */
|
|
+#define BUSRCON1_WAIT_EARLY_WAIT 0x01000000
|
|
+/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */
|
|
+#define BUSRCON1_WAIT_TWO_STAGE_SYNC 0x01000000
|
|
+/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */
|
|
+#define BUSRCON1_WAIT_WAIT_WITH_DATA 0x02000000
|
|
+/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */
|
|
+#define BUSRCON1_WAIT_SINGLE_STAGE_SYNC 0x02000000
|
|
+/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */
|
|
+#define BUSRCON1_WAIT_ABORT_AND_RETRY 0x03000000
|
|
+/** Disable Burst Address Wrapping */
|
|
+#define BUSRCON1_DBA 0x00800000
|
|
+/** Reversed polarity at wait */
|
|
+#define BUSRCON1_WAITINV 0x00400000
|
|
+/* Low active.
|
|
+#define BUSRCON1_WAITINV_ACTLOW 0x00000000 */
|
|
+/** High active */
|
|
+#define BUSRCON1_WAITINV_ACTHI 0x00400000
|
|
+/** Early ADV Enable for Synchronous Bursts */
|
|
+#define BUSRCON1_EBSE 0x00200000
|
|
+/* Low active.
|
|
+#define BUSRCON1_EBSE_DELAYED 0x00000000 */
|
|
+/** High active */
|
|
+#define BUSRCON1_EBSE_NOT_DELAYED 0x00200000
|
|
+/** Early Control Signals for Synchronous Bursts */
|
|
+#define BUSRCON1_ECSE 0x00100000
|
|
+/* Low active.
|
|
+#define BUSRCON1_ECSE_DELAYED 0x00000000 */
|
|
+/** High active */
|
|
+#define BUSRCON1_ECSE_NOT_DELAYED 0x00100000
|
|
+/** Synchronous Burst Buffer Mode Select */
|
|
+#define BUSRCON1_FBBMSEL 0x00080000
|
|
+/* FIXED_LENGTH
|
|
+#define BUSRCON1_FBBMSEL_FIXED_LENGTH 0x00000000 */
|
|
+/** CONTINUOUS */
|
|
+#define BUSRCON1_FBBMSEL_CONTINUOUS 0x00080000
|
|
+/** Burst Length for Synchronous Burst */
|
|
+#define BUSRCON1_FETBLEN_MASK 0x00070000
|
|
+/** field offset */
|
|
+#define BUSRCON1_FETBLEN_OFFSET 16
|
|
+/** Up to 1 data cycle (default after reset). */
|
|
+#define BUSRCON1_FETBLEN_SINGLE 0x00000000
|
|
+/** Up to 2 data cycles. */
|
|
+#define BUSRCON1_FETBLEN_BURST2 0x00010000
|
|
+/** Up to 4 data cycles. */
|
|
+#define BUSRCON1_FETBLEN_BURST4 0x00020000
|
|
+/** Up to 8 data cycles. */
|
|
+#define BUSRCON1_FETBLEN_BURST8 0x00030000
|
|
+/** Up to 16 data cycles. */
|
|
+#define BUSRCON1_FETBLEN_BURST16 0x00040000
|
|
+/** Reserved
|
|
+ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */
|
|
+#define BUSRCON1_NANDAMAP_MASK 0x0000C000
|
|
+/** field offset */
|
|
+#define BUSRCON1_NANDAMAP_OFFSET 14
|
|
+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
|
|
+#define BUSRCON1_NANDAMAP_NAND_A17_16 0x00000000
|
|
+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
|
|
+#define BUSRCON1_NANDAMAP_NAND_WAIT_ADV 0x00004000
|
|
+/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */
|
|
+#define BUSRCON1_NANDAMAP_NAND_AD9_8 0x00008000
|
|
+/** Reserved for future use. Do not use or unpredictable results may occur. */
|
|
+#define BUSRCON1_NANDAMAP_NAND_RFU 0x0000C000
|
|
+/** AAD-mux Protocol
|
|
+ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */
|
|
+#define BUSRCON1_AADMUX 0x00002000
|
|
+/* Muxed device is write accessed in AD-mux mode.
|
|
+#define BUSRCON1_AADMUX_AD_MUX 0x00000000 */
|
|
+/** Muxed device is write accessed in AAD-mux mode. */
|
|
+#define BUSRCON1_AADMUX_AAD_MUX 0x00002000
|
|
+/** Asynchronous Address Phase */
|
|
+#define BUSRCON1_AAP 0x00001000
|
|
+/* Clock is enabled at beginning of access.
|
|
+#define BUSRCON1_AAP_EARLY 0x00000000 */
|
|
+/** Clock is enabled after address phase. */
|
|
+#define BUSRCON1_AAP_LATE 0x00001000
|
|
+/** Burst Flash Read Single Stage Synchronisation */
|
|
+#define BUSRCON1_BFSSS 0x00000800
|
|
+/* Two stages of synchronisation used.
|
|
+#define BUSRCON1_BFSSS_TWO_STAGE 0x00000000 */
|
|
+/** Single stage of synchronisation used. */
|
|
+#define BUSRCON1_BFSSS_SINGLE_STAGE 0x00000800
|
|
+/** Burst Flash Clock Feedback Enable */
|
|
+#define BUSRCON1_FDBKEN 0x00000400
|
|
+/* Disable
|
|
+#define BUSRCON1_FDBKEN_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define BUSRCON1_FDBKEN_EN 0x00000400
|
|
+/** Auxiliary Chip Select Enable
|
|
+ Not supported in GPON-EBU, field must be set to 0. */
|
|
+#define BUSRCON1_CSA 0x00000200
|
|
+/* Disable
|
|
+#define BUSRCON1_CSA_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define BUSRCON1_CSA_EN 0x00000200
|
|
+/** Flash Non-Array Access Enable
|
|
+ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */
|
|
+#define BUSRCON1_NAA 0x00000100
|
|
+/* Disable
|
|
+#define BUSRCON1_NAA_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define BUSRCON1_NAA_EN 0x00000100
|
|
+/** Module Enable */
|
|
+#define BUSRCON1_ENABLE 0x00000001
|
|
+/* Disable
|
|
+#define BUSRCON1_ENABLE_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define BUSRCON1_ENABLE_EN 0x00000001
|
|
+
|
|
+/* Fields of "Bus Read Parameters Register1" */
|
|
+/** Address Cycles
|
|
+ Number of cycles for address phase. */
|
|
+#define BUSRP1_ADDRC_MASK 0xF0000000
|
|
+/** field offset */
|
|
+#define BUSRP1_ADDRC_OFFSET 28
|
|
+/** Address Hold Cycles For Multiplexed Address
|
|
+ Number of address hold cycles during multiplexed accesses. */
|
|
+#define BUSRP1_ADHOLC_MASK 0x0F000000
|
|
+/** field offset */
|
|
+#define BUSRP1_ADHOLC_OFFSET 24
|
|
+/** Programmed Command Delay Cycles
|
|
+ Number of delay cycles during command delay phase. */
|
|
+#define BUSRP1_CMDDELAY_MASK 0x00F00000
|
|
+/** field offset */
|
|
+#define BUSRP1_CMDDELAY_OFFSET 20
|
|
+/** Extended Data */
|
|
+#define BUSRP1_EXTDATA_MASK 0x000C0000
|
|
+/** field offset */
|
|
+#define BUSRP1_EXTDATA_OFFSET 18
|
|
+/** External device outputs data every BFCLK cycle */
|
|
+#define BUSRP1_EXTDATA_ONE 0x00000000
|
|
+/** External device outputs data every 2nd BFCLK cycles */
|
|
+#define BUSRP1_EXTDATA_TWO 0x00040000
|
|
+/** External device outputs data every 4th BFCLK cycles */
|
|
+#define BUSRP1_EXTDATA_FOUR 0x00080000
|
|
+/** External device outputs data every 8th BFCLK cycles */
|
|
+#define BUSRP1_EXTDATA_EIGHT 0x000C0000
|
|
+/** Frequency of external clock at pin BFCLKO */
|
|
+#define BUSRP1_EXTCLOCK_MASK 0x00030000
|
|
+/** field offset */
|
|
+#define BUSRP1_EXTCLOCK_OFFSET 16
|
|
+/** Equal to ebu_clk frequency. */
|
|
+#define BUSRP1_EXTCLOCK_ONE_TO_ONE 0x00000000
|
|
+/** 1/2 of ebu_clk frequency. */
|
|
+#define BUSRP1_EXTCLOCK_ONE_TO_TWO 0x00010000
|
|
+/** 1/3 of ebu_clk frequency. */
|
|
+#define BUSRP1_EXTCLOCK_ONE_TO_THREE 0x00020000
|
|
+/** 1/4 of ebu_clk frequency (default after reset). */
|
|
+#define BUSRP1_EXTCLOCK_ONE_TO_FOUR 0x00030000
|
|
+/** Data Hold Cycles For read Accesses
|
|
+ Number of data hold cycles during read accesses. Applies to spinner support only where the address is guaranteed stable for datac clocks after RD high */
|
|
+#define BUSRP1_DATAC_MASK 0x0000F000
|
|
+/** field offset */
|
|
+#define BUSRP1_DATAC_OFFSET 12
|
|
+/** Programmed Wait States for read accesses
|
|
+ Number of programmed wait states for read accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */
|
|
+#define BUSRP1_WAITRDC_MASK 0x00000F80
|
|
+/** field offset */
|
|
+#define BUSRP1_WAITRDC_OFFSET 7
|
|
+/** Recovery Cycles After read Accesses, same CS
|
|
+ Number of idle cycles after read accesses when the next access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */
|
|
+#define BUSRP1_RECOVC_MASK 0x00000070
|
|
+/** field offset */
|
|
+#define BUSRP1_RECOVC_OFFSET 4
|
|
+/** Recovery Cycles After read Accesses, other CS
|
|
+ Number of idle cycles after read accesses when the next access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */
|
|
+#define BUSRP1_DTACS_MASK 0x0000000F
|
|
+/** field offset */
|
|
+#define BUSRP1_DTACS_OFFSET 0
|
|
+
|
|
+/* Fields of "Bus Write Configuration Register1" */
|
|
+/** Device Type For Region
|
|
+ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */
|
|
+#define BUSWCON1_AGEN_MASK 0xF0000000
|
|
+/** field offset */
|
|
+#define BUSWCON1_AGEN_OFFSET 28
|
|
+/** Muxed Asynchronous Type External Memory */
|
|
+#define BUSWCON1_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000
|
|
+/** Muxed Burst Type External Memory */
|
|
+#define BUSWCON1_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000
|
|
+/** NAND Flash (page optimised) */
|
|
+#define BUSWCON1_AGEN_NAND_FLASH 0x20000000
|
|
+/** Muxed Cellular RAM External Memory */
|
|
+#define BUSWCON1_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000
|
|
+/** Demuxed Asynchronous Type External Memory */
|
|
+#define BUSWCON1_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000
|
|
+/** Demuxed Burst Type External Memory */
|
|
+#define BUSWCON1_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000
|
|
+/** Demuxed Page Mode External Memory */
|
|
+#define BUSWCON1_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000
|
|
+/** Demuxed Cellular RAM External Memory */
|
|
+#define BUSWCON1_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000
|
|
+/** Serial Flash */
|
|
+#define BUSWCON1_AGEN_SERIAL_FLASH 0xF0000000
|
|
+/** Device Addressing Mode
|
|
+ t.b.d. */
|
|
+#define BUSWCON1_PORTW_MASK 0x0C000000
|
|
+/** field offset */
|
|
+#define BUSWCON1_PORTW_OFFSET 26
|
|
+/** External Wait Control
|
|
+ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */
|
|
+#define BUSWCON1_WAIT_MASK 0x03000000
|
|
+/** field offset */
|
|
+#define BUSWCON1_WAIT_OFFSET 24
|
|
+/** WAIT is ignored (default after reset). */
|
|
+#define BUSWCON1_WAIT_OFF 0x00000000
|
|
+/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */
|
|
+#define BUSWCON1_WAIT_EARLY_WAIT 0x01000000
|
|
+/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */
|
|
+#define BUSWCON1_WAIT_TWO_STAGE_SYNC 0x01000000
|
|
+/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */
|
|
+#define BUSWCON1_WAIT_WAIT_WITH_DATA 0x02000000
|
|
+/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */
|
|
+#define BUSWCON1_WAIT_SINGLE_STAGE_SYNC 0x02000000
|
|
+/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */
|
|
+#define BUSWCON1_WAIT_ABORT_AND_RETRY 0x03000000
|
|
+/** Reserved */
|
|
+#define BUSWCON1_LOCKCS 0x00800000
|
|
+/** Reversed polarity at wait */
|
|
+#define BUSWCON1_WAITINV 0x00400000
|
|
+/* Low active.
|
|
+#define BUSWCON1_WAITINV_ACTLOW 0x00000000 */
|
|
+/** High active */
|
|
+#define BUSWCON1_WAITINV_ACTHI 0x00400000
|
|
+/** Early ADV Enable for Synchronous Bursts */
|
|
+#define BUSWCON1_EBSE 0x00200000
|
|
+/* Low active.
|
|
+#define BUSWCON1_EBSE_DELAYED 0x00000000 */
|
|
+/** High active */
|
|
+#define BUSWCON1_EBSE_NOT_DELAYED 0x00200000
|
|
+/** Early Control Signals for Synchronous Bursts */
|
|
+#define BUSWCON1_ECSE 0x00100000
|
|
+/* Low active.
|
|
+#define BUSWCON1_ECSE_DELAYED 0x00000000 */
|
|
+/** High active */
|
|
+#define BUSWCON1_ECSE_NOT_DELAYED 0x00100000
|
|
+/** Synchronous Burst Buffer Mode Select */
|
|
+#define BUSWCON1_FBBMSEL 0x00080000
|
|
+/* FIXED_LENGTH
|
|
+#define BUSWCON1_FBBMSEL_FIXED_LENGTH 0x00000000 */
|
|
+/** CONTINUOUS */
|
|
+#define BUSWCON1_FBBMSEL_CONTINUOUS 0x00080000
|
|
+/** Burst Length for Synchronous Burst */
|
|
+#define BUSWCON1_FETBLEN_MASK 0x00070000
|
|
+/** field offset */
|
|
+#define BUSWCON1_FETBLEN_OFFSET 16
|
|
+/** Up to 1 data cycle (default after reset). */
|
|
+#define BUSWCON1_FETBLEN_SINGLE 0x00000000
|
|
+/** Up to 2 data cycles. */
|
|
+#define BUSWCON1_FETBLEN_BURST2 0x00010000
|
|
+/** Up to 4 data cycles. */
|
|
+#define BUSWCON1_FETBLEN_BURST4 0x00020000
|
|
+/** Up to 8 data cycles. */
|
|
+#define BUSWCON1_FETBLEN_BURST8 0x00030000
|
|
+/** Up to 16 data cycles. */
|
|
+#define BUSWCON1_FETBLEN_BURST16 0x00040000
|
|
+/** Reserved
|
|
+ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */
|
|
+#define BUSWCON1_NANDAMAP_MASK 0x0000C000
|
|
+/** field offset */
|
|
+#define BUSWCON1_NANDAMAP_OFFSET 14
|
|
+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
|
|
+#define BUSWCON1_NANDAMAP_NAND_A17_16 0x00000000
|
|
+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */
|
|
+#define BUSWCON1_NANDAMAP_NAND_WAIT_ADV 0x00004000
|
|
+/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */
|
|
+#define BUSWCON1_NANDAMAP_NAND_AD9_8 0x00008000
|
|
+/** Reserved for future use. Do not use or unpredictable results may occur. */
|
|
+#define BUSWCON1_NANDAMAP_NAND_RFU 0x0000C000
|
|
+/** AAD-mux Protocol
|
|
+ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */
|
|
+#define BUSWCON1_AADMUX 0x00002000
|
|
+/* Muxed device is write accessed in AD-mux mode.
|
|
+#define BUSWCON1_AADMUX_AD_MUX 0x00000000 */
|
|
+/** Muxed device is write accessed in AAD-mux mode. */
|
|
+#define BUSWCON1_AADMUX_AAD_MUX 0x00002000
|
|
+/** Asynchronous Address Phase */
|
|
+#define BUSWCON1_AAP 0x00001000
|
|
+/* Clock is enabled at beginning of access.
|
|
+#define BUSWCON1_AAP_EARLY 0x00000000 */
|
|
+/** Clock is enabled after address phase. */
|
|
+#define BUSWCON1_AAP_LATE 0x00001000
|
|
+/** Auxiliary Chip Select Enable
|
|
+ Not supported in GPON-EBU, field must be set to 0. */
|
|
+#define BUSWCON1_CSA 0x00000200
|
|
+/* Disable
|
|
+#define BUSWCON1_CSA_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define BUSWCON1_CSA_EN 0x00000200
|
|
+/** Flash Non-Array Access Enable
|
|
+ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */
|
|
+#define BUSWCON1_NAA 0x00000100
|
|
+/* Disable
|
|
+#define BUSWCON1_NAA_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define BUSWCON1_NAA_EN 0x00000100
|
|
+/** Module Enable */
|
|
+#define BUSWCON1_ENABLE 0x00000001
|
|
+/* Disable
|
|
+#define BUSWCON1_ENABLE_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define BUSWCON1_ENABLE_EN 0x00000001
|
|
+
|
|
+/* Fields of "Bus Write Parameters Register1" */
|
|
+/** Address Cycles
|
|
+ Number of cycles for address phase. */
|
|
+#define BUSWP1_ADDRC_MASK 0xF0000000
|
|
+/** field offset */
|
|
+#define BUSWP1_ADDRC_OFFSET 28
|
|
+/** Address Hold Cycles For Multiplexed Address
|
|
+ Number of address hold cycles during multiplexed accesses. */
|
|
+#define BUSWP1_ADHOLC_MASK 0x0F000000
|
|
+/** field offset */
|
|
+#define BUSWP1_ADHOLC_OFFSET 24
|
|
+/** Programmed Command Delay Cycles
|
|
+ Number of delay cycles during command delay phase. */
|
|
+#define BUSWP1_CMDDELAY_MASK 0x00F00000
|
|
+/** field offset */
|
|
+#define BUSWP1_CMDDELAY_OFFSET 20
|
|
+/** Extended Data */
|
|
+#define BUSWP1_EXTDATA_MASK 0x000C0000
|
|
+/** field offset */
|
|
+#define BUSWP1_EXTDATA_OFFSET 18
|
|
+/** External device outputs data every BFCLK cycle */
|
|
+#define BUSWP1_EXTDATA_ONE 0x00000000
|
|
+/** External device outputs data every 2nd BFCLK cycles */
|
|
+#define BUSWP1_EXTDATA_TWO 0x00040000
|
|
+/** External device outputs data every 4th BFCLK cycles */
|
|
+#define BUSWP1_EXTDATA_FOUR 0x00080000
|
|
+/** External device outputs data every 8th BFCLK cycles */
|
|
+#define BUSWP1_EXTDATA_EIGHT 0x000C0000
|
|
+/** Frequency of external clock at pin BFCLKO */
|
|
+#define BUSWP1_EXTCLOCK_MASK 0x00030000
|
|
+/** field offset */
|
|
+#define BUSWP1_EXTCLOCK_OFFSET 16
|
|
+/** Equal to ebu_clk frequency. */
|
|
+#define BUSWP1_EXTCLOCK_ONE_TO_ONE 0x00000000
|
|
+/** 1/2 of ebu_clk frequency. */
|
|
+#define BUSWP1_EXTCLOCK_ONE_TO_TWO 0x00010000
|
|
+/** 1/3 of ebu_clk frequency. */
|
|
+#define BUSWP1_EXTCLOCK_ONE_TO_THREE 0x00020000
|
|
+/** 1/4 of ebu_clk frequency (default after reset). */
|
|
+#define BUSWP1_EXTCLOCK_ONE_TO_FOUR 0x00030000
|
|
+/** Data Hold Cycles For write Accesses
|
|
+ Number of data hold cycles during write accesses. */
|
|
+#define BUSWP1_DATAC_MASK 0x0000F000
|
|
+/** field offset */
|
|
+#define BUSWP1_DATAC_OFFSET 12
|
|
+/** Programmed Wait States For write Accesses
|
|
+ Number of programmed wait states for write accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */
|
|
+#define BUSWP1_WAITWDC_MASK 0x00000F80
|
|
+/** field offset */
|
|
+#define BUSWP1_WAITWDC_OFFSET 7
|
|
+/** Recovery Cycles After write Accesses, same CS
|
|
+ Number of idle cycles after write accesses when following access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */
|
|
+#define BUSWP1_RECOVC_MASK 0x00000070
|
|
+/** field offset */
|
|
+#define BUSWP1_RECOVC_OFFSET 4
|
|
+/** Recovery Cycles After write Accesses, other CS
|
|
+ Number of idle cycles after write accesses when the following access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */
|
|
+#define BUSWP1_DTACS_MASK 0x0000000F
|
|
+/** field offset */
|
|
+#define BUSWP1_DTACS_OFFSET 0
|
|
+
|
|
+/* Fields of "Bus Protocol Configuration Extension Register 0" */
|
|
+/** Byte Control Mapping
|
|
+ Remapping of byte enable signals on address lines is not supported in the GPON-EBU. */
|
|
+#define BUSCONEXT0_BCMAP_MASK 0x00030000
|
|
+/** field offset */
|
|
+#define BUSCONEXT0_BCMAP_OFFSET 16
|
|
+/** No mirroring of byte enables. */
|
|
+#define BUSCONEXT0_BCMAP_NOBCMAP 0x00000000
|
|
+/** Asynchronous Early Write
|
|
+ This bit is obsolete and must be set to 0 or unpredictable results may result. */
|
|
+#define BUSCONEXT0_AEW 0x00008000
|
|
+/** AAD-mux Consecutive Address Cycles
|
|
+ This bit selects whether ADV gets deasserted between the high and the low address phase of a synchronous AAD-mux access or the two address cycles are consecutive. See Figure 32 for a waveform example that results when acac is set. acac only takes effect if the CS region is configured for synchronous AADmux access (agen = 1 or 3, aadmux = 1) and is ignored otherwise. */
|
|
+#define BUSCONEXT0_ACAC 0x00004000
|
|
+/* ADV is deasserted between high and low address phase.
|
|
+#define BUSCONEXT0_ACAC_SEPERATED 0x00000000 */
|
|
+/** ADV is not deasserted between high and low address phase. */
|
|
+#define BUSCONEXT0_ACAC_CONSECUTIVE 0x00004000
|
|
+/** AAD-mux Write Address-to-Address Delay
|
|
+ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when writing to the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSWCON, fields agen and aadmux. */
|
|
+#define BUSCONEXT0_WAAC_MASK 0x00003800
|
|
+/** field offset */
|
|
+#define BUSCONEXT0_WAAC_OFFSET 11
|
|
+/** AAD-mux Read Address-to-Address Delay
|
|
+ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when reading from the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSRCON, fields agen and aadmux. */
|
|
+#define BUSCONEXT0_RAAC_MASK 0x00000700
|
|
+/** field offset */
|
|
+#define BUSCONEXT0_RAAC_OFFSET 8
|
|
+/** AAD-mux Paging Enable for CS0
|
|
+ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field selects whether or not to use paging. If paging is enabled, the EBU skips the high address cycle in case the upper address that would be sent are the same as in the most recent access to the device.configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */
|
|
+#define BUSCONEXT0_PAGE_EN 0x00000080
|
|
+/* Disable
|
|
+#define BUSCONEXT0_PAGE_EN_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define BUSCONEXT0_PAGE_EN_EN 0x00000080
|
|
+/** AAD-mux Address Extension Bit Generation Mode
|
|
+ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */
|
|
+#define BUSCONEXT0_AEBM_MASK 0x00000070
|
|
+/** field offset */
|
|
+#define BUSCONEXT0_AEBM_OFFSET 4
|
|
+/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 0 */
|
|
+#define BUSCONEXT0_AEBM_AMAP_CRE_RFU0 0x00000000
|
|
+/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 1 */
|
|
+#define BUSCONEXT0_AEBM_AMAP_CRE_RFU1 0x00000010
|
|
+/** A[15] in the high address cycle is set to AMemport[amsb+18], A[14] is set to AMemport[amsb+17] */
|
|
+#define BUSCONEXT0_AEBM_AMAP_CRE_AND_RFU 0x00000020
|
|
+/** Do not use */
|
|
+#define BUSCONEXT0_AEBM_reserved 0x00000030
|
|
+/** A[15:14] in the high address cycle is set to 00B. */
|
|
+#define BUSCONEXT0_AEBM_DIRECT_00 0x00000040
|
|
+/** A[15:14] in the high address cycle is set to 01B */
|
|
+#define BUSCONEXT0_AEBM_DIRECT_01 0x00000050
|
|
+/** A[15:14] in the high address cycle is set to 10B */
|
|
+#define BUSCONEXT0_AEBM_DIRECT_10 0x00000060
|
|
+/** A[15:14] in the high address cycle is set to 11B. */
|
|
+#define BUSCONEXT0_AEBM_DIRECT_11 0x00000070
|
|
+/** Most Significant Address Bit of External Device
|
|
+ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then for amsb < 14 the EBU always sets A[13:amsb] = 0 in the high address cycle of an access. The value of A[15:14] is defined in field aebm. A value of amsb > 13 therefore has no effect. It is recommended to set amsb that it matches the addressable range of the external device according to the following formula: amsb = n - 16 for a device with 2n addressable words. */
|
|
+#define BUSCONEXT0_AMSB_MASK 0x0000000F
|
|
+/** field offset */
|
|
+#define BUSCONEXT0_AMSB_OFFSET 0
|
|
+
|
|
+/* Fields of "Bus Protocol Configuration Extension Register 1" */
|
|
+/** Byte Control Mapping
|
|
+ Remapping of byte enable signals on address lines is not supported in the GPON-EBU. */
|
|
+#define BUSCONEXT1_BCMAP_MASK 0x00030000
|
|
+/** field offset */
|
|
+#define BUSCONEXT1_BCMAP_OFFSET 16
|
|
+/** No mirroring of byte enables. */
|
|
+#define BUSCONEXT1_BCMAP_NOBCMAP 0x00000000
|
|
+/** Asynchronous Early Write
|
|
+ This bit is obsolete and must be set to 0 or unpredictable results may result. */
|
|
+#define BUSCONEXT1_AEW 0x00008000
|
|
+/** AAD-mux Consecutive Address Cycles
|
|
+ This bit selects whether ADV gets deasserted between the high and the low address phase of a synchronous AAD-mux access or the two address cycles are consecutive. See Figure 32 for a waveform example that results when acac is set. acac only takes effect if the CS region is configured for synchronous AADmux access (agen = 1 or 3, aadmux = 1) and is ignored otherwise. */
|
|
+#define BUSCONEXT1_ACAC 0x00004000
|
|
+/* ADV is deasserted between high and low address phase.
|
|
+#define BUSCONEXT1_ACAC_SEPERATED 0x00000000 */
|
|
+/** ADV is not deasserted between high and low address phase. */
|
|
+#define BUSCONEXT1_ACAC_CONSECUTIVE 0x00004000
|
|
+/** AAD-mux Write Address-to-Address Delay
|
|
+ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when writing to the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSWCON, fields agen and aadmux. */
|
|
+#define BUSCONEXT1_WAAC_MASK 0x00003800
|
|
+/** field offset */
|
|
+#define BUSCONEXT1_WAAC_OFFSET 11
|
|
+/** AAD-mux Read Address-to-Address Delay
|
|
+ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when reading from the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSRCON, fields agen and aadmux. */
|
|
+#define BUSCONEXT1_RAAC_MASK 0x00000700
|
|
+/** field offset */
|
|
+#define BUSCONEXT1_RAAC_OFFSET 8
|
|
+/** AAD-mux Paging Enable for CS0
|
|
+ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field selects whether or not to use paging. If paging is enabled, the EBU skips the high address cycle in case the upper address that would be sent are the same as in the most recent access to the device.configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */
|
|
+#define BUSCONEXT1_PAGE_EN 0x00000080
|
|
+/* Disable
|
|
+#define BUSCONEXT1_PAGE_EN_DIS 0x00000000 */
|
|
+/** Enable */
|
|
+#define BUSCONEXT1_PAGE_EN_EN 0x00000080
|
|
+/** AAD-mux Address Extension Bit Generation Mode
|
|
+ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */
|
|
+#define BUSCONEXT1_AEBM_MASK 0x00000070
|
|
+/** field offset */
|
|
+#define BUSCONEXT1_AEBM_OFFSET 4
|
|
+/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 0 */
|
|
+#define BUSCONEXT1_AEBM_AMAP_CRE_RFU0 0x00000000
|
|
+/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 1 */
|
|
+#define BUSCONEXT1_AEBM_AMAP_CRE_RFU1 0x00000010
|
|
+/** A[15] in the high address cycle is set to AMemport[amsb+18], A[14] is set to AMemport[amsb+17] */
|
|
+#define BUSCONEXT1_AEBM_AMAP_CRE_AND_RFU 0x00000020
|
|
+/** Do not use */
|
|
+#define BUSCONEXT1_AEBM_reserved 0x00000030
|
|
+/** A[15:14] in the high address cycle is set to 00B. */
|
|
+#define BUSCONEXT1_AEBM_DIRECT_00 0x00000040
|
|
+/** A[15:14] in the high address cycle is set to 01B */
|
|
+#define BUSCONEXT1_AEBM_DIRECT_01 0x00000050
|
|
+/** A[15:14] in the high address cycle is set to 10B */
|
|
+#define BUSCONEXT1_AEBM_DIRECT_10 0x00000060
|
|
+/** A[15:14] in the high address cycle is set to 11B. */
|
|
+#define BUSCONEXT1_AEBM_DIRECT_11 0x00000070
|
|
+/** Most Significant Address Bit of External Device
|
|
+ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then for amsb < 14 the EBU always sets A[13:amsb] = 0 in the high address cycle of an access. The value of A[15:14] is defined in field aebm. A value of amsb > 13 therefore has no effect. It is recommended to set amsb that it matches the addressable range of the external device according to the following formula: amsb = n - 16 for a device with 2n addressable words. */
|
|
+#define BUSCONEXT1_AMSB_MASK 0x0000000F
|
|
+/** field offset */
|
|
+#define BUSCONEXT1_AMSB_OFFSET 0
|
|
+
|
|
+/* Fields of "Serial Flash Configuration Register" */
|
|
+/** Direct Access Device Port Width
|
|
+ DA_PORTW Defines the number of signal lines to be used with direct read access from a Serial Flash as defined for the command with opcode rd_opc. Depending on thedevice type and/or command, the number of used signal lines might differbetween command, address, and data phase of the transaction. */
|
|
+#define SFCON_DA_PORTW_MASK 0xE0000000
|
|
+/** field offset */
|
|
+#define SFCON_DA_PORTW_OFFSET 29
|
|
+/** One signal line used in all phases of the transaction. */
|
|
+#define SFCON_DA_PORTW_WIDTH_1_1_1 0x00000000
|
|
+/** One signal line used in the COMMAND and ADDRESS phase of the transaction and two signal lines used in the DATA phase. */
|
|
+#define SFCON_DA_PORTW_WIDTH_1_1_2 0x20000000
|
|
+/** One signal used in the COMMAND phase of the transaction and two signal lines used in the ADDRESS/DUMMY phase and the DATA phase. */
|
|
+#define SFCON_DA_PORTW_WIDTH_1_2_2 0x40000000
|
|
+/** Two signal lines used in all phases of the transaction. */
|
|
+#define SFCON_DA_PORTW_WIDTH_2_2_2 0x60000000
|
|
+/** One signal line used in the COMMAND and ADDRESS phase of the transaction and four signal lines used in the DATA phase. */
|
|
+#define SFCON_DA_PORTW_WIDTH_1_1_4 0x80000000
|
|
+/** One signal used in the COMMAND phase of the transaction and four signal lines used in the ADDRESS/DUMMY phase and the DATA phase. */
|
|
+#define SFCON_DA_PORTW_WIDTH_1_4_4 0xA0000000
|
|
+/** Four signal lines used in all phases of the transaction. */
|
|
+#define SFCON_DA_PORTW_WIDTH_4_4_4 0xC0000000
|
|
+/** for future use. */
|
|
+#define SFCON_DA_PORTW_WIDTH_reserved 0xE0000000
|
|
+/** Read Abort Enable
|
|
+ If set, a read access from the external device can be aborted via signal sf_rd_abort_i. See Section 3.18.2.9 for details. */
|
|
+#define SFCON_RD_ABORT_EN 0x10000000
|
|
+/** Device Size
|
|
+ Defines the number of significant address bits for the Serial Flash device(s). All address bits above the MSB are forced to 0. The configuration in this field also defines for the address auto-increment feature when to wrap around from the upper most address to 0. */
|
|
+#define SFCON_DEV_SIZE_MASK 0x0F000000
|
|
+/** field offset */
|
|
+#define SFCON_DEV_SIZE_OFFSET 24
|
|
+/** 16 MBit device */
|
|
+#define SFCON_DEV_SIZE_A20_0 0x00000000
|
|
+/** 32 MBit device */
|
|
+#define SFCON_DEV_SIZE_A21_0 0x01000000
|
|
+/** 64 MBit device */
|
|
+#define SFCON_DEV_SIZE_A22_0 0x02000000
|
|
+/** 128 MBit device */
|
|
+#define SFCON_DEV_SIZE_A23_0 0x03000000
|
|
+/** 256 MBit device */
|
|
+#define SFCON_DEV_SIZE_A24_0 0x04000000
|
|
+/** 512 MBit device */
|
|
+#define SFCON_DEV_SIZE_A25_0 0x05000000
|
|
+/** 1 GBit device */
|
|
+#define SFCON_DEV_SIZE_A26_0 0x06000000
|
|
+/** 2 GBit device */
|
|
+#define SFCON_DEV_SIZE_A27_0 0x07000000
|
|
+/** 4 GBit device */
|
|
+#define SFCON_DEV_SIZE_A28_0 0x08000000
|
|
+/** 8 GBit device */
|
|
+#define SFCON_DEV_SIZE_A29_0 0x09000000
|
|
+/** 16 GBit device */
|
|
+#define SFCON_DEV_SIZE_A30_0 0x0A000000
|
|
+/** 32 GBit device */
|
|
+#define SFCON_DEV_SIZE_A31_0 0x0B000000
|
|
+/** Device Page Size
|
|
+ Defines the page size employed by all connected Serial Flash devices. The device page size is used to determine the address wrap-around for the write address auto-increment feature. */
|
|
+#define SFCON_DPS_MASK 0x00C00000
|
|
+/** field offset */
|
|
+#define SFCON_DPS_OFFSET 22
|
|
+/** Device page size is 256 Bytes */
|
|
+#define SFCON_DPS_DPS_256 0x00000000
|
|
+/** Device page size is 512 Bytes */
|
|
+#define SFCON_DPS_DPS_512 0x00400000
|
|
+/** Page Buffer Size
|
|
+ Defines the size of the EBU's page buffer used in Buffered Access. Page buffer size configured here must be less than or equal to the maximum page buffer size which is a built option of the EBU (256 Bytes for GPON). */
|
|
+#define SFCON_PB_SIZE_MASK 0x00300000
|
|
+/** field offset */
|
|
+#define SFCON_PB_SIZE_OFFSET 20
|
|
+/** No read buffer is available/used. */
|
|
+#define SFCON_PB_SIZE_NONE 0x00000000
|
|
+/** 128 Bytes */
|
|
+#define SFCON_PB_SIZE_SIZE_128 0x00100000
|
|
+/** 256 Bytes */
|
|
+#define SFCON_PB_SIZE_SIZE_256 0x00200000
|
|
+/** Bidirectional Data Bus
|
|
+ Defines whether the Serial Flash uses a unidirectional or a bidirectional data bus. */
|
|
+#define SFCON_BIDIR 0x00080000
|
|
+/* The Serial Flash interface uses a pair of two unidirectional busses (one for write, one for read)
|
|
+#define SFCON_BIDIR_UNIDIRECTIONAL 0x00000000 */
|
|
+/** The Serial Flash interface uses a bidirectional data bus. */
|
|
+#define SFCON_BIDIR_BIDIRECTIONAL 0x00080000
|
|
+/** No Busy Error termination
|
|
+ By default, the EBU error-terminates all direct access to a Serial Flash while EBU_SFSTAT.busy is set. By setting NO_BUSY_ERR, the EBU can be configured to permit direct accesses to proceed to the Serial Flash, e.g. for devices that support a read-while-write functionality. */
|
|
+#define SFCON_NO_BUSY_ERR 0x00040000
|
|
+/** End-of-Busy Detection Mode
|
|
+ Defines how the EBU detects the end of a busy phase in the Serial Flash device. The current version of the EBU requires the software to explicitly poll the device's status register and then inform the EBU on the end of the busy status by clearing the corresponding bit in register EBU_SF_STAT. */
|
|
+#define SFCON_EOBDM_MASK 0x00030000
|
|
+/** field offset */
|
|
+#define SFCON_EOBDM_OFFSET 16
|
|
+/** No read buffer is available/used. */
|
|
+#define SFCON_EOBDM_SOFTWARE 0x00000000
|
|
+/** Poll device status register (not supported yet) */
|
|
+#define SFCON_EOBDM_POLL_SR 0x00010000
|
|
+/** Poll devices busy/ready pin fed into EBU via WAIT pin (not supported yet). */
|
|
+#define SFCON_EOBDM_POLL_RDY 0x00020000
|
|
+/** Same as POLL_RDY, but CS must be asserted to have the device output its busy/ready status (not supported yet). */
|
|
+#define SFCON_EOBDM_POLL_RDY_WITH_CS 0x00030000
|
|
+/** Direct Access Keep Chip Select
|
|
+ Defines whether the Serial Flash remains selected after a direct access transaction has been finished. */
|
|
+#define SFCON_DA_KEEP_CS 0x00008000
|
|
+/* After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address.
|
|
+#define SFCON_DA_KEEP_CS_DESELECT 0x00000000 */
|
|
+/** Chip Select of device is kept active after direct read access so that device is ready for follow-up read of next sequential byte without the need to send command and address. If the next command is to another Chip Select, is a different command or accesses a different address, the EBU first deactivates the kept Chip Select before it starts the new transaction with sending the command opcode and address. */
|
|
+#define SFCON_DA_KEEP_CS_KEEP_SELECTED 0x00008000
|
|
+/** Early Read Abort Enable
|
|
+ When aborting a Serial Flash Read is enabled in bit EBU_SFCON.rd_abort_en, bit early_abort selects at what point in the protocol an external access might be aborted. Datasheets of many Serial Flash devices are not explicit on what happens (and whether it is allowed) when a read access is cut-short by deselecting the device during the CMD, ADDR or DUMMY phase of the protocol. */
|
|
+#define SFCON_EARLY_ABORT 0x00004000
|
|
+/* DISABLE Early abortion is disabled (default after reset). Once the EBU has started the access on the External Bus (first bit time slot), the EBU continues the external transfer until the first data byte has been received. After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address.
|
|
+#define SFCON_EARLY_ABORT_DISABLE 0x00000000 */
|
|
+/** Early abortion is not yet supported in the current version of the EBU. Do not use. The feature is a late improvement to the EBU and could not be verified completely before the final release. After proven to work, it should be made officially available to reduce access latency after aborted Serial Flash reads. Setting early_abort to ENABLE alters the read abort handling in the following way: Once the EBU has started the access on the External Bus, the transfer is cut-short after transferring the CMD byte, the three address bytes, any DUMMY bits or at the end of the next data byte - whatever comes first. */
|
|
+#define SFCON_EARLY_ABORT_ENABLE 0x00004000
|
|
+/** Direct Access Address Length
|
|
+ Defines the number of address bytes to be sent (MSB first) to the device with a direct read access transaction. Other values than listed below are not supported and have unpredictable results. */
|
|
+#define SFCON_DA_ALEN_MASK 0x00003000
|
|
+/** field offset */
|
|
+#define SFCON_DA_ALEN_OFFSET 12
|
|
+/** 3 address bytes (bits 23:0 of the internal address) */
|
|
+#define SFCON_DA_ALEN_THREE 0x00000000
|
|
+/** Read Access Dummy Bytes
|
|
+ This field defines the number of dummy bytes to send between the last address byte before the EBU starts capturing read data from the bus for a direct read access. The number of dummy bytes depends on the data access command being used (see field), the clock frequency and the type of device being used. */
|
|
+#define SFCON_RD_DUMLEN_MASK 0x00000F00
|
|
+/** field offset */
|
|
+#define SFCON_RD_DUMLEN_OFFSET 8
|
|
+/** Direct Read Access Command Opcode
|
|
+ This byte defines the command opcode to send when performing a data read from the Serial Flash in Direct Access Mode. Any value can be set (the EBU does not interpret the value, but directly uses the contents of this register field in the command phase of the transaction). Common opcodes to be used and understood by most devices are READ (03H) and FAST_READ (0BH), but some devices might provide additional opcodes, e.g. to support higher clock frequencies requiring additional dummy bytes or to define a wider interface bus. */
|
|
+#define SFCON_RD_OPC_MASK 0x000000FF
|
|
+/** field offset */
|
|
+#define SFCON_RD_OPC_OFFSET 0
|
|
+/** READ */
|
|
+#define SFCON_RD_OPC_READ 0x00000003
|
|
+/** FAST_READ */
|
|
+#define SFCON_RD_OPC_FAST_READ 0x0000000B
|
|
+
|
|
+/* Fields of "Serial Flash Timing Register" */
|
|
+/** CS Idle time
|
|
+ This field defines the minimum time the device's Chip Select has to be deasserted in between accesses. Most devices require a minimum deselect time between 50 and 100 ns. See Table 43 for the encoding used in this field. */
|
|
+#define SFTIME_CS_IDLE_MASK 0xF0000000
|
|
+/** field offset */
|
|
+#define SFTIME_CS_IDLE_OFFSET 28
|
|
+/** 1 EBU clock cycles */
|
|
+#define SFTIME_CS_IDLE_CLKC_0 0x00000000
|
|
+/** 2 EBU clock cycles */
|
|
+#define SFTIME_CS_IDLE_CLKC_1 0x10000000
|
|
+/** 3 EBU clock cycles */
|
|
+#define SFTIME_CS_IDLE_CLKC_2 0x20000000
|
|
+/** 4 EBU clock cycles */
|
|
+#define SFTIME_CS_IDLE_CLKC_3 0x30000000
|
|
+/** 6 EBU clock cycles */
|
|
+#define SFTIME_CS_IDLE_CLKC_4 0x40000000
|
|
+/** 8 EBU clock cycles */
|
|
+#define SFTIME_CS_IDLE_CLKC_5 0x50000000
|
|
+/** 10 EBU clock cycles */
|
|
+#define SFTIME_CS_IDLE_CLKC_6 0x60000000
|
|
+/** 12 EBU clock cycles */
|
|
+#define SFTIME_CS_IDLE_CLKC_7 0x70000000
|
|
+/** 14 EBU clock cycles */
|
|
+#define SFTIME_CS_IDLE_CLKC_8 0x80000000
|
|
+/** 16 EBU clock cycles */
|
|
+#define SFTIME_CS_IDLE_CLKC_9 0x90000000
|
|
+/** 20 EBU clock cycles */
|
|
+#define SFTIME_CS_IDLE_CLKC_10 0xA0000000
|
|
+/** 24 EBU clock cycles */
|
|
+#define SFTIME_CS_IDLE_CLKC_11 0xB0000000
|
|
+/** 32 EBU clock cycles */
|
|
+#define SFTIME_CS_IDLE_CLKC_12 0xC0000000
|
|
+/** 40 EBU clock cycles */
|
|
+#define SFTIME_CS_IDLE_CLKC_13 0xD0000000
|
|
+/** 48 EBU clock cycles */
|
|
+#define SFTIME_CS_IDLE_CLKC_14 0xE0000000
|
|
+/** 64 EBU clock cycles */
|
|
+#define SFTIME_CS_IDLE_CLKC_15 0xF0000000
|
|
+/** CS Hold time
|
|
+ This field defines (in multiples of the EBU internal clock's period) the minimum time the device's Chip Select must remain asserted after transfer of the last bit of a write transaction. This CS hold time does not apply to read accesses */
|
|
+#define SFTIME_CS_HOLD_MASK 0x0C000000
|
|
+/** field offset */
|
|
+#define SFTIME_CS_HOLD_OFFSET 26
|
|
+/** CS Setup time
|
|
+ This field defines (in multiples of the EBU internal clock's period) when to assert the device's Chip Select before the first SCK clock period for transferring the command is started on the External Bus */
|
|
+#define SFTIME_CS_SETUP_MASK 0x03000000
|
|
+/** field offset */
|
|
+#define SFTIME_CS_SETUP_OFFSET 24
|
|
+/** Write-to-Read Pause
|
|
+ This field defines the length of the optional pause when switching from write to read direction in the transaction. During this pause, SCK is held stable. */
|
|
+#define SFTIME_WR2RD_PAUSE_MASK 0x00300000
|
|
+/** field offset */
|
|
+#define SFTIME_WR2RD_PAUSE_OFFSET 20
|
|
+/** Read Data Position
|
|
+ This field defines when to capture valid read data bit(s) (in multiples of half of the EBU internal clock's period) relative to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. RD_POS must be less than or equal to EBU_SFTIME.sck_per (not checked in hardware) or unpredictable results may occur. */
|
|
+#define SFTIME_RD_POS_MASK 0x000F0000
|
|
+/** field offset */
|
|
+#define SFTIME_RD_POS_OFFSET 16
|
|
+/** SCK Fall-edge Position
|
|
+ This field defines the positioning of the SCK fall edge (in multiples of half of the EBU internal clock's period) with respect to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. SCKF_POS must be less than or equal to SCK_PER (not checked in hardware) or unpredictable results may occur. If EBU_SFTIME.sck_inv is set, SCKF_POS defines the positioning of the falling instead of the rising edge of SCK. In the current version of the EBU, SCKF_POS must be set 0 or unpredictable results may occur. */
|
|
+#define SFTIME_SCKF_POS_MASK 0x0000F000
|
|
+/** field offset */
|
|
+#define SFTIME_SCKF_POS_OFFSET 12
|
|
+/** SCK Rise-edge Position
|
|
+ This field defines the positioning of the SCK rise edge (in multiples of half of the EBU internal clock's period) with respect to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. SCKR_POS must be less than EBU_SFTIME.sck_per (not checked in hardware) or unpredictable results may occur. If EBU_SFTIME.sck_inv is set, SCKR_POS defines the positioning of the falling instead of the rising edge of SCK. */
|
|
+#define SFTIME_SCKR_POS_MASK 0x00000F00
|
|
+/** field offset */
|
|
+#define SFTIME_SCKR_POS_OFFSET 8
|
|
+/** SCK Feedback Clock Inversion
|
|
+ If set, read data gets captured with the falling instead of the rising edge of SCK if clock feedback is enabled in EBU_SFTIME.sck_fdbk_en. */
|
|
+#define SFTIME_SCK_FDBK_INV 0x00000040
|
|
+/** SCK Clock Feedback
|
|
+ If set, read data is captured using the external SCK clock feedback into the chip instead of the EBU's internal clock. Using the feedback clock compensate for the high delay over the pads and its use is required at higher frequencies. A penalty for synchronizing the read data from the SCK into the ebu_clk domain applies to the read access latency. */
|
|
+#define SFTIME_SCK_FDBK_EN 0x00000020
|
|
+/** Inverted SCK
|
|
+ If set, the clock to the Serial Flash devices is inverted. This also results in SCK high while a Serial Flash remains selected between transactions (keep_cs feature). In the current version of the EBU, clock inversion is not supported. SCK_INV must be set to 0 or unpredictable results may occur. */
|
|
+#define SFTIME_SCK_INV 0x00000010
|
|
+/** SCK Period
|
|
+ This field defines the period of the SCK clock in multiples of half of the EBU clock period. The EBU supports values between 2 and 14, corresponding to a frequency ratio range from 1:1. to 1:7 between SCK and the internal clock. Other values are prohibited and result in unpredictable behaviour. In the current version of the EBU, odd values for SCK_PER are not supported. */
|
|
+#define SFTIME_SCK_PER_MASK 0x0000000F
|
|
+/** field offset */
|
|
+#define SFTIME_SCK_PER_OFFSET 0
|
|
+
|
|
+/* Fields of "Serial Flash Status Register" */
|
|
+/** Command Overwrite Error
|
|
+ This bit is set on an attempt to start an indirect access while a previous indirect access has not finished. The bit remains unaltered when the software writes a '0' and is toggled when a '1' is written. This toggle-by-write-1 behavior allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit to clear after it has been set by the Serial Flash protocol engine. */
|
|
+#define SFSTAT_CMD_OVWRT_ERR 0x40000000
|
|
+/** Command Error
|
|
+ This bit is set when the EBU discards an indirect or direct access to/from a Serial Flash. The bit remains unaltered when the software writes a '0' and is toggled when a '1' is written. This toggle-by-write-1 behavior allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit to clear after it has been set by the Serial Flash protocol engine. */
|
|
+#define SFSTAT_CMD_ERR 0x20000000
|
|
+/** Access Command Pending
|
|
+ If set, indicates that access from/to a Serial Flash device has not finished yet. */
|
|
+#define SFSTAT_CMD_PEND 0x00400000
|
|
+/** External Device Selected
|
|
+ If set, indicates that the Chip Select of a Serial Flash device is currently active on the External Bus. */
|
|
+#define SFSTAT_SELECTED 0x00200000
|
|
+/** Protocol Engine Active
|
|
+ If set, indicates that the EBU's Serial Flash protocol engine is active. */
|
|
+#define SFSTAT_ACTIVE 0x00100000
|
|
+/** Page Buffer Invalidate
|
|
+ When writing a one to this bit, bits PB_VALID and PB_UPDATE are both cleared, thereby invalidating the page buffer for access to/from the Serial Flash device. After invalidating the buffer, PB_INVALID is automatically cleared so that it always reads as 0. */
|
|
+#define SFSTAT_PB_INVALID 0x00010000
|
|
+/** Page Buffer Update
|
|
+ This bit is set when data in the page buffer gets modified. It is cleared when new data gets loaded to the page buffer, when it is written back to the device (WRITE_PAGE command) or when PB_VALID gets cleared. */
|
|
+#define SFSTAT_PB_UPDATE 0x00002000
|
|
+/** Page Buffer Valid
|
|
+ This bit is set after the last data byte of a LOAD_PAGE command has been stored in the page buffer or when the page buffer is explicitely validated via a VALIDATE_PAGE special command. It remains set until the page buffer gets invalidated by writing a 1 to PB_INVALID or any of the LOAD_PAGE special commands. While PB_VALID is set, all accesses to the buffered address range are diverted to the page buffer with no access being performed on the External Bus. */
|
|
+#define SFSTAT_PB_VALID 0x00001000
|
|
+/** Page Buffer Busy
|
|
+ The bit is set when the EBU starts executing a LOAD_PAGE or a WRITE_PAGE command and cleared when the last byte of the requested page has been transferred from/to the external device. The inverted value of PB_BUSY is output on the EBU interface and may trigger a system interrupt. */
|
|
+#define SFSTAT_PB_BUSY 0x00000100
|
|
+/** Device Busy
|
|
+ This bit is set by the Serial Flash protocol engine when an indirect access is performed via register EBU_SFCMD with SET_BUSY being set. While busy is set, access to the Serial Flash is very limited and all transactions are error-terminated except when explicitly marked to ignore the busy status. If the EBU is configured in EBU_SFCON.EOBDM to automatically poll the busy status of the device, busy is cleared as soon as the device is found to be idle again. On a software write, busy remains unaltered when written with a '0' and is toggled when written with a '1', respectively.This toggle-by-write-1 behaviour allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit after it got set by the Serial Flash protocol engine and no automatic busy detection is configured in EBU_SFCON.EOBDM Then the software has to clear busy when it finds the device to be no longer busy by either polling the device's status register via the EBU or by waiting for the maximum busy time of the operation started in the device. */
|
|
+#define SFSTAT_BUSY 0x00000001
|
|
+
|
|
+/* Fields of "Serial Flash Command Register" */
|
|
+/** Command Type
|
|
+ This field is a qualifier of the command opcode in EBU_SFCMD.opc. Two types */
|
|
+#define SFCMD_CMDTYPE 0x80000000
|
|
+/* The opcode in EBU_SFCMD.opc is directly used in the command phase of a single transaction to the Serial Flash device.
|
|
+#define SFCMD_CMDTYPE_ACCESS_CMD 0x00000000 */
|
|
+/** The opcode in EBU_SFCMD.opc is used to start a special command in the Serial Flash Controller which might include any number of external transactions to/from the Serial Flash device. */
|
|
+#define SFCMD_CMDTYPE_SPECIAL_CMD 0x80000000
|
|
+/** Device Port Width
|
|
+ Defines the number of signal lines to be used with direct read access from a Serial Flash as defined for the command with opcode opc. The encoding of this field is the same as forDA_PORTW. */
|
|
+#define SFCMD_PORTW_MASK 0x70000000
|
|
+/** field offset */
|
|
+#define SFCMD_PORTW_OFFSET 28
|
|
+/** Bidirectional Signal Lines
|
|
+ If set selects bidirectional signal lines to be used for the data transfer. */
|
|
+#define SFCMD_BIDIR 0x08000000
|
|
+/** Chip Select
|
|
+ This field selects which of the EBU's Chip Selects to activated for the command that is written to EBU_SFCMD.opc. A value between 0 and 3 selects one of the EBU's main CSs while 4 to 7 chooses one of the Auxiliary Chip Selects CSA[3:0], respectively. */
|
|
+#define SFCMD_CS_MASK 0x07000000
|
|
+/** field offset */
|
|
+#define SFCMD_CS_OFFSET 24
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+/** Disable Auto Address Increment
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+ By default, the address in register EBU_SFADDR is automatically incremented with each data byte being transferred. By setting this bit, the auto-increment can be disabled. */
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+#define SFCMD_DIS_AAI 0x00800000
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+/** Address Length
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+ Defines the number of address bytes from register EBU_SFADDR to sent in the address phase of the transaction to/from the Serial Flash. Note: Address bytes are also sent when the command has no data. */
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+#define SFCMD_ALEN_MASK 0x00700000
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+/** field offset */
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+#define SFCMD_ALEN_OFFSET 20
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+/** Dummy Phase Length
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+ Defines the number of dummy bytes to send to the device between the command/address phase and the data phase of a transaction. Note:Dummy bytes are also sent when the command has no address and/or no data. */
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+#define SFCMD_DUMLEN_MASK 0x000F0000
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+/** field offset */
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+#define SFCMD_DUMLEN_OFFSET 16
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+/** Keep Chip Select
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+ Defines whether the Serial Flash remains selected after the indirect access transaction has been finished. */
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+#define SFCMD_KEEP_CS 0x00008000
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+/* After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address.
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+#define SFCMD_KEEP_CS_DESELECT 0x00000000 */
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+/** Chip Select of device is kept active after direct read access so that device is ready for follow-up read of next sequential byte without the need to send command and address. If the next command is to another Chip Select, is a different command or accesses a different address, the EBU first deactivates the kept Chip Select before it starts the new transaction with sending the command opcode and address. */
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+#define SFCMD_KEEP_CS_KEEP_SELECTED 0x00008000
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+/** Set Busy Flag
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+ If set, starting the command sets EBU_SFSTAT.busy. */
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+#define SFCMD_SET_BUSY 0x00004000
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+/** Ignore Busy
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+ By default, the EBU error terminates all attempts to access a Serial Flash while EBU_SFSTAT.busy is set. Setting this bit overrules this error termination and permits the command written to EBU_SFCMD.opc to proceed to the External Bus. Normally, this bit is only set to execute a Read Status Register command to the Serial Flash, but may also be used for any other type of access the device is able to handle while it is busy. */
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+#define SFCMD_IGNORE_BUSY 0x00002000
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+/** Skip Opcode
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+ If this bit is set, the opcode in field OPC is not sent to the External Bus, but the external transaction starts with sending the first address byte (if ALEN 0), the first dummy byte (if alen = 0 and DUMLEN 0), or directly with transferring the data bytes (if ALEN = DUMLEN = 0 and DLEN 0). Limiting the external transfer to just the data phase - together with the keep_cs feature - allow to transfer any number of data bytes for a device command sent via EBU_SFCMD by keeping the device selected between accesses and chaining multiple indirect access commands each transferring up to 4 data bytes from/to register EBU_SFDATA. */
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+#define SFCMD_SKIP_OPC 0x00001000
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+/** Data Length
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+ This field defines the number of data bytes to transfer in the data phase of the command. For a read command, the data bytes are stored in register EBU_SFDATA, for a write transfer they are taken from that register. As the data register can hold at most 4 bytes, DLEN is restricted to the range [0..4]. */
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+#define SFCMD_DLEN_MASK 0x00000E00
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+/** field offset */
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+#define SFCMD_DLEN_OFFSET 9
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+/** Direction
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+ Defines the direction of the data transfer (if any) in the data phase of the transaction to/from the serial bus. */
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+#define SFCMD_DIR 0x00000100
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+/* dlen bytes of data are read from the Serial Flash during the data phase of the transaction and stored in register EBU_SFDATA.
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+#define SFCMD_DIR_READ 0x00000000 */
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+/** dlen bytes of data are read from register EBU_SFDATA and written to the Serial Flash during the data phase of the transactione */
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+#define SFCMD_DIR_WRITE 0x00000100
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+/** Command Opcode
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+ A write access to this field starts an Indirect Access command in the EBU's Serial Flash controller. Two types of commands are supported (selected in EBU_SFCMD.cmdtype) and determine how the EBU interprets the opcode:- - For a ACCESS_CMD, a single transaction is executed to/from the Serial Flash device and the OPC is sent to the device in the command phase of the protocol. The number of address, dummy and data bytes to transfer with the command are given in fields ALEN, DUMLEN, and DLEN of register EBU_SFCMD, respectively. - For a SPECIAL_CMD, the EBU starts a complex operation that usually involves multiple transactions to/from the Serial Flash device. See Section 3.18.2.5 for an overview of the complex commands currently supported. */
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+#define SFCMD_OPC_MASK 0x000000FF
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+/** field offset */
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+#define SFCMD_OPC_OFFSET 0
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+
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+/* Fields of "Serial Flash Address Register" */
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+/** Address
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+ Before writing to register EBU_SFCMD to start a command that requires the transfer of an address, the address to use must be stored in this register. If not disabled in EBU_SFCMD.dis_aai, ADDR is incremented automatically with each data byte transferred between the EBU and the Serial Flash for an indirect access. Note:Register EBU_SFADDR is only used for access in Indirect Access Mode and is ignored/remains unaltered for all accesses in Direct Access Mode. */
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+#define SFADDR_ADDR_MASK 0xFFFFFFFF
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+/** field offset */
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+#define SFADDR_ADDR_OFFSET 0
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+
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+/* Fields of "Serial Flash Data Register" */
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+/** Data Bytes
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+ Before writing to register EBU_SFCMD to start a command that requires the transfer of data from the EBU to the Serial Flash device (write access), the data to send must be stored in this register. The data bytes have to be right-aligned in this register, that is, the last byte to send must be placed in bits DATA[7:0], the second-to-last byte in bits DATA[15:8], etc.. Similarly, for a read access with data being transferred from the Serial Flash to the EBU, this register collects the read data received from the device. The read data is right-aligned, that is, the last byte received gets placed in bits DATA[7:0], the second-to-last byte in bits DATA[15:8], etc... The number of data bytes to be transferred between EBU and the Serial Flash is defined in EBU_SFCMD.DLEN. Note:Register EBU_SFDATA is only used for accesses in Indirect Access Mode and is ignored/remains unaltered for all accesses in Direct Access Mode. */
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+#define SFDATA_DATA_MASK 0xFFFFFFFF
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+/** field offset */
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+#define SFDATA_DATA_OFFSET 0
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+
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+/* Fields of "Serial Flash I/O Control Register" */
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+/** Start of Write Delay
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+ By default, the EBU starts driving to AD[3:0] two EBU clock cycles before asserting the CS for an external Serial Flash access. For write accesses, this delay can be increased via field SOWD. */
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+#define SFIO_SOWD_MASK 0x0000F000
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+/** field offset */
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+#define SFIO_SOWD_OFFSET 12
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+/** End of Write Delay
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+ This field defines the time (in number of EBU clock cycles) for which the EBU keeps driving the External Bus AD[3:0] after deassertion of the device's CS. */
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+#define SFIO_EOWD_MASK 0x00000F00
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+/** field offset */
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+#define SFIO_EOWD_OFFSET 8
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+/** Data Output
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+ The EBU always controls the AD[3:0] pins while a CS for a Serial Flash device is asserted. Field UNUSED_WD defines the values being driven to these pins while the Serial Flash controller is not writing data to or is reading data from the device via the respective line. See Section 3.18.6 for details. */
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+#define SFIO_UNUSED_WD_MASK 0x0000000F
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+/** field offset */
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+#define SFIO_UNUSED_WD_OFFSET 0
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+
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+/*! @} */ /* EBU_REGISTER */
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+
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+#endif /* _ebu_reg_h */
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