mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-24 20:27:42 +02:00
f7d2258cfb
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13224 3c298f89-4303-0410-b956-a3cf2f4a3e73
744 lines
21 KiB
Diff
744 lines
21 KiB
Diff
diff -urN a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c
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--- a/arch/mips/rb532/devices.c 2008-11-07 18:55:34.000000000 +0100
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+++ b/arch/mips/rb532/devices.c 2008-11-15 17:43:28.000000000 +0100
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@@ -34,21 +34,11 @@
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#include <asm/mach-rc32434/rb.h>
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#include <asm/mach-rc32434/integ.h>
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#include <asm/mach-rc32434/gpio.h>
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-
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-#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0)
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-#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1)
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-#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9)
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-#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10)
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+#include <asm/mach-rc32434/irq.h>
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#define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
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#define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
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-/* NAND definitions */
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-#define GPIO_RDY (1 << 0x08)
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-#define GPIO_WPX (1 << 0x09)
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-#define GPIO_ALE (1 << 0x0a)
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-#define GPIO_CLE (1 << 0x0b)
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-
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static struct resource korina_dev0_res[] = {
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{
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.name = "korina_regs",
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@@ -94,15 +84,13 @@
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};
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static struct platform_device korina_dev0 = {
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- .id = 0,
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+ .id = -1,
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.name = "korina",
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.dev.platform_data = &korina_dev0_data,
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.resource = korina_dev0_res,
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.num_resources = ARRAY_SIZE(korina_dev0_res),
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};
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-#define CF_GPIO_NUM 13
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-
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static struct resource cf_slot0_res[] = {
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{
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.name = "cf_membase",
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@@ -116,11 +104,11 @@
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};
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static struct cf_device cf_slot0_data = {
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- .gpio_pin = 13
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+ .gpio_pin = CF_GPIO_NUM
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};
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static struct platform_device cf_slot0 = {
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- .id = 0,
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+ .id = -1,
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.name = "pata-rb532-cf",
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.dev.platform_data = &cf_slot0_data,
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.resource = cf_slot0_res,
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@@ -130,7 +118,7 @@
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/* Resources and device for NAND */
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static int rb532_dev_ready(struct mtd_info *mtd)
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{
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- return readl(IDT434_REG_BASE + GPIOD) & GPIO_RDY;
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+ return gpio_get_value(GPIO_RDY);
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}
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static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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@@ -185,7 +173,7 @@
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static struct platform_device rb532_led = {
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.name = "rb532-led",
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- .id = 0,
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+ .id = -1,
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};
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static struct gpio_keys_button rb532_gpio_btn[] = {
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@@ -292,7 +280,7 @@
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{
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/* Look for the CF card reader */
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if (!readl(IDT434_REG_BASE + DEV1MASK))
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- rb532_devs[1] = NULL;
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+ rb532_devs[2] = NULL; /* disable cf_slot0 at index 2 */
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else {
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cf_slot0_res[0].start =
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readl(IDT434_REG_BASE + DEV1BASE);
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diff -urN a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c
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--- a/arch/mips/rb532/gpio.c 2008-11-07 18:55:34.000000000 +0100
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+++ b/arch/mips/rb532/gpio.c 2008-11-15 17:43:28.000000000 +0100
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@@ -27,28 +27,27 @@
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*/
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#include <linux/kernel.h>
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-#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/types.h>
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-#include <linux/pci.h>
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#include <linux/spinlock.h>
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-#include <linux/io.h>
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#include <linux/platform_device.h>
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-
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-#include <asm/addrspace.h>
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+#include <linux/gpio.h>
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#include <asm/mach-rc32434/rb.h>
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+#include <asm/mach-rc32434/gpio.h>
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-struct rb532_gpio_reg __iomem *rb532_gpio_reg0;
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-EXPORT_SYMBOL(rb532_gpio_reg0);
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+struct rb532_gpio_chip {
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+ struct gpio_chip chip;
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+ void __iomem *regbase;
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+};
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struct mpmc_device dev3;
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static struct resource rb532_gpio_reg0_res[] = {
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{
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.name = "gpio_reg0",
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- .start = (u32)(IDT434_REG_BASE + GPIOBASE),
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- .end = (u32)(IDT434_REG_BASE + GPIOBASE + sizeof(struct rb532_gpio_reg)),
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+ .start = REGBASE + GPIOBASE,
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+ .end = REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1,
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.flags = IORESOURCE_MEM,
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}
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};
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@@ -56,8 +55,8 @@
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static struct resource rb532_dev3_ctl_res[] = {
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{
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.name = "dev3_ctl",
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- .start = (u32)(IDT434_REG_BASE + DEV3BASE),
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- .end = (u32)(IDT434_REG_BASE + DEV3BASE + sizeof(struct dev_reg)),
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+ .start = REGBASE + DEV3BASE,
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+ .end = REGBASE + DEV3BASE + sizeof(struct dev_reg) - 1,
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.flags = IORESOURCE_MEM,
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}
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};
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@@ -70,7 +69,7 @@
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spin_lock_irqsave(&dev3.lock, flags);
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- data = *(volatile unsigned *) (IDT434_REG_BASE + reg_offs);
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+ data = readl(IDT434_REG_BASE + reg_offs);
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for (i = 0; i != len; ++i) {
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if (val & (1 << i))
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data |= (1 << (i + bit));
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@@ -108,114 +107,166 @@
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}
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EXPORT_SYMBOL(get_latch_u5);
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-int rb532_gpio_get_value(unsigned gpio)
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+/* rb532_set_bit - sanely set a bit
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+ *
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+ * bitval: new value for the bit
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+ * offset: bit index in the 4 byte address range
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+ * ioaddr: 4 byte aligned address being altered
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+ */
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+static inline void rb532_set_bit(unsigned bitval,
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+ unsigned offset, void __iomem *ioaddr)
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{
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- return readl(&rb532_gpio_reg0->gpiod) & (1 << gpio);
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-}
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-EXPORT_SYMBOL(rb532_gpio_get_value);
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+ unsigned long flags;
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+ u32 val;
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-void rb532_gpio_set_value(unsigned gpio, int value)
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-{
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- unsigned tmp;
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+ bitval = !!bitval; /* map parameter to {0,1} */
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+
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+ local_irq_save(flags);
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- tmp = readl(&rb532_gpio_reg0->gpiod) & ~(1 << gpio);
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- if (value)
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- tmp |= 1 << gpio;
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+ val = readl(ioaddr);
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+ val &= ~( ~bitval << offset ); /* unset bit if bitval == 0 */
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+ val |= ( bitval << offset ); /* set bit if bitval == 1 */
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+ writel(val, ioaddr);
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- writel(tmp, (void *)&rb532_gpio_reg0->gpiod);
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+ local_irq_restore(flags);
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}
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-EXPORT_SYMBOL(rb532_gpio_set_value);
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-int rb532_gpio_direction_input(unsigned gpio)
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+/* rb532_get_bit - read a bit
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+ *
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+ * returns the boolean state of the bit, which may be > 1
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+ */
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+static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr)
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{
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- writel(readl(&rb532_gpio_reg0->gpiocfg) & ~(1 << gpio),
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- (void *)&rb532_gpio_reg0->gpiocfg);
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-
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- return 0;
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+ return (readl(ioaddr) & (1 << offset));
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}
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-EXPORT_SYMBOL(rb532_gpio_direction_input);
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-int rb532_gpio_direction_output(unsigned gpio, int value)
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+/*
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+ * Return GPIO level */
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+static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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- gpio_set_value(gpio, value);
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- writel(readl(&rb532_gpio_reg0->gpiocfg) | (1 << gpio),
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- (void *)&rb532_gpio_reg0->gpiocfg);
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+ struct rb532_gpio_chip *gpch;
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- return 0;
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+ gpch = container_of(chip, struct rb532_gpio_chip, chip);
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+ return rb532_get_bit(offset, gpch->regbase + GPIOD);
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}
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-EXPORT_SYMBOL(rb532_gpio_direction_output);
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-void rb532_gpio_set_int_level(unsigned gpio, int value)
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+/*
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+ * Set output GPIO level
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+ */
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+static void rb532_gpio_set(struct gpio_chip *chip,
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+ unsigned offset, int value)
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{
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- unsigned tmp;
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+ struct rb532_gpio_chip *gpch;
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- tmp = readl(&rb532_gpio_reg0->gpioilevel) & ~(1 << gpio);
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- if (value)
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- tmp |= 1 << gpio;
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- writel(tmp, (void *)&rb532_gpio_reg0->gpioilevel);
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+ gpch = container_of(chip, struct rb532_gpio_chip, chip);
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+ rb532_set_bit(value, offset, gpch->regbase + GPIOD);
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}
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-EXPORT_SYMBOL(rb532_gpio_set_int_level);
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-int rb532_gpio_get_int_level(unsigned gpio)
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+/*
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+ * Set GPIO direction to input
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+ */
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+static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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- return readl(&rb532_gpio_reg0->gpioilevel) & (1 << gpio);
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+ struct rb532_gpio_chip *gpch;
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+
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+ gpch = container_of(chip, struct rb532_gpio_chip, chip);
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+
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+ if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
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+ return 1; /* alternate function, GPIOCFG is ignored */
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+
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+ rb532_set_bit(0, offset, gpch->regbase + GPIOCFG);
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+ return 0;
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}
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-EXPORT_SYMBOL(rb532_gpio_get_int_level);
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-void rb532_gpio_set_int_status(unsigned gpio, int value)
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+/*
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+ * Set GPIO direction to output
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+ */
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+static int rb532_gpio_direction_output(struct gpio_chip *chip,
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+ unsigned offset, int value)
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{
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- unsigned tmp;
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+ struct rb532_gpio_chip *gpch;
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+
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+ gpch = container_of(chip, struct rb532_gpio_chip, chip);
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- tmp = readl(&rb532_gpio_reg0->gpioistat);
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- if (value)
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- tmp |= 1 << gpio;
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- writel(tmp, (void *)&rb532_gpio_reg0->gpioistat);
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+ if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC))
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+ return 1; /* alternate function, GPIOCFG is ignored */
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+
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+ /* set the initial output value */
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+ rb532_set_bit(value, offset, gpch->regbase + GPIOD);
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+
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+ rb532_set_bit(1, offset, gpch->regbase + GPIOCFG);
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+ return 0;
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}
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-EXPORT_SYMBOL(rb532_gpio_set_int_status);
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-int rb532_gpio_get_int_status(unsigned gpio)
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+static struct rb532_gpio_chip rb532_gpio_chip[] = {
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+ [0] = {
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+ .chip = {
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+ .label = "gpio0",
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+ .direction_input = rb532_gpio_direction_input,
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+ .direction_output = rb532_gpio_direction_output,
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+ .get = rb532_gpio_get,
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+ .set = rb532_gpio_set,
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+ .base = 0,
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+ .ngpio = 32,
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+ },
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+ },
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+};
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+
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+/*
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+ * Set GPIO interrupt level
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+ */
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+void rb532_gpio_set_ilevel(int bit, unsigned gpio)
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{
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- return readl(&rb532_gpio_reg0->gpioistat) & (1 << gpio);
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+ rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL);
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}
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-EXPORT_SYMBOL(rb532_gpio_get_int_status);
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+EXPORT_SYMBOL(rb532_gpio_set_ilevel);
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-void rb532_gpio_set_func(unsigned gpio, int value)
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+/*
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+ * Set GPIO interrupt status
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+ */
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+void rb532_gpio_set_istat(int bit, unsigned gpio)
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{
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- unsigned tmp;
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-
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- tmp = readl(&rb532_gpio_reg0->gpiofunc);
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- if (value)
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- tmp |= 1 << gpio;
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- writel(tmp, (void *)&rb532_gpio_reg0->gpiofunc);
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+ rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT);
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}
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-EXPORT_SYMBOL(rb532_gpio_set_func);
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+EXPORT_SYMBOL(rb532_gpio_set_istat);
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-int rb532_gpio_get_func(unsigned gpio)
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+/*
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+ * Configure GPIO alternate function
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+ */
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+static void rb532_gpio_set_func(int bit, unsigned gpio)
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{
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- return readl(&rb532_gpio_reg0->gpiofunc) & (1 << gpio);
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+ rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC);
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}
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-EXPORT_SYMBOL(rb532_gpio_get_func);
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int __init rb532_gpio_init(void)
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{
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- rb532_gpio_reg0 = ioremap_nocache(rb532_gpio_reg0_res[0].start,
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- rb532_gpio_reg0_res[0].end -
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- rb532_gpio_reg0_res[0].start);
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+ struct resource *r;
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+
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+ r = rb532_gpio_reg0_res;
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+ rb532_gpio_chip->regbase = ioremap_nocache(r->start, r->end - r->start);
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- if (!rb532_gpio_reg0) {
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+ if (!rb532_gpio_chip->regbase) {
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printk(KERN_ERR "rb532: cannot remap GPIO register 0\n");
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return -ENXIO;
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}
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- dev3.base = ioremap_nocache(rb532_dev3_ctl_res[0].start,
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- rb532_dev3_ctl_res[0].end -
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- rb532_dev3_ctl_res[0].start);
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+ /* Register our GPIO chip */
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+ gpiochip_add(&rb532_gpio_chip->chip);
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+
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+ r = rb532_dev3_ctl_res;
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+ dev3.base = ioremap_nocache(r->start, r->end - r->start);
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if (!dev3.base) {
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printk(KERN_ERR "rb532: cannot remap device controller 3\n");
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return -ENXIO;
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}
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+ /* configure CF_GPIO_NUM as CFRDY IRQ source */
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+ rb532_gpio_set_func(0, CF_GPIO_NUM);
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+ rb532_gpio_direction_input(&rb532_gpio_chip->chip, CF_GPIO_NUM);
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+ rb532_gpio_set_ilevel(1, CF_GPIO_NUM);
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+ rb532_gpio_set_istat(0, CF_GPIO_NUM);
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+
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return 0;
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}
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arch_initcall(rb532_gpio_init);
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diff -urN a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c
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--- a/arch/mips/rb532/irq.c 2008-11-07 18:55:34.000000000 +0100
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+++ b/arch/mips/rb532/irq.c 2008-11-15 17:43:28.000000000 +0100
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@@ -45,7 +45,7 @@
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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-#include <asm/mach-rc32434/rc32434.h>
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+#include <asm/mach-rc32434/irq.h>
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struct intr_group {
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u32 mask; /* mask of valid bits in pending/mask registers */
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diff -urN a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c
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--- a/arch/mips/rb532/prom.c 2008-11-07 18:55:34.000000000 +0100
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+++ b/arch/mips/rb532/prom.c 2008-11-15 17:43:28.000000000 +0100
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@@ -37,12 +37,8 @@
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#include <asm/mach-rc32434/ddr.h>
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#include <asm/mach-rc32434/prom.h>
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-extern void __init setup_serial_port(void);
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-
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unsigned int idt_cpu_freq = 132000000;
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EXPORT_SYMBOL(idt_cpu_freq);
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-unsigned int gpio_bootup_state;
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-EXPORT_SYMBOL(gpio_bootup_state);
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static struct resource ddr_reg[] = {
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{
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@@ -108,9 +104,6 @@
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mips_machtype = MACH_MIKROTIK_RB532;
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}
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- if (match_tag(prom_argv[i], GPIO_TAG))
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- gpio_bootup_state = tag2ul(prom_argv[i], GPIO_TAG);
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-
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strcpy(cp, prom_argv[i]);
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cp += strlen(prom_argv[i]);
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}
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@@ -122,11 +115,6 @@
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strcpy(cp, arcs_cmdline);
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cp += strlen(arcs_cmdline);
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}
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- if (gpio_bootup_state & 0x02)
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- strcpy(cp, GPIO_INIT_NOBUTTON);
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- else
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- strcpy(cp, GPIO_INIT_BUTTON);
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-
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cmd_line[CL_SIZE-1] = '\0';
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strcpy(arcs_cmdline, cmd_line);
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diff -urN a/arch/mips/rb532/serial.c b/arch/mips/rb532/serial.c
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--- a/arch/mips/rb532/serial.c 2008-11-07 18:55:34.000000000 +0100
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+++ b/arch/mips/rb532/serial.c 2008-11-15 17:43:28.000000000 +0100
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@@ -31,16 +31,16 @@
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#include <linux/serial_8250.h>
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#include <asm/serial.h>
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-#include <asm/mach-rc32434/rc32434.h>
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+#include <asm/mach-rc32434/rb.h>
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extern unsigned int idt_cpu_freq;
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static struct uart_port rb532_uart = {
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.type = PORT_16550A,
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.line = 0,
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- .irq = RC32434_UART0_IRQ,
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+ .irq = UART0_IRQ,
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.iotype = UPIO_MEM,
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- .membase = (char *)KSEG1ADDR(RC32434_UART0_BASE),
|
|
+ .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE),
|
|
.regshift = 2
|
|
};
|
|
|
|
diff -urN a/arch/mips/rb532/setup.c b/arch/mips/rb532/setup.c
|
|
--- a/arch/mips/rb532/setup.c 2008-11-07 18:55:34.000000000 +0100
|
|
+++ b/arch/mips/rb532/setup.c 2008-11-15 17:43:28.000000000 +0100
|
|
@@ -9,7 +9,7 @@
|
|
#include <asm/time.h>
|
|
#include <linux/ioport.h>
|
|
|
|
-#include <asm/mach-rc32434/rc32434.h>
|
|
+#include <asm/mach-rc32434/rb.h>
|
|
#include <asm/mach-rc32434/pci.h>
|
|
|
|
struct pci_reg __iomem *pci_reg;
|
|
@@ -27,7 +27,7 @@
|
|
static void rb_machine_restart(char *command)
|
|
{
|
|
/* just jump to the reset vector */
|
|
- writel(0x80000001, (void *)KSEG1ADDR(RC32434_REG_BASE + RC32434_RST));
|
|
+ writel(0x80000001, IDT434_REG_BASE + RST);
|
|
((void (*)(void)) KSEG1ADDR(0x1FC00000u))();
|
|
}
|
|
|
|
diff -urN a/arch/mips/rb532/time.c b/arch/mips/rb532/time.c
|
|
--- a/arch/mips/rb532/time.c 2008-11-07 18:55:34.000000000 +0100
|
|
+++ b/arch/mips/rb532/time.c 2008-11-15 17:43:28.000000000 +0100
|
|
@@ -28,7 +28,6 @@
|
|
#include <linux/timex.h>
|
|
|
|
#include <asm/mipsregs.h>
|
|
-#include <asm/debug.h>
|
|
#include <asm/time.h>
|
|
#include <asm/mach-rc32434/rc32434.h>
|
|
|
|
diff -urN linux-2.6.27.5/arch/mips/Kconfig linux-2.6.27.5.new/arch/mips/Kconfig
|
|
--- linux-2.6.27.5/arch/mips/Kconfig 2008-11-07 18:55:34.000000000 +0100
|
|
+++ linux-2.6.27.5.new/arch/mips/Kconfig 2008-11-15 17:50:42.000000000 +0100
|
|
@@ -568,7 +568,7 @@
|
|
select SYS_SUPPORTS_LITTLE_ENDIAN
|
|
select SWAP_IO_SPACE
|
|
select BOOT_RAW
|
|
- select GENERIC_GPIO
|
|
+ select ARCH_REQUIRE_GPIOLIB
|
|
help
|
|
Support the Mikrotik(tm) RouterBoard 532 series,
|
|
based on the IDT RC32434 SoC.
|
|
diff -urN a/include/asm-mips/mach-rc32434/gpio.h b/include-mips/asm/mach-rc32434/gpio.h
|
|
--- a/include/asm-mips/mach-rc32434/gpio.h 2008-11-07 18:55:34.000000000 +0100
|
|
+++ b/include/asm-mips/mach-rc32434/gpio.h 2008-11-15 17:43:28.000000000 +0100
|
|
@@ -14,6 +14,16 @@
|
|
#define _RC32434_GPIO_H_
|
|
|
|
#include <linux/types.h>
|
|
+#include <asm-generic/gpio.h>
|
|
+
|
|
+#define NR_BUILTIN_GPIO 32
|
|
+
|
|
+#define gpio_get_value __gpio_get_value
|
|
+#define gpio_set_value __gpio_set_value
|
|
+#define gpio_cansleep __gpio_cansleep
|
|
+
|
|
+#define gpio_to_irq(gpio) (8 + 4 * 32 + gpio)
|
|
+#define irq_to_gpio(irq) (irq - (8 + 4 * 32))
|
|
|
|
struct rb532_gpio_reg {
|
|
u32 gpiofunc; /* GPIO Function Register
|
|
@@ -61,66 +71,20 @@
|
|
/* PCI messaging unit */
|
|
#define RC32434_PCI_MSU_GPIO (1 << 13)
|
|
|
|
+/* NAND GPIO signals */
|
|
+#define GPIO_RDY 8
|
|
+#define GPIO_WPX 9
|
|
+#define GPIO_ALE 10
|
|
+#define GPIO_CLE 11
|
|
+
|
|
+/* Compact Flash GPIO pin */
|
|
+#define CF_GPIO_NUM 13
|
|
|
|
extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val);
|
|
extern unsigned get_434_reg(unsigned reg_offs);
|
|
extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
|
|
extern unsigned char get_latch_u5(void);
|
|
-
|
|
-extern int rb532_gpio_get_value(unsigned gpio);
|
|
-extern void rb532_gpio_set_value(unsigned gpio, int value);
|
|
-extern int rb532_gpio_direction_input(unsigned gpio);
|
|
-extern int rb532_gpio_direction_output(unsigned gpio, int value);
|
|
-extern void rb532_gpio_set_int_level(unsigned gpio, int value);
|
|
-extern int rb532_gpio_get_int_level(unsigned gpio);
|
|
-extern void rb532_gpio_set_int_status(unsigned gpio, int value);
|
|
-extern int rb532_gpio_get_int_status(unsigned gpio);
|
|
-
|
|
-
|
|
-/* Wrappers for the arch-neutral GPIO API */
|
|
-
|
|
-static inline int gpio_request(unsigned gpio, const char *label)
|
|
-{
|
|
- /* Not yet implemented */
|
|
- return 0;
|
|
-}
|
|
-
|
|
-static inline void gpio_free(unsigned gpio)
|
|
-{
|
|
- /* Not yet implemented */
|
|
-}
|
|
-
|
|
-static inline int gpio_direction_input(unsigned gpio)
|
|
-{
|
|
- return rb532_gpio_direction_input(gpio);
|
|
-}
|
|
-
|
|
-static inline int gpio_direction_output(unsigned gpio, int value)
|
|
-{
|
|
- return rb532_gpio_direction_output(gpio, value);
|
|
-}
|
|
-
|
|
-static inline int gpio_get_value(unsigned gpio)
|
|
-{
|
|
- return rb532_gpio_get_value(gpio);
|
|
-}
|
|
-
|
|
-static inline void gpio_set_value(unsigned gpio, int value)
|
|
-{
|
|
- rb532_gpio_set_value(gpio, value);
|
|
-}
|
|
-
|
|
-static inline int gpio_to_irq(unsigned gpio)
|
|
-{
|
|
- return gpio;
|
|
-}
|
|
-
|
|
-static inline int irq_to_gpio(unsigned irq)
|
|
-{
|
|
- return irq;
|
|
-}
|
|
-
|
|
-/* For cansleep */
|
|
-#include <asm-generic/gpio.h>
|
|
+extern void rb532_gpio_set_ilevel(int bit, unsigned gpio);
|
|
+extern void rb532_gpio_set_istat(int bit, unsigned gpio);
|
|
|
|
#endif /* _RC32434_GPIO_H_ */
|
|
diff -urN a/include/asm-mips/mach-rc32434/irq.h b/include/asm-mips/mach-rc32434/irq.h
|
|
--- a/include/asm-mips/mach-rc32434/irq.h 2008-11-07 18:55:34.000000000 +0100
|
|
+++ b/include/asm-mips/mach-rc32434/irq.h 2008-11-15 17:43:28.000000000 +0100
|
|
@@ -4,5 +4,30 @@
|
|
#define NR_IRQS 256
|
|
|
|
#include <asm/mach-generic/irq.h>
|
|
+#include <asm/mach-rc32434/rb.h>
|
|
+
|
|
+/* Interrupt Controller */
|
|
+#define IC_GROUP0_PEND (REGBASE + 0x38000)
|
|
+#define IC_GROUP0_MASK (REGBASE + 0x38008)
|
|
+#define IC_GROUP_OFFSET 0x0C
|
|
+
|
|
+#define NUM_INTR_GROUPS 5
|
|
+
|
|
+/* 16550 UARTs */
|
|
+#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
|
|
+ /* GRP3 IRQ numbers start here */
|
|
+#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32)
|
|
+ /* GRP4 IRQ numbers start here */
|
|
+#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32)
|
|
+ /* GRP5 IRQ numbers start here */
|
|
+#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32)
|
|
+#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
|
|
+
|
|
+#define UART0_IRQ (GROUP3_IRQ_BASE + 0)
|
|
+
|
|
+#define ETH0_DMA_RX_IRQ (GROUP1_IRQ_BASE + 0)
|
|
+#define ETH0_DMA_TX_IRQ (GROUP1_IRQ_BASE + 1)
|
|
+#define ETH0_RX_OVR_IRQ (GROUP3_IRQ_BASE + 9)
|
|
+#define ETH0_TX_UND_IRQ (GROUP3_IRQ_BASE + 10)
|
|
|
|
#endif /* __ASM_RC32434_IRQ_H */
|
|
diff -urN a/include/asm-mips/mach-rc32434/prom.h b/include/asm-mips/mach-rc32434/prom.h
|
|
--- a/include/asm-mips/mach-rc32434/prom.h 2008-11-07 18:55:34.000000000 +0100
|
|
+++ b/include/asm-mips/mach-rc32434/prom.h 2008-11-15 17:43:28.000000000 +0100
|
|
@@ -28,14 +28,10 @@
|
|
|
|
#define PROM_ENTRY(x) (0xbfc00000 + ((x) * 8))
|
|
|
|
-#define GPIO_INIT_NOBUTTON ""
|
|
-#define GPIO_INIT_BUTTON " 2"
|
|
-
|
|
#define SR_NMI 0x00180000
|
|
#define SERIAL_SPEED_ENTRY 0x00000001
|
|
|
|
#define FREQ_TAG "HZ="
|
|
-#define GPIO_TAG "gpio="
|
|
#define KMAC_TAG "kmac="
|
|
#define MEM_TAG "mem="
|
|
#define BOARD_TAG "board="
|
|
diff -urN a/include/asm-mips/mach-rc32434/rb.h b/include/asm-mips/mach-rc32434/rb.h
|
|
--- a/include/asm-mips/mach-rc32434/rb.h 2008-11-07 18:55:34.000000000 +0100
|
|
+++ b/include/asm-mips/mach-rc32434/rb.h 2008-11-15 17:43:28.000000000 +0100
|
|
@@ -17,7 +17,10 @@
|
|
|
|
#include <linux/genhd.h>
|
|
|
|
-#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
|
|
+#define REGBASE 0x18000000
|
|
+#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE))
|
|
+#define UART0BASE 0x58000
|
|
+#define RST (1 << 15)
|
|
#define DEV0BASE 0x010000
|
|
#define DEV0MASK 0x010004
|
|
#define DEV0C 0x010008
|
|
@@ -37,12 +40,14 @@
|
|
#define BTCS 0x010040
|
|
#define BTCOMPARE 0x010044
|
|
#define GPIOBASE 0x050000
|
|
-#define GPIOCFG 0x050004
|
|
-#define GPIOD 0x050008
|
|
-#define GPIOILEVEL 0x05000C
|
|
-#define GPIOISTAT 0x050010
|
|
-#define GPIONMIEN 0x050014
|
|
-#define IMASK6 0x038038
|
|
+/* Offsets relative to GPIOBASE */
|
|
+#define GPIOFUNC 0x00
|
|
+#define GPIOCFG 0x04
|
|
+#define GPIOD 0x08
|
|
+#define GPIOILEVEL 0x0C
|
|
+#define GPIOISTAT 0x10
|
|
+#define GPIONMIEN 0x14
|
|
+#define IMASK6 0x38
|
|
#define LO_WPX (1 << 0)
|
|
#define LO_ALE (1 << 1)
|
|
#define LO_CLE (1 << 2)
|
|
diff -urN a/include/asm-mips/mach-rc32434/rc32434.h b/include/asm-mips/mach-rc32434/rc32434.h
|
|
--- a/include/asm-mips/mach-rc32434/rc32434.h 2008-11-07 18:55:34.000000000 +0100
|
|
+++ b/include/asm-mips/mach-rc32434/rc32434.h 2008-11-15 17:43:28.000000000 +0100
|
|
@@ -8,37 +8,7 @@
|
|
#include <linux/delay.h>
|
|
#include <linux/io.h>
|
|
|
|
-#define RC32434_REG_BASE 0x18000000
|
|
-#define RC32434_RST (1 << 15)
|
|
-
|
|
#define IDT_CLOCK_MULT 2
|
|
-#define MIPS_CPU_TIMER_IRQ 7
|
|
-
|
|
-/* Interrupt Controller */
|
|
-#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
|
|
-#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
|
|
-#define IC_GROUP_OFFSET 0x0C
|
|
-
|
|
-#define NUM_INTR_GROUPS 5
|
|
-
|
|
-/* 16550 UARTs */
|
|
-#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
|
|
- /* GRP3 IRQ numbers start here */
|
|
-#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32)
|
|
- /* GRP4 IRQ numbers start here */
|
|
-#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32)
|
|
- /* GRP5 IRQ numbers start here */
|
|
-#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32)
|
|
-#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
|
|
-
|
|
-
|
|
-#ifdef __MIPSEB__
|
|
-#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
|
|
-#else
|
|
-#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
|
|
-#endif
|
|
-
|
|
-#define RC32434_UART0_IRQ (GROUP3_IRQ_BASE + 0)
|
|
|
|
/* cpu pipeline flush */
|
|
static inline void rc32434_sync(void)
|
|
@@ -46,16 +16,4 @@
|
|
__asm__ volatile ("sync");
|
|
}
|
|
|
|
-static inline void rc32434_sync_udelay(int us)
|
|
-{
|
|
- __asm__ volatile ("sync");
|
|
- udelay(us);
|
|
-}
|
|
-
|
|
-static inline void rc32434_sync_delay(int ms)
|
|
-{
|
|
- __asm__ volatile ("sync");
|
|
- mdelay(ms);
|
|
-}
|
|
-
|
|
#endif /* _ASM_RC32434_RC32434_H_ */
|
|
--- a/arch/mips/pci/fixup-rc32434.c 2008-11-07 18:55:34.000000000 +0100
|
|
+++ b/arch/mips/pci/fixup-rc32434.c 2008-11-15 17:43:28.000000000 +0100
|
|
@@ -30,6 +30,7 @@
|
|
#include <linux/init.h>
|
|
|
|
#include <asm/mach-rc32434/rc32434.h>
|
|
+#include <asm/mach-rc32434/irq.h>
|
|
|
|
static int __devinitdata irq_map[2][12] = {
|
|
{0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1},
|