mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-01 01:46:16 +02:00
125276dafe
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16480 3c298f89-4303-0410-b956-a3cf2f4a3e73
78 lines
2.7 KiB
Diff
78 lines
2.7 KiB
Diff
--- a/drivers/staging/octeon/cvmx-helper-board.c
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+++ b/drivers/staging/octeon/cvmx-helper-board.c
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@@ -90,7 +90,7 @@ int cvmx_helper_board_get_mii_address(in
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case CVMX_BOARD_TYPE_KODAMA:
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case CVMX_BOARD_TYPE_EBH3100:
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case CVMX_BOARD_TYPE_HIKARI:
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- case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
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+ //case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
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case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
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case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
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/*
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@@ -103,6 +103,12 @@ int cvmx_helper_board_get_mii_address(in
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return 9;
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else
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return -1;
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+ case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
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+ /* We have only one port, using GMII */
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+ if (ipd_port == 0)
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+ return 9;
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+ else
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+ return -1;
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case CVMX_BOARD_TYPE_NAC38:
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/* Board has 8 RGMII ports PHYs are 0-7 */
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if ((ipd_port >= 0) && (ipd_port < 4))
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@@ -205,7 +211,7 @@ cvmx_helper_link_info_t __cvmx_helper_bo
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result.s.speed = 1000;
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return result;
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case CVMX_BOARD_TYPE_EBH3100:
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- case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
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+ //case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
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case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
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case CVMX_BOARD_TYPE_CN3020_EVB_HS5:
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/* Port 1 on these boards is always Gigabit */
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@@ -217,6 +223,9 @@ cvmx_helper_link_info_t __cvmx_helper_bo
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}
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/* Fall through to the generic code below */
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break;
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+ case CVMX_BOARD_TYPE_CN3010_EVB_HS5: /* hack for the WNDAP330 */
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+ is_broadcom_phy = 1;
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+ break;
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case CVMX_BOARD_TYPE_CUST_NB5:
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/* Port 1 on these boards is always Gigabit */
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if (ipd_port == 1) {
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--- a/drivers/staging/octeon/cvmx-helper-rgmii.c
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+++ b/drivers/staging/octeon/cvmx-helper-rgmii.c
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@@ -66,13 +66,15 @@ int __cvmx_helper_rgmii_probe(int interf
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cvmx_dprintf("ERROR: RGMII initialize called in "
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"SPI interface\n");
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} else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
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- || OCTEON_IS_MODEL(OCTEON_CN30XX)
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+ //|| OCTEON_IS_MODEL(OCTEON_CN30XX)
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|| OCTEON_IS_MODEL(OCTEON_CN50XX)) {
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/*
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* On these chips "type" says we're in
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* GMII/MII mode. This limits us to 2 ports
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*/
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num_ports = 2;
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+ } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
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+ num_ports = 1;
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} else {
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cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n",
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__func__);
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--- a/arch/mips/cavium-octeon/pci.c
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+++ b/arch/mips/cavium-octeon/pci.c
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@@ -95,9 +95,11 @@ const char *octeon_get_pci_interrupts(vo
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case CVMX_BOARD_TYPE_EBH3000:
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return "";
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case CVMX_BOARD_TYPE_EBH3100:
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- case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
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+ //case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
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case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
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return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
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+ case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
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+ return "AAAAAAAAAAAAAABAAAAAAAAAAAAAAABA";
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case CVMX_BOARD_TYPE_BBGW_REF:
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return "AABCD";
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default:
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