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b270e13375
Signed-off-by: Gabor Juhos <juhosg@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34227 3c298f89-4303-0410-b956-a3cf2f4a3e73
35 lines
1.3 KiB
Diff
35 lines
1.3 KiB
Diff
From 132a7253fe87b1f4d71aab5abee3108a793234db Mon Sep 17 00:00:00 2001
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From: Ralf Baechle <ralf@linux-mips.org>
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Date: Tue, 13 Nov 2012 10:41:50 +0100
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Subject: [PATCH] MIPS: Malta: Fix interupt number of CBUS UART.
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The CBUS UART's interrupt number was wrong conflicting with the interrupt
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being tied to the Intel PIIX4. Since the PIIX4's interrupt is registered
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before the CBUS UART which is not being used on most systems this would
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not be noticed.
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Attempts to open the ttyS2 CBUS UART would result in:
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genirq: Flags mismatch irq 18. 00000000 (serial) vs. 00010000 (XT-PIC cascade)
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serial_link_irq_chain: request failed: -16 for irq: 18
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Qemu was written to match the kernel so will need to be fixed also.
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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(cherry picked from commit fe2ccd4dcebd3c5e264af1705bb9b659972418cc)
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---
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arch/mips/mti-malta/malta-platform.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/arch/mips/mti-malta/malta-platform.c
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+++ b/arch/mips/mti-malta/malta-platform.c
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@@ -48,7 +48,7 @@ static struct plat_serial8250_port uart8
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SMC_PORT(0x2F8, 3),
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{
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.mapbase = 0x1f000900, /* The CBUS UART */
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- .irq = MIPS_CPU_IRQ_BASE + 2,
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+ .irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_MB2,
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.uartclk = 3686400, /* Twice the usual clk! */
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.iotype = UPIO_MEM32,
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.flags = CBUS_UART_FLAGS,
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