mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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343c185b7d
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16547 3c298f89-4303-0410-b956-a3cf2f4a3e73
131 lines
5.1 KiB
Diff
131 lines
5.1 KiB
Diff
From b6b6d18a54e22784cb48e1953201484830d030e4 Mon Sep 17 00:00:00 2001
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From: Kurt Mahan <kmahan@freescale.com>
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Date: Thu, 6 Dec 2007 14:17:46 -0700
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Subject: [PATCH] Change USB to SDRAM priority.
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Increase the USB priority to the maximum, above ColdfireCore,
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in the SDRAM crossbar switch. This fixes the issues with the
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USB core not being able to transfer to memory fast enough to
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keep up with HS.
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LTIBName: m5445x-usb-sdram-priority
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Signed-off-by: Kurt Mahan <kmahan@freescale.com>
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---
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arch/m68k/coldfire/config.c | 12 ++++++
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include/asm-m68k/mcf5445x_xbs.h | 81 +++++++++++++++++++++++++++++++++++++++
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2 files changed, 93 insertions(+), 0 deletions(-)
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create mode 100644 include/asm-m68k/mcf5445x_xbs.h
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--- a/arch/m68k/coldfire/config.c
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+++ b/arch/m68k/coldfire/config.c
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@@ -36,6 +36,7 @@
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#include <asm/mcf5445x_sdramc.h>
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#include <asm/mcf5445x_fbcs.h>
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#include <asm/mcf5445x_dtim.h>
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+#include <asm/mcf5445x_xbs.h>
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/* JKM -- testing */
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#include <linux/pfn.h>
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@@ -131,6 +132,17 @@ asmlinkage void __init cf_early_init(voi
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MCF_SDRAMC_SDCS(1) = (256*1024*1024) | 0x1B;
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#endif
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+ /* Setup SDRAM crossbar(XBS) priorities */
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+printk(KERN_INFO "Bumping USB Priority\n");
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+ MCF_XBS_PRS2 = (MCF_XBS_PRS_M0(MCF_XBS_PRI_2) |
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+ MCF_XBS_PRS_M1(MCF_XBS_PRI_3) |
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+ MCF_XBS_PRS_M2(MCF_XBS_PRI_4) |
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+ MCF_XBS_PRS_M3(MCF_XBS_PRI_5) |
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+ MCF_XBS_PRS_M5(MCF_XBS_PRI_6) |
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+ MCF_XBS_PRS_M6(MCF_XBS_PRI_1) |
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+ MCF_XBS_PRS_M7(MCF_XBS_PRI_7));
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+
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+
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m68k_machtype = MACH_CFMMU;
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m68k_fputype = FPU_CFV4E;
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m68k_mmutype = MMU_CFV4E;
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--- /dev/null
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+++ b/include/asm-m68k/mcf5445x_xbs.h
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@@ -0,0 +1,81 @@
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+/*
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+ * Kurt Mahan kmahan@freescale.com
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+ *
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+ * Copyright Freescale Semiconductor, Inc. 2007
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ */
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+
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+#ifndef __MCF5445X_XBS_H__
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+#define __MCF5445X_XBS_H__
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+
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+/*
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+ * Crossbar Switch (XBS)
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+ */
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+
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+/* Register read/write macros */
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+#define MCF_XBS_PRS1 MCF_REG32(0xFC004100) /* Flexbus Priority */
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+#define MCF_XBS_CRS1 MCF_REG32(0xFC004110) /* Flexbus Control */
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+#define MCF_XBS_PRS2 MCF_REG32(0xFC004200) /* SDRam Priority */
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+#define MCF_XBS_CRS2 MCF_REG32(0xFC004210) /* SDRam Control */
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+#define MCF_XBS_PRS3 MCF_REG32(0xFC004300) /* ATA Priority */
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+#define MCF_XBS_CRS3 MCF_REG32(0xFC004310) /* ATA Control */
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+#define MCF_XBS_PRS4 MCF_REG32(0xFC004400) /* SRAM Priority */
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+#define MCF_XBS_CRS4 MCF_REG32(0xFC004410) /* SRAM Control */
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+#define MCF_XBS_PRS5 MCF_REG32(0xFC004500) /* PCI Priority */
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+#define MCF_XBS_CRS5 MCF_REG32(0xFC004510) /* PCI Control */
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+#define MCF_XBS_PRS6 MCF_REG32(0xFC004600) /* Slave6 Priority */
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+#define MCF_XBS_CRS6 MCF_REG32(0xFC004610) /* Slave6 Control */
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+#define MCF_XBS_PRS7 MCF_REG32(0xFC004700) /* Other Priority */
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+#define MCF_XBS_CRS7 MCF_REG32(0xFC004710) /* Other Control */
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+
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+/* Priorities */
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+#define MCF_XBS_PRI_1 0 /* Level 1 (highest) */
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+#define MCF_XBS_PRI_2 1 /* Level 2 */
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+#define MCF_XBS_PRI_3 2 /* Level 3 */
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+#define MCF_XBS_PRI_4 3 /* Level 4 */
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+#define MCF_XBS_PRI_5 4 /* Level 5 */
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+#define MCF_XBS_PRI_6 5 /* Level 6 */
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+#define MCF_XBS_PRI_7 6 /* Level 7 (lowest) */
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+#define MCF_XBS_PRI_MASK 7 /* Mask (Not a valid level) */
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+
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+/* Priority Register (PRSn) Defs */
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+#define MCF_XBS_PRS_MACRO(m,p) ((p)<<((m)<<2))
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+#define MCF_XBS_PRS_M0(p) MCF_XBS_PRS_MACRO(0, p) /* Coldfire Core */
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+#define MCF_XBS_PRS_M1(p) MCF_XBS_PRS_MACRO(1, p) /* eDMA */
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+#define MCF_XBS_PRS_M2(p) MCF_XBS_PRS_MACRO(2, p) /* FEC0 */
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+#define MCF_XBS_PRS_M3(p) MCF_XBS_PRS_MACRO(3, p) /* FEC1 */
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+#define MCF_XBS_PRS_M4(p) MCF_XBS_PRS_MACRO(4, p) /* Master 4 */
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+#define MCF_XBS_PRS_M5(p) MCF_XBS_PRS_MACRO(5, p) /* PCI */
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+#define MCF_XBS_PRS_M6(p) MCF_XBS_PRS_MACRO(6, p) /* USB OTG */
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+#define MCF_XBS_PRS_M7(p) MCF_XBS_PRS_MACRO(7, p) /* Serial Boot */
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+
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+/* Control Register (CRSn) Defs */
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+#define MCF_XBS_CRS_RO 0x80000000 /* Read Only */
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+#define MCF_XBS_CRS_ARB 0x00000100 /* Arbitration Mode */
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+#define MCF_XBS_CRS_PCTL 0x00000030 /* Parking Control */
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+#define MCF_XBS_CRS_PARK 0x00000007 /* Park Location */
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+
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+/* MCF_XBS_CRS_ARB Defs */
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+#define MCF_ABS_CRS_ARB_FIXED 0x00000000 /* Fixed priority */
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+#define MCF_ABS_CRS_ARB_ROUND 0x00000100 /* Round Robin priority */
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+
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+/* MCF_XBS_CRS_PCTL Defs */
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+#define MCF_ABS_CRS_PCTL_PARK 0x00000000 /* Park on the defined PARK */
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+#define MCF_ABS_CRS_PCTL_LAST 0x00000010 /* Park on the last master */
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+#define MCF_ABS_CRS_PCTL_NONE 0x00000020 /* Don't park */
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+
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+/* MCF_XBS_CRS_PARK Defs */
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+#define MCF_ABS_CRS_PARK_M0 0x00000000 /* Park on Coldfire Core */
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+#define MCF_ABS_CRS_PARK_M1 0x00000001 /* Park on eDMA */
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+#define MCF_ABS_CRS_PARK_M2 0x00000002 /* Park on FEC0 */
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+#define MCF_ABS_CRS_PARK_M3 0x00000003 /* Park on FEC1 */
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+#define MCF_ABS_CRS_PARK_M4 0x00000004 /* Park on Reserved */
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+#define MCF_ABS_CRS_PARK_M5 0x00000005 /* Park on PCI */
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+#define MCF_ABS_CRS_PARK_M6 0x00000006 /* Park on USB OTG */
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+#define MCF_ABS_CRS_PARK_M7 0x00000007 /* Park on Serial Boot */
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+
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+#endif /* __MCF5445X_XBS_H__ */
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