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fc35f54386
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11352 3c298f89-4303-0410-b956-a3cf2f4a3e73
38 lines
1.2 KiB
Diff
38 lines
1.2 KiB
Diff
From: Ke Wei <kewei@marvell.com>
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Some Feroceon-based SoCs have an MBUS bridge interrupt controller
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that requires writing a one instead of a zero to clear edge
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interrupt sources such as timer expiry.
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This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform
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code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or
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BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform.
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Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
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---
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arch/arm/plat-orion/time.c | 2 +-
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include/asm-arm/arch-orion5x/orion5x.h | 1 +
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2 files changed, 2 insertions(+), 1 deletions(-)
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--- a/arch/arm/plat-orion/time.c
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+++ b/arch/arm/plat-orion/time.c
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@@ -74,7 +74,7 @@
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/*
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* Clear and enable clockevent timer interrupt.
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*/
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- writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE);
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+ writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
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u = readl(BRIDGE_MASK);
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u |= BRIDGE_INT_TIMER1;
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--- a/include/asm-arm/arch-orion5x/orion5x.h
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+++ b/include/asm-arm/arch-orion5x/orion5x.h
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@@ -152,6 +152,7 @@
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#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114)
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#define BRIDGE_INT_TIMER0 0x0002
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#define BRIDGE_INT_TIMER1 0x0004
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+#define BRIDGE_INT_TIMER1_CLR ~0x0004
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#define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200)
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#define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204)
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