mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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2cea1e6b9a
openwrt. this gives us the ability to better support different hardware models, without changing any external tar-balls. only et.o and wl.o is missing and is fetched from my webserver. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@379 3c298f89-4303-0410-b956-a3cf2f4a3e73
187 lines
6.7 KiB
C
187 lines
6.7 KiB
C
/*
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* Generic Broadcom Home Networking Division (HND) DMA engine definitions.
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* This supports the following chips: BCM42xx, 44xx, 47xx .
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*
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* Copyright 2004, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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* $Id$
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*/
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#ifndef _hnddma_h_
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#define _hnddma_h_
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/*
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* Each DMA processor consists of a transmit channel and a receive channel.
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*/
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typedef volatile struct {
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/* transmit channel */
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uint32 xmtcontrol; /* enable, et al */
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uint32 xmtaddr; /* descriptor ring base address (4K aligned) */
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uint32 xmtptr; /* last descriptor posted to chip */
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uint32 xmtstatus; /* current active descriptor, et al */
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/* receive channel */
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uint32 rcvcontrol; /* enable, et al */
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uint32 rcvaddr; /* descriptor ring base address (4K aligned) */
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uint32 rcvptr; /* last descriptor posted to chip */
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uint32 rcvstatus; /* current active descriptor, et al */
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} dmaregs_t;
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typedef volatile struct {
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/* diag access */
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uint32 fifoaddr; /* diag address */
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uint32 fifodatalow; /* low 32bits of data */
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uint32 fifodatahigh; /* high 32bits of data */
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uint32 pad; /* reserved */
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} dmafifo_t;
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/* transmit channel control */
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#define XC_XE ((uint32)1 << 0) /* transmit enable */
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#define XC_SE ((uint32)1 << 1) /* transmit suspend request */
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#define XC_LE ((uint32)1 << 2) /* loopback enable */
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#define XC_FL ((uint32)1 << 4) /* flush request */
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/* transmit descriptor table pointer */
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#define XP_LD_MASK 0xfff /* last valid descriptor */
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/* transmit channel status */
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#define XS_CD_MASK 0x0fff /* current descriptor pointer */
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#define XS_XS_MASK 0xf000 /* transmit state */
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#define XS_XS_SHIFT 12
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#define XS_XS_DISABLED 0x0000 /* disabled */
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#define XS_XS_ACTIVE 0x1000 /* active */
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#define XS_XS_IDLE 0x2000 /* idle wait */
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#define XS_XS_STOPPED 0x3000 /* stopped */
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#define XS_XS_SUSP 0x4000 /* suspend pending */
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#define XS_XE_MASK 0xf0000 /* transmit errors */
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#define XS_XE_SHIFT 16
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#define XS_XE_NOERR 0x00000 /* no error */
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#define XS_XE_DPE 0x10000 /* descriptor protocol error */
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#define XS_XE_DFU 0x20000 /* data fifo underrun */
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#define XS_XE_BEBR 0x30000 /* bus error on buffer read */
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#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
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#define XS_AD_MASK 0xfff00000 /* active descriptor */
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#define XS_AD_SHIFT 20
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/* receive channel control */
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#define RC_RE ((uint32)1 << 0) /* receive enable */
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#define RC_RO_MASK 0xfe /* receive frame offset */
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#define RC_RO_SHIFT 1
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#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
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/* receive descriptor table pointer */
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#define RP_LD_MASK 0xfff /* last valid descriptor */
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/* receive channel status */
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#define RS_CD_MASK 0x0fff /* current descriptor pointer */
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#define RS_RS_MASK 0xf000 /* receive state */
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#define RS_RS_SHIFT 12
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#define RS_RS_DISABLED 0x0000 /* disabled */
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#define RS_RS_ACTIVE 0x1000 /* active */
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#define RS_RS_IDLE 0x2000 /* idle wait */
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#define RS_RS_STOPPED 0x3000 /* reserved */
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#define RS_RE_MASK 0xf0000 /* receive errors */
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#define RS_RE_SHIFT 16
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#define RS_RE_NOERR 0x00000 /* no error */
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#define RS_RE_DPE 0x10000 /* descriptor protocol error */
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#define RS_RE_DFO 0x20000 /* data fifo overflow */
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#define RS_RE_BEBW 0x30000 /* bus error on buffer write */
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#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
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#define RS_AD_MASK 0xfff00000 /* active descriptor */
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#define RS_AD_SHIFT 20
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/* fifoaddr */
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#define FA_OFF_MASK 0xffff /* offset */
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#define FA_SEL_MASK 0xf0000 /* select */
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#define FA_SEL_SHIFT 16
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#define FA_SEL_XDD 0x00000 /* transmit dma data */
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#define FA_SEL_XDP 0x10000 /* transmit dma pointers */
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#define FA_SEL_RDD 0x40000 /* receive dma data */
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#define FA_SEL_RDP 0x50000 /* receive dma pointers */
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#define FA_SEL_XFD 0x80000 /* transmit fifo data */
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#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
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#define FA_SEL_RFD 0xc0000 /* receive fifo data */
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#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
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/*
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* DMA Descriptor
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* Descriptors are only read by the hardware, never written back.
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*/
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typedef volatile struct {
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uint32 ctrl; /* misc control bits & bufcount */
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uint32 addr; /* data buffer address */
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} dmadd_t;
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/*
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* Each descriptor ring must be 4096byte aligned
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* and fit within a single 4096byte page.
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*/
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#define DMAMAXRINGSZ 4096
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#define DMARINGALIGN 4096
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/* control flags */
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#define CTRL_BC_MASK 0x1fff /* buffer byte count */
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#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
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#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
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#define CTRL_EOF ((uint32)1 << 30) /* end of frame */
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#define CTRL_SOF ((uint32)1 << 31) /* start of frame */
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/* control flags in the range [27:20] are core-specific and not defined here */
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#define CTRL_CORE_MASK 0x0ff00000
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/* export structure */
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typedef volatile struct {
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/* rx error counters */
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uint rxgiants; /* rx giant frames */
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uint rxnobuf; /* rx out of dma descriptors */
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/* tx error counters */
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uint txnobuf; /* tx out of dma descriptors */
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} hnddma_t;
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#ifndef di_t
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#define di_t void
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#endif
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/* externs */
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extern void *dma_attach(void *drv, void *dev, char *name, dmaregs_t *dmaregs,
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uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset,
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uint ddoffset, uint dataoffset, uint *msg_level);
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extern void dma_detach(di_t *di);
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extern void dma_txreset(di_t *di);
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extern void dma_rxreset(di_t *di);
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extern void dma_txinit(di_t *di);
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extern bool dma_txenabled(di_t *di);
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extern void dma_rxinit(di_t *di);
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extern void dma_rxenable(di_t *di);
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extern bool dma_rxenabled(di_t *di);
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extern void dma_txsuspend(di_t *di);
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extern void dma_txresume(di_t *di);
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extern bool dma_txsuspended(di_t *di);
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extern bool dma_txstopped(di_t *di);
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extern bool dma_rxstopped(di_t *di);
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extern int dma_txfast(di_t *di, void *p, uint32 coreflags);
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extern int dma_tx(di_t *di, void *p, uint32 coreflags);
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extern void dma_fifoloopbackenable(di_t *di);
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extern void *dma_rx(di_t *di);
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extern void dma_rxfill(di_t *di);
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extern void dma_txreclaim(di_t *di, bool forceall);
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extern void dma_rxreclaim(di_t *di);
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extern char *dma_dump(di_t *di, char *buf);
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extern char *dma_dumptx(di_t *di, char *buf);
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extern char *dma_dumprx(di_t *di, char *buf);
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extern uint dma_getvar(di_t *di, char *name);
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extern void *dma_getnexttxp(di_t *di, bool forceall);
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extern void *dma_peeknexttxp(di_t *di);
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extern void *dma_getnextrxp(di_t *di, bool forceall);
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extern void dma_txblock(di_t *di);
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extern void dma_txunblock(di_t *di);
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extern uint dma_txactive(di_t *di);
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extern void dma_txrotate(di_t *di);
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#endif /* _hnddma_h_ */
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