mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-27 02:24:35 +02:00
e0b80e41eb
Tested on the following boards: ALFA AP96 TL-MR3220 v1 TL-WR1043ND v1 TL-WR2543ND v1 TL-WR703N v1 TL-WR741ND v1 TL-WR741ND v4 WNDR3700 v1 WZR-HP-G300NH git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29868 3c298f89-4303-0410-b956-a3cf2f4a3e73
149 lines
4.5 KiB
Diff
149 lines
4.5 KiB
Diff
From 29c8b2eef2011bf9392479487a51f6927892bfd6 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Mon, 20 Jun 2011 21:26:04 +0200
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Subject: [PATCH 07/27] MIPS: ath79: add AR933X specific clock init
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Cc: linux-mips@linux-mips.org
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Cc: Kathy Giori <kgiori@qca.qualcomm.com>
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Cc: "Luis R. Rodriguez" <rodrigue@qca.qualcomm.com>
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Patchwork: https://patchwork.linux-mips.org/patch/2522/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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arch/mips/ath79/clock.c | 55 ++++++++++++++++++++++++
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 22 +++++++++
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arch/mips/include/asm/mach-ath79/ath79.h | 6 +++
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3 files changed, 83 insertions(+), 0 deletions(-)
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -110,6 +110,59 @@ static void __init ar913x_clocks_init(vo
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ath79_uart_clk.rate = ath79_ahb_clk.rate;
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}
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+static void __init ar933x_clocks_init(void)
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+{
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+ u32 clock_ctrl;
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+ u32 cpu_config;
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+ u32 freq;
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+ u32 t;
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+
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+ t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
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+ if (t & AR933X_BOOTSTRAP_REF_CLK_40)
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+ ath79_ref_clk.rate = (40 * 1000 * 1000);
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+ else
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+ ath79_ref_clk.rate = (25 * 1000 * 1000);
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+
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+ clock_ctrl = ath79_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
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+ if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
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+ ath79_cpu_clk.rate = ath79_ref_clk.rate;
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+ ath79_ahb_clk.rate = ath79_ref_clk.rate;
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+ ath79_ddr_clk.rate = ath79_ref_clk.rate;
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+ } else {
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+ cpu_config = ath79_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
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+
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+ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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+ AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
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+ freq = ath79_ref_clk.rate / t;
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+
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+ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
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+ AR933X_PLL_CPU_CONFIG_NINT_MASK;
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+ freq *= t;
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+
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+ t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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+ AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
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+ if (t == 0)
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+ t = 1;
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+
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+ freq >>= t;
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+
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+ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
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+ AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
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+ ath79_cpu_clk.rate = freq / t;
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+
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+ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
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+ AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
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+ ath79_ddr_clk.rate = freq / t;
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+
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+ t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
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+ AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
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+ ath79_ahb_clk.rate = freq / t;
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+ }
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+
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+ ath79_wdt_clk.rate = ath79_ref_clk.rate;
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+ ath79_uart_clk.rate = ath79_ref_clk.rate;
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+}
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+
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void __init ath79_clocks_init(void)
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{
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if (soc_is_ar71xx())
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@@ -118,6 +171,8 @@ void __init ath79_clocks_init(void)
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ar724x_clocks_init();
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else if (soc_is_ar913x())
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ar913x_clocks_init();
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+ else if (soc_is_ar933x())
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+ ar933x_clocks_init();
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else
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BUG();
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -123,6 +123,24 @@
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#define AR913X_AHB_DIV_SHIFT 19
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#define AR913X_AHB_DIV_MASK 0x1
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+#define AR933X_PLL_CPU_CONFIG_REG 0x00
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+#define AR933X_PLL_CLOCK_CTRL_REG 0x08
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+
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+#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
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+#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
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+#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
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+#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
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+#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
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+#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
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+
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+#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
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+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
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+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
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+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
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+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
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+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
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+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
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+
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/*
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* USB_CONFIG block
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*/
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@@ -155,6 +173,8 @@
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#define AR724X_RESET_REG_RESET_MODULE 0x1c
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+#define AR933X_RESET_REG_BOOTSTRAP 0xac
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+
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#define MISC_INT_ETHSW BIT(12)
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#define MISC_INT_TIMER4 BIT(10)
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#define MISC_INT_TIMER3 BIT(9)
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@@ -204,6 +224,8 @@
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#define AR913X_RESET_USB_HOST BIT(5)
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#define AR913X_RESET_USB_PHY BIT(4)
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+#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
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+
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#define REV_ID_MAJOR_MASK 0xfff0
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#define REV_ID_MAJOR_AR71XX 0x00a0
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#define REV_ID_MAJOR_AR913X 0x00b0
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--- a/arch/mips/include/asm/mach-ath79/ath79.h
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+++ b/arch/mips/include/asm/mach-ath79/ath79.h
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@@ -68,6 +68,12 @@ static inline int soc_is_ar913x(void)
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ath79_soc == ATH79_SOC_AR9132);
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}
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+static inline int soc_is_ar933x(void)
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+{
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+ return (ath79_soc == ATH79_SOC_AR9330 ||
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+ ath79_soc == ATH79_SOC_AR9331);
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+}
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+
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extern void __iomem *ath79_ddr_base;
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extern void __iomem *ath79_pll_base;
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extern void __iomem *ath79_reset_base;
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