mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-13 14:51:10 +03:00
fc35f54386
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11352 3c298f89-4303-0410-b956-a3cf2f4a3e73
80 lines
2.6 KiB
Diff
80 lines
2.6 KiB
Diff
Currently, Orion window setup uses hardcoded window indexes for each
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of the boot/cs0/cs1/cs2/PCIe WA windows. The static window allocation
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used can clash if board support code will ever attempt to configure
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both a dev2 and a PCIe WA window, as both of those use CPU mbus window
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#7 at present.
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This patch keeps track of the last used window, and opens subsequently
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requested windows sequentially, starting from 4. (Windows 0-3 are used
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as MEM/IO windows for the PCI/PCIe buses.)
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Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
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---
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arch/arm/mach-orion5x/addr-map.c | 20 +++++++++++++++-----
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1 files changed, 15 insertions(+), 5 deletions(-)
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--- a/arch/arm/mach-orion5x/addr-map.c
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+++ b/arch/arm/mach-orion5x/addr-map.c
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@@ -70,6 +70,7 @@
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struct mbus_dram_target_info orion5x_mbus_dram_info;
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+static int __initdata win_alloc_count;
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static int __init orion5x_cpu_win_can_remap(int win)
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{
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@@ -87,6 +88,9 @@
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static void __init setup_cpu_win(int win, u32 base, u32 size,
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u8 target, u8 attr, int remap)
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{
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+ if (win >= 8)
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+ panic("setup_cpu_win: trying to allocate window %d\n", win);
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+
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orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000);
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orion5x_write(CPU_WIN_CTRL(win),
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((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1);
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@@ -128,6 +132,7 @@
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TARGET_PCIE, ATTR_PCIE_MEM, -1);
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setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
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TARGET_PCI, ATTR_PCI_MEM, -1);
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+ win_alloc_count = 4;
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/*
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* Setup MBUS dram target info.
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@@ -156,25 +161,30 @@
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void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
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{
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- setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
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+ setup_cpu_win(win_alloc_count++, base, size,
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+ TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
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}
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void __init orion5x_setup_dev0_win(u32 base, u32 size)
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{
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- setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
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+ setup_cpu_win(win_alloc_count++, base, size,
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+ TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
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}
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void __init orion5x_setup_dev1_win(u32 base, u32 size)
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{
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- setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
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+ setup_cpu_win(win_alloc_count++, base, size,
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+ TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
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}
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void __init orion5x_setup_dev2_win(u32 base, u32 size)
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{
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- setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
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+ setup_cpu_win(win_alloc_count++, base, size,
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+ TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
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}
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void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
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{
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- setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
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+ setup_cpu_win(win_alloc_count++, base, size,
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+ TARGET_PCIE, ATTR_PCIE_WA, -1);
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}
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