mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-12 21:31:32 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@13835 3c298f89-4303-0410-b956-a3cf2f4a3e73
854 lines
22 KiB
Diff
854 lines
22 KiB
Diff
From 957a60be8a6b55da588df12e160ac53e3b36238e Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Fri, 2 Jan 2009 16:10:25 +0100
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Subject: [RFC 05/12] ath9k: move PCI code into separate file
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Convert 'struct pci_dev' to 'struct device' to make it usable on the AHB
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bus as well.
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
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---
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drivers/net/wireless/ath9k/Makefile | 1 +
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drivers/net/wireless/ath9k/core.h | 16 ++
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drivers/net/wireless/ath9k/main.c | 368 ++---------------------------------
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drivers/net/wireless/ath9k/pci.c | 357 +++++++++++++++++++++++++++++++++
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4 files changed, 395 insertions(+), 347 deletions(-)
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--- a/drivers/net/wireless/ath9k/Makefile
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+++ b/drivers/net/wireless/ath9k/Makefile
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@@ -11,6 +11,7 @@ ath9k-y += hw.o \
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xmit.o \
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rc.o
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+ath9k-$(CONFIG_PCI) += pci.o
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ath9k-$(CONFIG_ATH9K_DEBUG) += debug.o
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obj-$(CONFIG_ATH9K) += ath9k.o
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--- a/drivers/net/wireless/ath9k/core.h
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+++ b/drivers/net/wireless/ath9k/core.h
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@@ -857,4 +857,20 @@ static inline void ath_bus_cleanup(struc
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sc->bus_ops->cleanup(sc);
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}
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+extern struct ieee80211_ops ath9k_ops;
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+
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+irqreturn_t ath_isr(int irq, void *dev);
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+int ath_attach(u16 devid, struct ath_softc *sc);
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+void ath_detach(struct ath_softc *sc);
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+const char *ath_mac_bb_name(u32 mac_bb_version);
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+const char *ath_rf_name(u16 rf_version);
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+
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+#ifdef CONFIG_PCI
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+int ath_pci_init(void);
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+void ath_pci_exit(void);
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+#else
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+static inline int ath_pci_init(void) { return 0; };
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+static inline void ath_pci_exit(void) {};
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+#endif
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+
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#endif /* CORE_H */
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--- a/drivers/net/wireless/ath9k/main.c
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+++ b/drivers/net/wireless/ath9k/main.c
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@@ -28,37 +28,6 @@ MODULE_DESCRIPTION("Support for Atheros
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MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
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MODULE_LICENSE("Dual BSD/GPL");
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-static struct pci_device_id ath_pci_id_table[] __devinitdata = {
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- { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
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- { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
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- { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
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- { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
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- { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
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- { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
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- { 0 }
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-};
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-
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-static void ath_detach(struct ath_softc *sc);
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-
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-/* return bus cachesize in 4B word units */
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-static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
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-{
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- u8 u8tmp;
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-
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- pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
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- *csz = (int)u8tmp;
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-
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- /*
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- * This check was put in to avoid "unplesant" consequences if
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- * the bootrom has not fully initialized all PCI devices.
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- * Sometimes the cache line size register is not set
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- */
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-
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- if (*csz == 0)
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- *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
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-}
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-
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-
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static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
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{
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sc->cur_rate_table = sc->hw_rate_table[mode];
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@@ -499,7 +468,7 @@ static void ath9k_tasklet(unsigned long
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ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
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}
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-static irqreturn_t ath_isr(int irq, void *dev)
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+irqreturn_t ath_isr(int irq, void *dev)
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{
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struct ath_softc *sc = dev;
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struct ath_hal *ah = sc->sc_ah;
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@@ -1287,7 +1256,7 @@ static int ath_start_rfkill_poll(struct
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}
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#endif /* CONFIG_RFKILL */
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-static void ath_detach(struct ath_softc *sc)
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+void ath_detach(struct ath_softc *sc)
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{
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struct ieee80211_hw *hw = sc->hw;
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int i = 0;
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@@ -1538,7 +1507,7 @@ bad:
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return error;
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}
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-static int ath_attach(u16 devid, struct ath_softc *sc)
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+int ath_attach(u16 devid, struct ath_softc *sc)
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{
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struct ieee80211_hw *hw = sc->hw;
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int error = 0;
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@@ -2466,7 +2435,7 @@ static int ath9k_ampdu_action(struct iee
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return ret;
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}
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-static struct ieee80211_ops ath9k_ops = {
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+struct ieee80211_ops ath9k_ops = {
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.tx = ath9k_tx,
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.start = ath9k_start,
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.stop = ath9k_stop,
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@@ -2510,7 +2479,7 @@ static struct {
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/*
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* Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
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*/
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-static const char *
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+const char *
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ath_mac_bb_name(u32 mac_bb_version)
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{
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int i;
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@@ -2527,7 +2496,7 @@ ath_mac_bb_name(u32 mac_bb_version)
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/*
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* Return the RF name. "????" is returned if the RF is unknown.
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*/
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-static const char *
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+const char *
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ath_rf_name(u16 rf_version)
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{
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int i;
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@@ -2541,306 +2510,7 @@ ath_rf_name(u16 rf_version)
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return "????";
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}
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-static dma_addr_t ath_pci_map_single_to_device(struct ath_softc *sc,
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- void *p, size_t size)
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-{
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- return pci_map_single(sc->pdev, p, size, PCI_DMA_TODEVICE);
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-}
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-
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-static void ath_pci_unmap_single_to_device(struct ath_softc *sc,
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- dma_addr_t da, size_t size)
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-{
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- pci_unmap_single(sc->pdev, da, size, PCI_DMA_TODEVICE);
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-}
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-
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-static dma_addr_t ath_pci_map_single_from_device(struct ath_softc *sc,
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- void *p, size_t size)
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-{
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- return pci_map_single(sc->pdev, p, size, PCI_DMA_FROMDEVICE);
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-}
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-
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-static void ath_pci_unmap_single_from_device(struct ath_softc *sc,
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- dma_addr_t da, size_t size)
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-{
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- pci_unmap_single(sc->pdev, da, size, PCI_DMA_FROMDEVICE);
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-}
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-
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-static int ath_pci_dma_mapping_error(struct ath_softc *sc, dma_addr_t da)
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-{
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- return pci_dma_mapping_error(sc->pdev, da);
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-}
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-
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-static void ath_pci_sync_single_for_cpu(struct ath_softc *sc, dma_addr_t da,
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- size_t size)
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-{
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- pci_dma_sync_single_for_cpu(sc->pdev, da, size,
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- PCI_DMA_FROMDEVICE);
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-}
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-
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-static void *ath_pci_dma_alloc(struct ath_softc *sc, size_t size,
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- dma_addr_t *pda)
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-{
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- return pci_alloc_consistent(sc->pdev, size, pda);
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-}
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-
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-static void ath_pci_dma_free(struct ath_softc *sc, size_t size,
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- void *p, dma_addr_t da)
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-{
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- pci_free_consistent(sc->pdev, size, p, da);
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-}
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-
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-static u32 ath_pci_reg_read(struct ath_hal *ah, unsigned reg)
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-{
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- return ioread32(ah->ah_sh + reg);
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-}
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-
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-static void ath_pci_reg_write(struct ath_hal *ah, unsigned reg, u32 val)
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-{
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- iowrite32(val, ah->ah_sh + reg);
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-}
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-
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-static void ath_pci_cleanup(struct ath_softc *sc)
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-{
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- ath_detach(sc);
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- if (sc->pdev->irq)
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- free_irq(sc->pdev->irq, sc);
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- pci_iounmap(sc->pdev, sc->mem);
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- pci_release_region(sc->pdev, 0);
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- pci_disable_device(sc->pdev);
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- ieee80211_free_hw(sc->hw);
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-}
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-
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-static struct ath_bus_ops ath_pci_bus_ops = {
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- .dma_map_single_to_device = ath_pci_map_single_to_device,
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- .dma_unmap_single_to_device = ath_pci_unmap_single_to_device,
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- .dma_map_single_from_device = ath_pci_map_single_from_device,
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- .dma_unmap_single_from_device = ath_pci_unmap_single_from_device,
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- .dma_map_single_to_device = ath_pci_map_single_to_device,
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- .dma_mapping_error = ath_pci_dma_mapping_error,
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- .dma_sync_single_for_cpu = ath_pci_sync_single_for_cpu,
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- .dma_alloc = ath_pci_dma_alloc,
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- .dma_free = ath_pci_dma_free,
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-
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- .reg_read = ath_pci_reg_read,
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- .reg_write = ath_pci_reg_write,
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-
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- .read_cachesize = ath_pci_read_cachesize,
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-
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- .cleanup = ath_pci_cleanup,
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-};
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-
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-static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
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-{
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- void __iomem *mem;
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- struct ath_softc *sc;
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- struct ieee80211_hw *hw;
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- u8 csz;
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- u32 val;
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- int ret = 0;
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- struct ath_hal *ah;
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-
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- if (pci_enable_device(pdev))
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- return -EIO;
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-
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- ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
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-
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- if (ret) {
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- printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
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- goto bad;
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- }
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-
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- ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
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-
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- if (ret) {
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- printk(KERN_ERR "ath9k: 32-bit DMA consistent "
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- "DMA enable failed\n");
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- goto bad;
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- }
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-
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- /*
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- * Cache line size is used to size and align various
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- * structures used to communicate with the hardware.
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- */
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- pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
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- if (csz == 0) {
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- /*
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- * Linux 2.4.18 (at least) writes the cache line size
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- * register as a 16-bit wide register which is wrong.
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- * We must have this setup properly for rx buffer
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- * DMA to work so force a reasonable value here if it
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- * comes up zero.
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- */
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- csz = L1_CACHE_BYTES / sizeof(u32);
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- pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
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- }
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- /*
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- * The default setting of latency timer yields poor results,
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- * set it to the value used by other systems. It may be worth
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- * tweaking this setting more.
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- */
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- pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
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-
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- pci_set_master(pdev);
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-
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- /*
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- * Disable the RETRY_TIMEOUT register (0x41) to keep
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- * PCI Tx retries from interfering with C3 CPU state.
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- */
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- pci_read_config_dword(pdev, 0x40, &val);
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- if ((val & 0x0000ff00) != 0)
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- pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
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-
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- ret = pci_request_region(pdev, 0, "ath9k");
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- if (ret) {
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- dev_err(&pdev->dev, "PCI memory region reserve error\n");
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- ret = -ENODEV;
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- goto bad;
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- }
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-
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- mem = pci_iomap(pdev, 0, 0);
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- if (!mem) {
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- printk(KERN_ERR "PCI memory map error\n") ;
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- ret = -EIO;
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- goto bad1;
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- }
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-
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- hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
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- if (hw == NULL) {
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- printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
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- goto bad2;
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- }
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-
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- SET_IEEE80211_DEV(hw, &pdev->dev);
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- pci_set_drvdata(pdev, hw);
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-
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- sc = hw->priv;
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- sc->hw = hw;
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- sc->pdev = pdev;
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- sc->mem = mem;
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- sc->bus_ops = &ath_pci_bus_ops;
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-
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- if (ath_attach(id->device, sc) != 0) {
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- ret = -ENODEV;
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- goto bad3;
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- }
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-
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- /* setup interrupt service routine */
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-
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- if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
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- printk(KERN_ERR "%s: request_irq failed\n",
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- wiphy_name(hw->wiphy));
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- ret = -EIO;
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- goto bad4;
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- }
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-
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- ah = sc->sc_ah;
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- printk(KERN_INFO
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- "%s: Atheros AR%s MAC/BB Rev:%x "
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- "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
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- wiphy_name(hw->wiphy),
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- ath_mac_bb_name(ah->ah_macVersion),
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- ah->ah_macRev,
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- ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
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- ah->ah_phyRev,
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- (unsigned long)mem, pdev->irq);
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-
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- return 0;
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-bad4:
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- ath_detach(sc);
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-bad3:
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- ieee80211_free_hw(hw);
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-bad2:
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- pci_iounmap(pdev, mem);
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-bad1:
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- pci_release_region(pdev, 0);
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-bad:
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- pci_disable_device(pdev);
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- return ret;
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-}
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-
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-static void ath_pci_remove(struct pci_dev *pdev)
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-{
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- struct ieee80211_hw *hw = pci_get_drvdata(pdev);
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- struct ath_softc *sc = hw->priv;
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-
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- ath_pci_cleanup(sc);
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-}
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-
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-#ifdef CONFIG_PM
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-
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-static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
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-{
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- struct ieee80211_hw *hw = pci_get_drvdata(pdev);
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- struct ath_softc *sc = hw->priv;
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-
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- ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
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-
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-#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
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- if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
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- cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
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-#endif
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-
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- pci_save_state(pdev);
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- pci_disable_device(pdev);
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- pci_set_power_state(pdev, 3);
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-
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- return 0;
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-}
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-
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-static int ath_pci_resume(struct pci_dev *pdev)
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-{
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- struct ieee80211_hw *hw = pci_get_drvdata(pdev);
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- struct ath_softc *sc = hw->priv;
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- u32 val;
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- int err;
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-
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- err = pci_enable_device(pdev);
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- if (err)
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- return err;
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- pci_restore_state(pdev);
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- /*
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- * Suspend/Resume resets the PCI configuration space, so we have to
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- * re-disable the RETRY_TIMEOUT register (0x41) to keep
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- * PCI Tx retries from interfering with C3 CPU state
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- */
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- pci_read_config_dword(pdev, 0x40, &val);
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- if ((val & 0x0000ff00) != 0)
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- pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
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-
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- /* Enable LED */
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- ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
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- AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
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- ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
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-
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-#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
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- /*
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- * check the h/w rfkill state on resume
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- * and start the rfkill poll timer
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- */
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- if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
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- queue_delayed_work(sc->hw->workqueue,
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- &sc->rf_kill.rfkill_poll, 0);
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-#endif
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-
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- return 0;
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-}
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-
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-#endif /* CONFIG_PM */
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-
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-MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
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-
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-static struct pci_driver ath_pci_driver = {
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- .name = "ath9k",
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- .id_table = ath_pci_id_table,
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- .probe = ath_pci_probe,
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- .remove = ath_pci_remove,
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-#ifdef CONFIG_PM
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- .suspend = ath_pci_suspend,
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- .resume = ath_pci_resume,
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-#endif /* CONFIG_PM */
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-};
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-
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-static int __init init_ath_pci(void)
|
|
+static int __init ath9k_init(void)
|
|
{
|
|
int error;
|
|
|
|
@@ -2852,26 +2522,30 @@ static int __init init_ath_pci(void)
|
|
printk(KERN_ERR
|
|
"Unable to register rate control algorithm: %d\n",
|
|
error);
|
|
- ath_rate_control_unregister();
|
|
- return error;
|
|
+ goto err_out;
|
|
}
|
|
|
|
- if (pci_register_driver(&ath_pci_driver) < 0) {
|
|
+ error = ath_pci_init();
|
|
+ if (error < 0) {
|
|
printk(KERN_ERR
|
|
"ath_pci: No devices found, driver not installed.\n");
|
|
- ath_rate_control_unregister();
|
|
- pci_unregister_driver(&ath_pci_driver);
|
|
- return -ENODEV;
|
|
+ error = -ENODEV;
|
|
+ goto err_rate_unregister;
|
|
}
|
|
|
|
return 0;
|
|
+
|
|
+ err_rate_unregister:
|
|
+ ath_rate_control_unregister();
|
|
+ err_out:
|
|
+ return error;
|
|
}
|
|
-module_init(init_ath_pci);
|
|
+module_init(ath9k_init);
|
|
|
|
-static void __exit exit_ath_pci(void)
|
|
+static void __exit ath9k_exit(void)
|
|
{
|
|
+ ath_pci_exit();
|
|
ath_rate_control_unregister();
|
|
- pci_unregister_driver(&ath_pci_driver);
|
|
printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
|
|
}
|
|
-module_exit(exit_ath_pci);
|
|
+module_exit(ath9k_exit);
|
|
--- /dev/null
|
|
+++ b/drivers/net/wireless/ath9k/pci.c
|
|
@@ -0,0 +1,357 @@
|
|
+/*
|
|
+ * Copyright (c) 2008 Atheros Communications Inc.
|
|
+ *
|
|
+ * Permission to use, copy, modify, and/or distribute this software for any
|
|
+ * purpose with or without fee is hereby granted, provided that the above
|
|
+ * copyright notice and this permission notice appear in all copies.
|
|
+ *
|
|
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
|
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
|
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
|
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
|
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
|
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
|
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
|
+ */
|
|
+
|
|
+#include <linux/nl80211.h>
|
|
+#include "core.h"
|
|
+#include "reg.h"
|
|
+#include "hw.h"
|
|
+
|
|
+static struct pci_device_id ath_pci_id_table[] __devinitdata = {
|
|
+ { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
|
|
+ { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
|
|
+ { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
|
|
+ { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
|
|
+ { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
|
|
+ { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
|
|
+ { 0 }
|
|
+};
|
|
+
|
|
+/* return bus cachesize in 4B word units */
|
|
+static void ath_pci_read_cachesize(struct ath_softc *sc, int *csz)
|
|
+{
|
|
+ u8 u8tmp;
|
|
+
|
|
+ pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
|
|
+ *csz = (int)u8tmp;
|
|
+
|
|
+ /*
|
|
+ * This check was put in to avoid "unplesant" consequences if
|
|
+ * the bootrom has not fully initialized all PCI devices.
|
|
+ * Sometimes the cache line size register is not set
|
|
+ */
|
|
+
|
|
+ if (*csz == 0)
|
|
+ *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
|
|
+}
|
|
+
|
|
+static dma_addr_t ath_pci_map_single_to_device(struct ath_softc *sc,
|
|
+ void *p, size_t size)
|
|
+{
|
|
+ return pci_map_single(sc->pdev, p, size, PCI_DMA_TODEVICE);
|
|
+}
|
|
+
|
|
+static void ath_pci_unmap_single_to_device(struct ath_softc *sc,
|
|
+ dma_addr_t da, size_t size)
|
|
+{
|
|
+ pci_unmap_single(sc->pdev, da, size, PCI_DMA_TODEVICE);
|
|
+}
|
|
+
|
|
+static dma_addr_t ath_pci_map_single_from_device(struct ath_softc *sc,
|
|
+ void *p, size_t size)
|
|
+{
|
|
+ return pci_map_single(sc->pdev, p, size, PCI_DMA_FROMDEVICE);
|
|
+}
|
|
+
|
|
+static void ath_pci_unmap_single_from_device(struct ath_softc *sc,
|
|
+ dma_addr_t da, size_t size)
|
|
+{
|
|
+ pci_unmap_single(sc->pdev, da, size, PCI_DMA_FROMDEVICE);
|
|
+}
|
|
+
|
|
+static int ath_pci_dma_mapping_error(struct ath_softc *sc, dma_addr_t da)
|
|
+{
|
|
+ return pci_dma_mapping_error(sc->pdev, da);
|
|
+}
|
|
+
|
|
+static void ath_pci_sync_single_for_cpu(struct ath_softc *sc, dma_addr_t da,
|
|
+ size_t size)
|
|
+{
|
|
+ pci_dma_sync_single_for_cpu(sc->pdev, da, size,
|
|
+ PCI_DMA_FROMDEVICE);
|
|
+}
|
|
+
|
|
+static void *ath_pci_dma_alloc(struct ath_softc *sc, size_t size,
|
|
+ dma_addr_t *pda)
|
|
+{
|
|
+ return pci_alloc_consistent(sc->pdev, size, pda);
|
|
+}
|
|
+
|
|
+static void ath_pci_dma_free(struct ath_softc *sc, size_t size,
|
|
+ void *p, dma_addr_t da)
|
|
+{
|
|
+ pci_free_consistent(sc->pdev, size, p, da);
|
|
+}
|
|
+
|
|
+static u32 ath_pci_reg_read(struct ath_hal *ah, unsigned reg)
|
|
+{
|
|
+ return ioread32(ah->ah_sh + reg);
|
|
+}
|
|
+
|
|
+static void ath_pci_reg_write(struct ath_hal *ah, unsigned reg, u32 val)
|
|
+{
|
|
+ iowrite32(val, ah->ah_sh + reg);
|
|
+}
|
|
+
|
|
+static void ath_pci_cleanup(struct ath_softc *sc)
|
|
+{
|
|
+ ath_detach(sc);
|
|
+ if (sc->pdev->irq)
|
|
+ free_irq(sc->pdev->irq, sc);
|
|
+ pci_iounmap(sc->pdev, sc->mem);
|
|
+ pci_release_region(sc->pdev, 0);
|
|
+ pci_disable_device(sc->pdev);
|
|
+ ieee80211_free_hw(sc->hw);
|
|
+}
|
|
+
|
|
+static struct ath_bus_ops ath_pci_bus_ops = {
|
|
+ .dma_map_single_to_device = ath_pci_map_single_to_device,
|
|
+ .dma_unmap_single_to_device = ath_pci_unmap_single_to_device,
|
|
+ .dma_map_single_from_device = ath_pci_map_single_from_device,
|
|
+ .dma_unmap_single_from_device = ath_pci_unmap_single_from_device,
|
|
+ .dma_map_single_to_device = ath_pci_map_single_to_device,
|
|
+ .dma_mapping_error = ath_pci_dma_mapping_error,
|
|
+ .dma_sync_single_for_cpu = ath_pci_sync_single_for_cpu,
|
|
+ .dma_alloc = ath_pci_dma_alloc,
|
|
+ .dma_free = ath_pci_dma_free,
|
|
+
|
|
+ .reg_read = ath_pci_reg_read,
|
|
+ .reg_write = ath_pci_reg_write,
|
|
+
|
|
+ .read_cachesize = ath_pci_read_cachesize,
|
|
+
|
|
+ .cleanup = ath_pci_cleanup,
|
|
+};
|
|
+
|
|
+static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|
+{
|
|
+ void __iomem *mem;
|
|
+ struct ath_softc *sc;
|
|
+ struct ieee80211_hw *hw;
|
|
+ u8 csz;
|
|
+ u32 val;
|
|
+ int ret = 0;
|
|
+ struct ath_hal *ah;
|
|
+
|
|
+ if (pci_enable_device(pdev))
|
|
+ return -EIO;
|
|
+
|
|
+ ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
|
|
+
|
|
+ if (ret) {
|
|
+ printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
|
|
+ goto bad;
|
|
+ }
|
|
+
|
|
+ ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
|
|
+
|
|
+ if (ret) {
|
|
+ printk(KERN_ERR "ath9k: 32-bit DMA consistent "
|
|
+ "DMA enable failed\n");
|
|
+ goto bad;
|
|
+ }
|
|
+
|
|
+ /*
|
|
+ * Cache line size is used to size and align various
|
|
+ * structures used to communicate with the hardware.
|
|
+ */
|
|
+ pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
|
|
+ if (csz == 0) {
|
|
+ /*
|
|
+ * Linux 2.4.18 (at least) writes the cache line size
|
|
+ * register as a 16-bit wide register which is wrong.
|
|
+ * We must have this setup properly for rx buffer
|
|
+ * DMA to work so force a reasonable value here if it
|
|
+ * comes up zero.
|
|
+ */
|
|
+ csz = L1_CACHE_BYTES / sizeof(u32);
|
|
+ pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
|
|
+ }
|
|
+ /*
|
|
+ * The default setting of latency timer yields poor results,
|
|
+ * set it to the value used by other systems. It may be worth
|
|
+ * tweaking this setting more.
|
|
+ */
|
|
+ pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
|
|
+
|
|
+ pci_set_master(pdev);
|
|
+
|
|
+ /*
|
|
+ * Disable the RETRY_TIMEOUT register (0x41) to keep
|
|
+ * PCI Tx retries from interfering with C3 CPU state.
|
|
+ */
|
|
+ pci_read_config_dword(pdev, 0x40, &val);
|
|
+ if ((val & 0x0000ff00) != 0)
|
|
+ pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
|
|
+
|
|
+ ret = pci_request_region(pdev, 0, "ath9k");
|
|
+ if (ret) {
|
|
+ dev_err(&pdev->dev, "PCI memory region reserve error\n");
|
|
+ ret = -ENODEV;
|
|
+ goto bad;
|
|
+ }
|
|
+
|
|
+ mem = pci_iomap(pdev, 0, 0);
|
|
+ if (!mem) {
|
|
+ printk(KERN_ERR "PCI memory map error\n") ;
|
|
+ ret = -EIO;
|
|
+ goto bad1;
|
|
+ }
|
|
+
|
|
+ hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
|
|
+ if (hw == NULL) {
|
|
+ printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
|
|
+ goto bad2;
|
|
+ }
|
|
+
|
|
+ SET_IEEE80211_DEV(hw, &pdev->dev);
|
|
+ pci_set_drvdata(pdev, hw);
|
|
+
|
|
+ sc = hw->priv;
|
|
+ sc->hw = hw;
|
|
+ sc->pdev = pdev;
|
|
+ sc->mem = mem;
|
|
+ sc->bus_ops = &ath_pci_bus_ops;
|
|
+
|
|
+ if (ath_attach(id->device, sc) != 0) {
|
|
+ ret = -ENODEV;
|
|
+ goto bad3;
|
|
+ }
|
|
+
|
|
+ /* setup interrupt service routine */
|
|
+
|
|
+ if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
|
|
+ printk(KERN_ERR "%s: request_irq failed\n",
|
|
+ wiphy_name(hw->wiphy));
|
|
+ ret = -EIO;
|
|
+ goto bad4;
|
|
+ }
|
|
+
|
|
+ ah = sc->sc_ah;
|
|
+ printk(KERN_INFO
|
|
+ "%s: Atheros AR%s MAC/BB Rev:%x "
|
|
+ "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
|
|
+ wiphy_name(hw->wiphy),
|
|
+ ath_mac_bb_name(ah->ah_macVersion),
|
|
+ ah->ah_macRev,
|
|
+ ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
|
|
+ ah->ah_phyRev,
|
|
+ (unsigned long)mem, pdev->irq);
|
|
+
|
|
+ return 0;
|
|
+bad4:
|
|
+ ath_detach(sc);
|
|
+bad3:
|
|
+ ieee80211_free_hw(hw);
|
|
+bad2:
|
|
+ pci_iounmap(pdev, mem);
|
|
+bad1:
|
|
+ pci_release_region(pdev, 0);
|
|
+bad:
|
|
+ pci_disable_device(pdev);
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static void ath_pci_remove(struct pci_dev *pdev)
|
|
+{
|
|
+ struct ieee80211_hw *hw = pci_get_drvdata(pdev);
|
|
+ struct ath_softc *sc = hw->priv;
|
|
+
|
|
+ ath_pci_cleanup(sc);
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_PM
|
|
+
|
|
+static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
|
|
+{
|
|
+ struct ieee80211_hw *hw = pci_get_drvdata(pdev);
|
|
+ struct ath_softc *sc = hw->priv;
|
|
+
|
|
+ ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
|
|
+
|
|
+#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
|
|
+ if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
|
|
+ cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
|
|
+#endif
|
|
+
|
|
+ pci_save_state(pdev);
|
|
+ pci_disable_device(pdev);
|
|
+ pci_set_power_state(pdev, 3);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int ath_pci_resume(struct pci_dev *pdev)
|
|
+{
|
|
+ struct ieee80211_hw *hw = pci_get_drvdata(pdev);
|
|
+ struct ath_softc *sc = hw->priv;
|
|
+ u32 val;
|
|
+ int err;
|
|
+
|
|
+ err = pci_enable_device(pdev);
|
|
+ if (err)
|
|
+ return err;
|
|
+ pci_restore_state(pdev);
|
|
+ /*
|
|
+ * Suspend/Resume resets the PCI configuration space, so we have to
|
|
+ * re-disable the RETRY_TIMEOUT register (0x41) to keep
|
|
+ * PCI Tx retries from interfering with C3 CPU state
|
|
+ */
|
|
+ pci_read_config_dword(pdev, 0x40, &val);
|
|
+ if ((val & 0x0000ff00) != 0)
|
|
+ pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
|
|
+
|
|
+ /* Enable LED */
|
|
+ ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
|
|
+ AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
|
|
+ ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
|
|
+
|
|
+#if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
|
|
+ /*
|
|
+ * check the h/w rfkill state on resume
|
|
+ * and start the rfkill poll timer
|
|
+ */
|
|
+ if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
|
|
+ queue_delayed_work(sc->hw->workqueue,
|
|
+ &sc->rf_kill.rfkill_poll, 0);
|
|
+#endif
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+#endif /* CONFIG_PM */
|
|
+
|
|
+MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
|
|
+
|
|
+static struct pci_driver ath_pci_driver = {
|
|
+ .name = "ath9k",
|
|
+ .id_table = ath_pci_id_table,
|
|
+ .probe = ath_pci_probe,
|
|
+ .remove = ath_pci_remove,
|
|
+#ifdef CONFIG_PM
|
|
+ .suspend = ath_pci_suspend,
|
|
+ .resume = ath_pci_resume,
|
|
+#endif /* CONFIG_PM */
|
|
+};
|
|
+
|
|
+int __init ath_pci_init(void)
|
|
+{
|
|
+ return pci_register_driver(&ath_pci_driver);
|
|
+}
|
|
+
|
|
+void ath_pci_exit(void)
|
|
+{
|
|
+ pci_unregister_driver(&ath_pci_driver);
|
|
+}
|