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e0b80e41eb
Tested on the following boards: ALFA AP96 TL-MR3220 v1 TL-WR1043ND v1 TL-WR2543ND v1 TL-WR703N v1 TL-WR741ND v1 TL-WR741ND v4 WNDR3700 v1 WZR-HP-G300NH git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29868 3c298f89-4303-0410-b956-a3cf2f4a3e73
155 lines
4.4 KiB
Diff
155 lines
4.4 KiB
Diff
From e69d89040d4884ea4069352338f555694e65fe70 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Fri, 9 Dec 2011 21:30:03 +0100
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Subject: [PATCH 26/35] MIPS: ath79: rework IP2/IP3 interrupt handling
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The current implementation assumes that flushing the
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DDR writeback buffer is required for IP2/IP3 interrupts,
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however this is not true for all SoCs.
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Use SoC specific IP2/IP3 handlers instead of flushing
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the buffers in the dispatcher code.
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
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---
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arch/mips/ath79/irq.c | 92 ++++++++++++++++++++++++++++++++++++++-----------
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1 files changed, 72 insertions(+), 20 deletions(-)
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--- a/arch/mips/ath79/irq.c
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+++ b/arch/mips/ath79/irq.c
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@@ -1,7 +1,7 @@
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/*
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* Atheros AR71xx/AR724x/AR913x specific interrupt handling
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*
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- * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
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+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Atheros' 2.6.15 BSP
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@@ -23,8 +23,8 @@
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include "common.h"
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-static unsigned int ath79_ip2_flush_reg;
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-static unsigned int ath79_ip3_flush_reg;
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+static void (*ath79_ip2_handler)(void);
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+static void (*ath79_ip3_handler)(void);
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static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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@@ -152,10 +152,8 @@ asmlinkage void plat_irq_dispatch(void)
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if (pending & STATUSF_IP7)
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do_IRQ(ATH79_CPU_IRQ_TIMER);
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- else if (pending & STATUSF_IP2) {
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- ath79_ddr_wb_flush(ath79_ip2_flush_reg);
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- do_IRQ(ATH79_CPU_IRQ_IP2);
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- }
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+ else if (pending & STATUSF_IP2)
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+ ath79_ip2_handler();
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else if (pending & STATUSF_IP4)
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do_IRQ(ATH79_CPU_IRQ_GE0);
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@@ -163,10 +161,8 @@ asmlinkage void plat_irq_dispatch(void)
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else if (pending & STATUSF_IP5)
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do_IRQ(ATH79_CPU_IRQ_GE1);
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- else if (pending & STATUSF_IP3) {
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- ath79_ddr_wb_flush(ath79_ip3_flush_reg);
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- do_IRQ(ATH79_CPU_IRQ_USB);
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- }
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+ else if (pending & STATUSF_IP3)
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+ ath79_ip3_handler();
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else if (pending & STATUSF_IP6)
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do_IRQ(ATH79_CPU_IRQ_MISC);
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@@ -175,22 +171,78 @@ asmlinkage void plat_irq_dispatch(void)
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spurious_interrupt();
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}
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+/*
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+ * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
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+ * these devices typically allocate coherent DMA memory, however the
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+ * DMA controller may still have some unsynchronized data in the FIFO.
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+ * Issue a flush in the handlers to ensure that the driver sees
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+ * the update.
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+ */
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+static void ar71xx_ip2_handler(void)
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+{
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+ ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
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+ do_IRQ(ATH79_CPU_IRQ_IP2);
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+}
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+
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+static void ar724x_ip2_handler(void)
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+{
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+ ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE);
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+ do_IRQ(ATH79_CPU_IRQ_IP2);
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+}
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+
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+static void ar913x_ip2_handler(void)
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+{
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+ ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC);
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+ do_IRQ(ATH79_CPU_IRQ_IP2);
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+}
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+
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+static void ar933x_ip2_handler(void)
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+{
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+ ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC);
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+ do_IRQ(ATH79_CPU_IRQ_IP2);
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+}
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+
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+static void ar71xx_ip3_handler(void)
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+{
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+ ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
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+ do_IRQ(ATH79_CPU_IRQ_USB);
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+}
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+
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+static void ar724x_ip3_handler(void)
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+{
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+ ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB);
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+ do_IRQ(ATH79_CPU_IRQ_USB);
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+}
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+
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+static void ar913x_ip3_handler(void)
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+{
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+ ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB);
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+ do_IRQ(ATH79_CPU_IRQ_USB);
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+}
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+
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+static void ar933x_ip3_handler(void)
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+{
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+ ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB);
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+ do_IRQ(ATH79_CPU_IRQ_USB);
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+}
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+
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void __init arch_init_irq(void)
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{
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if (soc_is_ar71xx()) {
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- ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI;
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- ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB;
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+ ath79_ip2_handler = ar71xx_ip2_handler;
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+ ath79_ip3_handler = ar71xx_ip3_handler;
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} else if (soc_is_ar724x()) {
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- ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE;
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- ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB;
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+ ath79_ip2_handler = ar724x_ip2_handler;
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+ ath79_ip3_handler = ar724x_ip3_handler;
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} else if (soc_is_ar913x()) {
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- ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
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- ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
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+ ath79_ip2_handler = ar913x_ip2_handler;
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+ ath79_ip3_handler = ar913x_ip3_handler;
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} else if (soc_is_ar933x()) {
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- ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC;
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- ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB;
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- } else
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+ ath79_ip2_handler = ar933x_ip2_handler;
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+ ath79_ip3_handler = ar933x_ip3_handler;
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+ } else {
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BUG();
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+ }
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cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
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mips_cpu_irq_init();
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