mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-14 07:11:52 +02:00
84e11fcd5a
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19458 3c298f89-4303-0410-b956-a3cf2f4a3e73
34 lines
967 B
Diff
34 lines
967 B
Diff
--- a/arch/mips/kernel/cevt-r4k.c
|
|
+++ b/arch/mips/kernel/cevt-r4k.c
|
|
@@ -22,6 +22,22 @@
|
|
|
|
#ifndef CONFIG_MIPS_MT_SMTC
|
|
|
|
+/*
|
|
+ * Compare interrupt can be routed and latched outside the core,
|
|
+ * so a single execution hazard barrier may not be enough to give
|
|
+ * it time to clear as seen in the Cause register. 4 time the
|
|
+ * pipeline depth seems reasonably conservative, and empirically
|
|
+ * works better in configurations with high CPU/bus clock ratios.
|
|
+ */
|
|
+
|
|
+#define compare_change_hazard() \
|
|
+ do { \
|
|
+ irq_disable_hazard(); \
|
|
+ irq_disable_hazard(); \
|
|
+ irq_disable_hazard(); \
|
|
+ irq_disable_hazard(); \
|
|
+ } while (0)
|
|
+
|
|
static int mips_next_event(unsigned long delta,
|
|
struct clock_event_device *evt)
|
|
{
|
|
@@ -31,6 +47,7 @@ static int mips_next_event(unsigned long
|
|
cnt = read_c0_count();
|
|
cnt += delta;
|
|
write_c0_compare(cnt);
|
|
+ compare_change_hazard();
|
|
res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
|
|
return res;
|
|
}
|