mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-21 21:49:00 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31335 3c298f89-4303-0410-b956-a3cf2f4a3e73
397 lines
12 KiB
Diff
397 lines
12 KiB
Diff
From a1a9dcf7554df9bbf23ca0933e645b2327abbb8b Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 10 Aug 2011 15:32:16 +0200
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Subject: [PATCH 18/73] NET: MIPS: lantiq: make etop ethernet work on ase/ar9
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Extend the driver to handle the different DMA channel layout for AR9 and
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Amazon-SE SoCs. The patch also adds support for the integrated PHY found
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on Amazon-SE and the gigabit switch found inside the AR9.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Cc: netdev@vger.kernel.org
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---
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.../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 22 +---
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.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 10 ++
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arch/mips/lantiq/xway/devices.c | 11 +-
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drivers/net/ethernet/lantiq_etop.c | 171 ++++++++++++++++++--
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4 files changed, 174 insertions(+), 40 deletions(-)
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--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
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+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
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@@ -38,26 +38,8 @@
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#define MIPS_CPU_TIMER_IRQ 7
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-#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
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-#define LTQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
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-#define LTQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
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-#define LTQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
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-#define LTQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
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-#define LTQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
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-#define LTQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
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-#define LTQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
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-#define LTQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
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-#define LTQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
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-#define LTQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
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-#define LTQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
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-#define LTQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
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-#define LTQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
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-#define LTQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
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-#define LTQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
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-#define LTQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
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-#define LTQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
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-#define LTQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
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-#define LTQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
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+#define LTQ_DMA_ETOP ((ltq_is_ase()) ? \
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+ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
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#define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24)
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--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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@@ -82,6 +82,7 @@
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#define LTQ_PMU_SIZE 0x1000
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#define PMU_DMA 0x0020
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+#define PMU_EPHY 0x0080
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#define PMU_USB 0x8041
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#define PMU_LED 0x0800
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#define PMU_GPT 0x1000
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@@ -93,6 +94,10 @@
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#define LTQ_ETOP_BASE_ADDR 0x1E180000
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#define LTQ_ETOP_SIZE 0x40000
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+/* GBIT - gigabit switch */
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+#define LTQ_GBIT_BASE_ADDR 0x1E108000
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+#define LTQ_GBIT_SIZE 0x200
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+
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/* DMA */
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#define LTQ_DMA_BASE_ADDR 0x1E104100
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#define LTQ_DMA_SIZE 0x800
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@@ -147,6 +152,11 @@ extern void ltq_pmu_enable(unsigned int
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extern void ltq_pmu_disable(unsigned int module);
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extern void ltq_cgu_enable(unsigned int clk);
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+static inline int ltq_is_ase(void)
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+{
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+ return (ltq_get_soc_type() == SOC_TYPE_AMAZON_SE);
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+}
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+
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static inline int ltq_is_ar9(void)
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{
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return (ltq_get_soc_type() == SOC_TYPE_AR9);
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--- a/arch/mips/lantiq/xway/devices.c
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+++ b/arch/mips/lantiq/xway/devices.c
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@@ -74,18 +74,23 @@ void __init ltq_register_ase_asc(void)
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}
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/* ethernet */
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-static struct resource ltq_etop_resources =
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- MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE);
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+static struct resource ltq_etop_resources[] = {
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+ MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE),
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+ MEM_RES("gbit", LTQ_GBIT_BASE_ADDR, LTQ_GBIT_SIZE),
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+};
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static struct platform_device ltq_etop = {
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.name = "ltq_etop",
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- .resource = <q_etop_resources,
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+ .resource = ltq_etop_resources,
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.num_resources = 1,
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};
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void __init
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ltq_register_etop(struct ltq_eth_data *eth)
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{
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+ /* only register the gphy on socs that have one */
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+ if (ltq_is_ar9() | ltq_is_vr9())
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+ ltq_etop.num_resources = 2;
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if (eth) {
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ltq_etop.dev.platform_data = eth;
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platform_device_register(<q_etop);
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--- a/drivers/net/ethernet/lantiq_etop.c
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+++ b/drivers/net/ethernet/lantiq_etop.c
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@@ -71,10 +71,43 @@
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#define ETOP_MII_REVERSE 0xe
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#define ETOP_PLEN_UNDER 0x40
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#define ETOP_CGEN 0x800
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+#define ETOP_CFG_MII0 0x01
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-/* use 2 static channels for TX/RX */
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+#define LTQ_GBIT_MDIO_CTL 0xCC
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+#define LTQ_GBIT_MDIO_DATA 0xd0
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+#define LTQ_GBIT_GCTL0 0x68
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+#define LTQ_GBIT_PMAC_HD_CTL 0x8c
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+#define LTQ_GBIT_P0_CTL 0x4
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+#define LTQ_GBIT_PMAC_RX_IPG 0xa8
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+
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+#define PMAC_HD_CTL_AS (1 << 19)
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+#define PMAC_HD_CTL_RXSH (1 << 22)
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+
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+/* Switch Enable (0=disable, 1=enable) */
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+#define GCTL0_SE 0x80000000
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+/* Disable MDIO auto polling (0=disable, 1=enable) */
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+#define PX_CTL_DMDIO 0x00400000
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+
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+/* register information for the gbit's MDIO bus */
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+#define MDIO_XR9_REQUEST 0x00008000
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+#define MDIO_XR9_READ 0x00000800
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+#define MDIO_XR9_WRITE 0x00000400
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+#define MDIO_XR9_REG_MASK 0x1f
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+#define MDIO_XR9_ADDR_MASK 0x1f
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+#define MDIO_XR9_RD_MASK 0xffff
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+#define MDIO_XR9_REG_OFFSET 0
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+#define MDIO_XR9_ADDR_OFFSET 5
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+#define MDIO_XR9_WR_OFFSET 16
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+
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+/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
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+#define ltq_has_gbit() (ltq_is_ar9() || ltq_is_vr9())
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+
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+/* use 2 static channels for TX/RX
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+ depending on the SoC we need to use different DMA channels for ethernet */
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#define LTQ_ETOP_TX_CHANNEL 1
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-#define LTQ_ETOP_RX_CHANNEL 6
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+#define LTQ_ETOP_RX_CHANNEL ((ltq_is_ase()) ? (5) : \
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+ ((ltq_has_gbit()) ? (0) : (6)))
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+
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#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
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#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
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@@ -83,9 +116,15 @@
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#define ltq_etop_w32_mask(x, y, z) \
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ltq_w32_mask(x, y, ltq_etop_membase + (z))
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+#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x))
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+#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y))
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+#define ltq_gbit_w32_mask(x, y, z) \
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+ ltq_w32_mask(x, y, ltq_gbit_membase + (z))
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+
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#define DRV_VERSION "1.0"
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static void __iomem *ltq_etop_membase;
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+static void __iomem *ltq_gbit_membase;
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struct ltq_etop_chan {
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int idx;
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@@ -110,6 +149,9 @@ struct ltq_etop_priv {
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spinlock_t lock;
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};
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+static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
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+ int phy_reg, u16 phy_data);
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+
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static int
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ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
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{
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@@ -211,7 +253,7 @@ static irqreturn_t
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ltq_etop_dma_irq(int irq, void *_priv)
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{
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struct ltq_etop_priv *priv = _priv;
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- int ch = irq - LTQ_DMA_CH0_INT;
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+ int ch = irq - LTQ_DMA_ETOP;
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napi_schedule(&priv->ch[ch].napi);
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return IRQ_HANDLED;
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@@ -244,15 +286,43 @@ ltq_etop_hw_exit(struct net_device *dev)
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ltq_etop_free_channel(dev, &priv->ch[i]);
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}
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+static void
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+ltq_etop_gbit_init(void)
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+{
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+ ltq_pmu_enable(PMU_SWITCH);
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+
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+ ltq_gpio_request(42, 2, 1, "MDIO");
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+ ltq_gpio_request(43, 2, 1, "MDC");
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+
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+ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
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+ /** Disable MDIO auto polling mode */
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+ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
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+ /* set 1522 packet size */
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+ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
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+ /* disable pmac & dmac headers */
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+ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
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+ LTQ_GBIT_PMAC_HD_CTL);
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+ /* Due to traffic halt when burst length 8,
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+ replace default IPG value with 0x3B */
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+ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
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+}
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+
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static int
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ltq_etop_hw_init(struct net_device *dev)
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{
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struct ltq_etop_priv *priv = netdev_priv(dev);
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+ unsigned int mii_mode = priv->pldata->mii_mode;
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int i;
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ltq_pmu_enable(PMU_PPE);
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- switch (priv->pldata->mii_mode) {
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+ if (ltq_has_gbit()) {
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+ ltq_etop_gbit_init();
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+ /* force the etops link to the gbit to MII */
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+ mii_mode = PHY_INTERFACE_MODE_MII;
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+ }
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+
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+ switch (mii_mode) {
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case PHY_INTERFACE_MODE_RMII:
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ltq_etop_w32_mask(ETOP_MII_MASK,
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ETOP_MII_REVERSE, LTQ_ETOP_CFG);
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@@ -264,6 +334,18 @@ ltq_etop_hw_init(struct net_device *dev)
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break;
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default:
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+ if (ltq_is_ase()) {
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+ ltq_pmu_enable(PMU_EPHY);
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+ /* disable external MII */
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+ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
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+ /* enable clock for internal PHY */
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+ ltq_cgu_enable(CGU_EPHY);
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+ /* we need to write this magic to the internal phy to
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+ make it work */
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+ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
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+ pr_info("Selected EPHY mode\n");
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+ break;
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+ }
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netdev_err(dev, "unknown mii mode %d\n",
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priv->pldata->mii_mode);
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return -ENOTSUPP;
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@@ -275,7 +357,7 @@ ltq_etop_hw_init(struct net_device *dev)
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ltq_dma_init_port(DMA_PORT_ETOP);
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for (i = 0; i < MAX_DMA_CHAN; i++) {
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- int irq = LTQ_DMA_CH0_INT + i;
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+ int irq = LTQ_DMA_ETOP + i;
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struct ltq_etop_chan *ch = &priv->ch[i];
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ch->idx = ch->dma.nr = i;
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@@ -339,6 +421,39 @@ static const struct ethtool_ops ltq_etop
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};
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static int
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+ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
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+ int phy_reg, u16 phy_data)
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+{
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+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
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+ (phy_data << MDIO_XR9_WR_OFFSET) |
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+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
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+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
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+
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+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
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+ ;
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+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
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+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
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+ ;
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+ return 0;
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+}
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+
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+static int
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+ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
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+{
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+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
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+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
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+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
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+
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+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
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+ ;
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+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
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+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
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+ ;
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+ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
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+ return val;
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+}
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+
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+static int
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ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
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{
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u32 val = MDIO_REQUEST |
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@@ -379,14 +494,11 @@ ltq_etop_mdio_probe(struct net_device *d
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{
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struct ltq_etop_priv *priv = netdev_priv(dev);
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struct phy_device *phydev = NULL;
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- int phy_addr;
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- for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
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- if (priv->mii_bus->phy_map[phy_addr]) {
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- phydev = priv->mii_bus->phy_map[phy_addr];
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- break;
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- }
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- }
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+ if (ltq_is_ase())
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+ phydev = priv->mii_bus->phy_map[8];
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+ else
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+ phydev = priv->mii_bus->phy_map[0];
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if (!phydev) {
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netdev_err(dev, "no PHY found\n");
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@@ -408,6 +520,9 @@ ltq_etop_mdio_probe(struct net_device *d
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| SUPPORTED_Autoneg
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| SUPPORTED_MII
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| SUPPORTED_TP);
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+ if (ltq_has_gbit())
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+ phydev->supported &= SUPPORTED_1000baseT_Half
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+ | SUPPORTED_1000baseT_Full;
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phydev->advertising = phydev->supported;
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priv->phydev = phydev;
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@@ -433,8 +548,13 @@ ltq_etop_mdio_init(struct net_device *de
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}
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priv->mii_bus->priv = dev;
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- priv->mii_bus->read = ltq_etop_mdio_rd;
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- priv->mii_bus->write = ltq_etop_mdio_wr;
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+ if (ltq_has_gbit()) {
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+ priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
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+ priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
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+ } else {
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+ priv->mii_bus->read = ltq_etop_mdio_rd;
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+ priv->mii_bus->write = ltq_etop_mdio_wr;
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+ }
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priv->mii_bus->name = "ltq_mii";
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snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
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priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
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@@ -524,9 +644,9 @@ ltq_etop_tx(struct sk_buff *skb, struct
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struct ltq_etop_priv *priv = netdev_priv(dev);
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struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
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struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
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- int len;
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unsigned long flags;
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u32 byte_offset;
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+ int len;
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len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
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@@ -700,7 +820,7 @@ ltq_etop_probe(struct platform_device *p
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{
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struct net_device *dev;
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struct ltq_etop_priv *priv;
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- struct resource *res;
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+ struct resource *res, *gbit_res;
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int err;
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int i;
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@@ -728,6 +848,23 @@ ltq_etop_probe(struct platform_device *p
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goto err_out;
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}
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+ if (ltq_has_gbit()) {
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+ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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+ if (!gbit_res) {
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+ dev_err(&pdev->dev, "failed to get gbit resource\n");
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+ err = -ENOENT;
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+ goto err_out;
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+ }
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+ ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
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+ gbit_res->start, resource_size(gbit_res));
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+ if (!ltq_gbit_membase) {
|
|
+ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
|
|
+ pdev->id);
|
|
+ err = -ENOMEM;
|
|
+ goto err_out;
|
|
+ }
|
|
+ }
|
|
+
|
|
dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
|
|
strcpy(dev->name, "eth%d");
|
|
dev->netdev_ops = <q_eth_netdev_ops;
|