mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-21 20:19:00 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16048 3c298f89-4303-0410-b956-a3cf2f4a3e73
803 lines
19 KiB
Diff
803 lines
19 KiB
Diff
--- /dev/null
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+++ b/arch/arm/plat-s3c/include/plat/pwm.h
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@@ -0,0 +1,45 @@
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+#ifndef __S3C2410_PWM_H
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+#define __S3C2410_PWM_H
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+
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+#include <linux/err.h>
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+#include <linux/platform_device.h>
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+#include <linux/clk.h>
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+
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+#include <mach/io.h>
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+#include <mach/hardware.h>
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+#include <asm/mach-types.h>
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+#include <plat/regs-timer.h>
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+
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+enum pwm_timer {
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+ PWM0,
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+ PWM1,
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+ PWM2,
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+ PWM3,
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+ PWM4
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+};
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+
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+struct s3c2410_pwm {
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+ enum pwm_timer timerid;
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+ struct clk *pclk;
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+ unsigned long pclk_rate;
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+ unsigned long prescaler;
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+ unsigned long divider;
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+ unsigned long counter;
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+ unsigned long comparer;
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+};
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+
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+struct s3c24xx_pwm_platform_data{
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+ /* callback to attach platform children (to enforce suspend / resume
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+ * ordering */
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+ void (*attach_child_devices)(struct device *parent_device);
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+};
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+
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+int s3c2410_pwm_init(struct s3c2410_pwm *s3c2410_pwm);
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+int s3c2410_pwm_enable(struct s3c2410_pwm *s3c2410_pwm);
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+int s3c2410_pwm_disable(struct s3c2410_pwm *s3c2410_pwm);
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+int s3c2410_pwm_start(struct s3c2410_pwm *s3c2410_pwm);
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+int s3c2410_pwm_stop(struct s3c2410_pwm *s3c2410_pwm);
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+int s3c2410_pwm_duty_cycle(int reg_value, struct s3c2410_pwm *s3c2410_pwm);
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+int s3c2410_pwm_dumpregs(void);
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+
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+#endif /* __S3C2410_PWM_H */
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--- a/arch/arm/plat-s3c/Kconfig
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+++ b/arch/arm/plat-s3c/Kconfig
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@@ -157,6 +157,11 @@ config S3C_DMA
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help
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Internal configuration for S3C DMA core
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+config S3C_PWM
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+ bool
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+ help
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+ PWM timer code for the S3C2410, and similar processors
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+
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# device definitions to compile in
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config S3C_DEV_HSMMC
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--- a/arch/arm/plat-s3c/Makefile
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+++ b/arch/arm/plat-s3c/Makefile
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@@ -35,5 +35,6 @@ obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmm
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obj-y += dev-i2c0.o
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obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o
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obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o
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+obj-$(CONFIG_S3C_PWM) += pwm.o
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obj-$(CONFIG_S3C_DMA) += dma.o
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--- /dev/null
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+++ b/arch/arm/plat-s3c/pwm.c
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@@ -0,0 +1,288 @@
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+/*
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+ * arch/arm/plat-s3c/pwm.c
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+ *
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+ * Copyright (c) by Javi Roman <javiroman@kernel-labs.org>
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+ * for the Openmoko Project.
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+ *
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+ * S3C2410A SoC PWM support
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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+ *
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/init.h>
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+#include <linux/clk.h>
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+#include <linux/device.h>
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+#include <mach/hardware.h>
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+#include <plat/regs-timer.h>
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+#include <plat/pwm.h>
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+#include <asm/io.h>
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+
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+#ifdef CONFIG_PM
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+ static unsigned long standby_reg_tcon;
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+ static unsigned long standby_reg_tcfg0;
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+ static unsigned long standby_reg_tcfg1;
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+#endif
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+
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+int s3c2410_pwm_disable(struct s3c2410_pwm *pwm)
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+{
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+ unsigned long tcon;
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+
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+ /* stop timer */
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+ tcon = __raw_readl(S3C2410_TCON);
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+ tcon &= 0xffffff00;
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+ __raw_writel(tcon, S3C2410_TCON);
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+
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+ clk_disable(pwm->pclk);
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+ clk_put(pwm->pclk);
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+
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(s3c2410_pwm_disable);
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+
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+int s3c2410_pwm_init(struct s3c2410_pwm *pwm)
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+{
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+ pwm->pclk = clk_get(NULL, "timers");
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+ if (IS_ERR(pwm->pclk))
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+ return PTR_ERR(pwm->pclk);
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+
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+ clk_enable(pwm->pclk);
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+ pwm->pclk_rate = clk_get_rate(pwm->pclk);
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(s3c2410_pwm_init);
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+
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+int s3c2410_pwm_enable(struct s3c2410_pwm *pwm)
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+{
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+ unsigned long tcfg0, tcfg1, tcnt, tcmp;
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+
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+ /* control registers bits */
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+ tcfg1 = __raw_readl(S3C2410_TCFG1);
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+ tcfg0 = __raw_readl(S3C2410_TCFG0);
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+
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+ /* divider & scaler slection */
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+ switch (pwm->timerid) {
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+ case PWM0:
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+ tcfg1 &= ~S3C2410_TCFG1_MUX0_MASK;
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+ tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
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+ break;
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+ case PWM1:
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+ tcfg1 &= ~S3C2410_TCFG1_MUX1_MASK;
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+ tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
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+ break;
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+ case PWM2:
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+ tcfg1 &= ~S3C2410_TCFG1_MUX2_MASK;
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+ tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
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+ break;
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+ case PWM3:
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+ tcfg1 &= ~S3C2410_TCFG1_MUX3_MASK;
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+ tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
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+ break;
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+ case PWM4:
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+ /* timer four is not capable of doing PWM */
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+ break;
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+ default:
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+ clk_disable(pwm->pclk);
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+ clk_put(pwm->pclk);
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+ return -1;
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+ }
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+
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+ /* divider & scaler values */
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+ tcfg1 |= pwm->divider;
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+ __raw_writel(tcfg1, S3C2410_TCFG1);
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+
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+ switch (pwm->timerid) {
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+ case PWM0:
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+ case PWM1:
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+ tcfg0 |= pwm->prescaler;
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+ __raw_writel(tcfg0, S3C2410_TCFG0);
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+ break;
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+ default:
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+ if ((tcfg0 | pwm->prescaler) != tcfg0) {
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+ printk(KERN_WARNING "not changing prescaler of PWM %u,"
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+ " since it's shared with timer4 (clock tick)\n",
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+ pwm->timerid);
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+ }
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+ break;
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+ }
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+
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+ /* timer count and compare buffer initial values */
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+ tcnt = pwm->counter;
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+ tcmp = pwm->comparer;
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+
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+ __raw_writel(tcnt, S3C2410_TCNTB(pwm->timerid));
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+ __raw_writel(tcmp, S3C2410_TCMPB(pwm->timerid));
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+
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+ /* ensure timer is stopped */
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+ s3c2410_pwm_stop(pwm);
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+
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(s3c2410_pwm_enable);
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+
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+int s3c2410_pwm_start(struct s3c2410_pwm *pwm)
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+{
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+ unsigned long tcon;
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+
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+ tcon = __raw_readl(S3C2410_TCON);
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+
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+ switch (pwm->timerid) {
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+ case PWM0:
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+ tcon |= S3C2410_TCON_T0START;
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+ tcon &= ~S3C2410_TCON_T0MANUALUPD;
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+ break;
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+ case PWM1:
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+ tcon |= S3C2410_TCON_T1START;
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+ tcon &= ~S3C2410_TCON_T1MANUALUPD;
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+ break;
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+ case PWM2:
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+ tcon |= S3C2410_TCON_T2START;
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+ tcon &= ~S3C2410_TCON_T2MANUALUPD;
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+ break;
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+ case PWM3:
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+ tcon |= S3C2410_TCON_T3START;
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+ tcon &= ~S3C2410_TCON_T3MANUALUPD;
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+ break;
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+ case PWM4:
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+ /* timer four is not capable of doing PWM */
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+ default:
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+ return -ENODEV;
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+ }
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+
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+ __raw_writel(tcon, S3C2410_TCON);
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+
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(s3c2410_pwm_start);
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+
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+int s3c2410_pwm_stop(struct s3c2410_pwm *pwm)
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+{
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+ unsigned long tcon;
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+
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+ tcon = __raw_readl(S3C2410_TCON);
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+
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+ switch (pwm->timerid) {
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+ case PWM0:
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+ tcon &= ~0x00000000;
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+ tcon |= S3C2410_TCON_T0RELOAD;
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+ tcon |= S3C2410_TCON_T0MANUALUPD;
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+ break;
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+ case PWM1:
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+ tcon &= ~0x00000080;
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+ tcon |= S3C2410_TCON_T1RELOAD;
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+ tcon |= S3C2410_TCON_T1MANUALUPD;
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+ break;
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+ case PWM2:
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+ tcon &= ~0x00000800;
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+ tcon |= S3C2410_TCON_T2RELOAD;
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+ tcon |= S3C2410_TCON_T2MANUALUPD;
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+ break;
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+ case PWM3:
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+ tcon &= ~0x00008000;
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+ tcon |= S3C2410_TCON_T3RELOAD;
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+ tcon |= S3C2410_TCON_T3MANUALUPD;
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+ break;
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+ case PWM4:
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+ /* timer four is not capable of doing PWM */
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+ default:
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+ return -ENODEV;
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+ }
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+
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+ __raw_writel(tcon, S3C2410_TCON);
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+
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(s3c2410_pwm_stop);
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+
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+int s3c2410_pwm_duty_cycle(int reg_value, struct s3c2410_pwm *pwm)
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+{
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+ __raw_writel(reg_value, S3C2410_TCMPB(pwm->timerid));
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+
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(s3c2410_pwm_duty_cycle);
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+
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+int s3c2410_pwm_dumpregs(void)
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+{
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+ printk(KERN_INFO "TCON: %08lx, TCFG0: %08lx, TCFG1: %08lx\n",
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+ (unsigned long) __raw_readl(S3C2410_TCON),
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+ (unsigned long) __raw_readl(S3C2410_TCFG0),
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+ (unsigned long) __raw_readl(S3C2410_TCFG1));
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+
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(s3c2410_pwm_dumpregs);
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+
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+static int __init s3c24xx_pwm_probe(struct platform_device *pdev)
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+{
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+ struct s3c24xx_pwm_platform_data *pdata = pdev->dev.platform_data;
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+
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+ dev_info(&pdev->dev, "s3c24xx_pwm is registered \n");
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+
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+ /* if platform was interested, give him a chance to register
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+ * platform devices that switch power with us as the parent
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+ * at registration time -- ensures suspend / resume ordering
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+ */
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+ if (pdata)
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+ if (pdata->attach_child_devices)
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+ (pdata->attach_child_devices)(&pdev->dev);
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+
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+ return 0;
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+}
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+
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+#ifdef CONFIG_PM
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+static int s3c24xx_pwm_suspend(struct platform_device *pdev, pm_message_t state)
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+{
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+ /* PWM config should be kept in suspending */
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+ standby_reg_tcon = __raw_readl(S3C2410_TCON);
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+ standby_reg_tcfg0 = __raw_readl(S3C2410_TCFG0);
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+ standby_reg_tcfg1 = __raw_readl(S3C2410_TCFG1);
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+
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+ return 0;
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+}
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+
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+static int s3c24xx_pwm_resume(struct platform_device *pdev)
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+{
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+ __raw_writel(standby_reg_tcon, S3C2410_TCON);
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+ __raw_writel(standby_reg_tcfg0, S3C2410_TCFG0);
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+ __raw_writel(standby_reg_tcfg1, S3C2410_TCFG1);
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+
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+ return 0;
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+}
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+#else
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+#define s3c24xx_pwm_suspend NULL
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+#define s3c24xx_pwm_resume NULL
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+#endif
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+
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+static struct platform_driver s3c24xx_pwm_driver = {
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+ .driver = {
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+ .name = "s3c24xx_pwm",
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+ .owner = THIS_MODULE,
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+ },
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+ .probe = s3c24xx_pwm_probe,
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+ .suspend = s3c24xx_pwm_suspend,
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+ .resume = s3c24xx_pwm_resume,
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+};
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+
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+static int __init s3c24xx_pwm_init(void)
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+{
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+ return platform_driver_register(&s3c24xx_pwm_driver);
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+}
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+
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+static void __exit s3c24xx_pwm_exit(void)
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+{
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+}
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+
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+MODULE_AUTHOR("Javi Roman <javiroman@kernel-labs.org>");
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+MODULE_LICENSE("GPL");
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+
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+module_init(s3c24xx_pwm_init);
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+module_exit(s3c24xx_pwm_exit);
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--- /dev/null
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+++ b/arch/arm/plat-s3c24xx/pwm-clock.c
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@@ -0,0 +1,437 @@
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+/* linux/arch/arm/plat-s3c24xx/pwm-clock.c
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+ *
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+ * Copyright (c) 2007 Simtec Electronics
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+ * Copyright (c) 2007, 2008 Ben Dooks
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+ * Ben Dooks <ben-linux@fluff.org>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License.
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+*/
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+
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+#include <linux/init.h>
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+#include <linux/module.h>
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+#include <linux/kernel.h>
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+#include <linux/list.h>
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+#include <linux/errno.h>
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+#include <linux/clk.h>
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+#include <linux/err.h>
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+#include <linux/io.h>
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+
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+#include <mach/hardware.h>
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+#include <asm/irq.h>
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+
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+#include <mach/regs-clock.h>
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+#include <mach/regs-gpio.h>
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+
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+#include <asm/plat-s3c24xx/clock.h>
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+#include <asm/plat-s3c24xx/cpu.h>
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+
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+#include <asm/plat-s3c/regs-timer.h>
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+
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+/* Each of the timers 0 through 5 go through the following
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+ * clock tree, with the inputs depending on the timers.
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+ *
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+ * pclk ---- [ prescaler 0 ] -+---> timer 0
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+ * +---> timer 1
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+ *
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+ * pclk ---- [ prescaler 1 ] -+---> timer 2
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+ * +---> timer 3
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+ * \---> timer 4
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+ *
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+ * Which are fed into the timers as so:
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+ *
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+ * prescaled 0 ---- [ div 2,4,8,16 ] ---\
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+ * [mux] -> timer 0
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+ * tclk 0 ------------------------------/
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+ *
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+ * prescaled 0 ---- [ div 2,4,8,16 ] ---\
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+ * [mux] -> timer 1
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+ * tclk 0 ------------------------------/
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+ *
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+ *
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+ * prescaled 1 ---- [ div 2,4,8,16 ] ---\
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+ * [mux] -> timer 2
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+ * tclk 1 ------------------------------/
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+ *
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+ * prescaled 1 ---- [ div 2,4,8,16 ] ---\
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+ * [mux] -> timer 3
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+ * tclk 1 ------------------------------/
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+ *
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+ * prescaled 1 ---- [ div 2,4,8, 16 ] --\
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+ * [mux] -> timer 4
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+ * tclk 1 ------------------------------/
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+ *
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+ * Since the mux and the divider are tied together in the
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+ * same register space, it is impossible to set the parent
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+ * and the rate at the same time. To avoid this, we add an
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+ * intermediate 'prescaled-and-divided' clock to select
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+ * as the parent for the timer input clock called tdiv.
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+ *
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+ * prescaled clk --> pwm-tdiv ---\
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+ * [ mux ] --> timer X
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+ * tclk -------------------------/
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+*/
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+
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+static unsigned long clk_pwm_scaler_getrate(struct clk *clk)
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+{
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+ unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0);
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+
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+ if (clk->id == 1) {
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+ tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK;
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|
+ tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT;
|
|
+ } else {
|
|
+ tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK;
|
|
+ }
|
|
+
|
|
+ return clk_get_rate(clk->parent) / (tcfg0 + 1);
|
|
+}
|
|
+
|
|
+/* TODO - add set rate calls. */
|
|
+
|
|
+static struct clk clk_timer_scaler[] = {
|
|
+ [0] = {
|
|
+ .name = "pwm-scaler0",
|
|
+ .id = -1,
|
|
+ .get_rate = clk_pwm_scaler_getrate,
|
|
+ },
|
|
+ [1] = {
|
|
+ .name = "pwm-scaler1",
|
|
+ .id = -1,
|
|
+ .get_rate = clk_pwm_scaler_getrate,
|
|
+ },
|
|
+};
|
|
+
|
|
+static struct clk clk_timer_tclk[] = {
|
|
+ [0] = {
|
|
+ .name = "pwm-tclk0",
|
|
+ .id = -1,
|
|
+ },
|
|
+ [1] = {
|
|
+ .name = "pwm-tclk1",
|
|
+ .id = -1,
|
|
+ },
|
|
+};
|
|
+
|
|
+struct pwm_tdiv_clk {
|
|
+ struct clk clk;
|
|
+ unsigned int divisor;
|
|
+};
|
|
+
|
|
+static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk)
|
|
+{
|
|
+ return container_of(clk, struct pwm_tdiv_clk, clk);
|
|
+}
|
|
+
|
|
+static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
|
|
+{
|
|
+ return 1 << (1 + tcfg1);
|
|
+}
|
|
+
|
|
+static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
|
|
+{
|
|
+ unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
|
|
+ unsigned int divisor;
|
|
+
|
|
+ tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
|
|
+ tcfg1 &= S3C2410_TCFG1_MUX_MASK;
|
|
+
|
|
+ if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)
|
|
+ divisor = to_tdiv(clk)->divisor;
|
|
+ else
|
|
+ divisor = tcfg_to_divisor(tcfg1);
|
|
+
|
|
+ return clk_get_rate(clk->parent) / divisor;
|
|
+}
|
|
+
|
|
+static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
|
|
+ unsigned long rate)
|
|
+{
|
|
+ unsigned long parent_rate;
|
|
+ unsigned long divisor;
|
|
+
|
|
+ parent_rate = clk_get_rate(clk->parent);
|
|
+ divisor = parent_rate / rate;
|
|
+
|
|
+ if (divisor <= 2)
|
|
+ divisor = 2;
|
|
+ else if (divisor <= 4)
|
|
+ divisor = 4;
|
|
+ else if (divisor <= 8)
|
|
+ divisor = 8;
|
|
+ else
|
|
+ divisor = 16;
|
|
+
|
|
+ return parent_rate / divisor;
|
|
+}
|
|
+
|
|
+static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
|
|
+{
|
|
+ unsigned long bits;
|
|
+
|
|
+ switch (divclk->divisor) {
|
|
+ case 2:
|
|
+ bits = S3C2410_TCFG1_MUX_DIV2;
|
|
+ break;
|
|
+ case 4:
|
|
+ bits = S3C2410_TCFG1_MUX_DIV4;
|
|
+ break;
|
|
+ case 8:
|
|
+ bits = S3C2410_TCFG1_MUX_DIV8;
|
|
+ break;
|
|
+ case 16:
|
|
+ default:
|
|
+ bits = S3C2410_TCFG1_MUX_DIV16;
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ return bits;
|
|
+}
|
|
+
|
|
+static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
|
|
+{
|
|
+ unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
|
|
+ unsigned long bits = clk_pwm_tdiv_bits(divclk);
|
|
+ unsigned long flags;
|
|
+ unsigned long shift = S3C2410_TCFG1_SHIFT(divclk->clk.id);
|
|
+
|
|
+ local_irq_save(flags);
|
|
+
|
|
+ tcfg1 = __raw_readl(S3C2410_TCFG1);
|
|
+ tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
|
|
+ tcfg1 |= bits << shift;
|
|
+ __raw_writel(tcfg1, S3C2410_TCFG1);
|
|
+
|
|
+ local_irq_restore(flags);
|
|
+}
|
|
+
|
|
+static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
|
|
+{
|
|
+ struct pwm_tdiv_clk *divclk = to_tdiv(clk);
|
|
+ unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
|
|
+ unsigned long parent_rate = clk_get_rate(clk->parent);
|
|
+ unsigned long divisor;
|
|
+
|
|
+ tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
|
|
+ tcfg1 &= S3C2410_TCFG1_MUX_MASK;
|
|
+
|
|
+ rate = clk_round_rate(clk, rate);
|
|
+ divisor = parent_rate / rate;
|
|
+
|
|
+ if (divisor > 16)
|
|
+ return -EINVAL;
|
|
+
|
|
+ divclk->divisor = divisor;
|
|
+
|
|
+ /* Update the current MUX settings if we are currently
|
|
+ * selected as the clock source for this clock. */
|
|
+
|
|
+ if (tcfg1 != S3C2410_TCFG1_MUX_TCLK)
|
|
+ clk_pwm_tdiv_update(divclk);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static struct pwm_tdiv_clk clk_timer_tdiv[] = {
|
|
+ [0] = {
|
|
+ .clk = {
|
|
+ .name = "pwm-tdiv",
|
|
+ .parent = &clk_timer_scaler[0],
|
|
+ .get_rate = clk_pwm_tdiv_get_rate,
|
|
+ .set_rate = clk_pwm_tdiv_set_rate,
|
|
+ .round_rate = clk_pwm_tdiv_round_rate,
|
|
+ },
|
|
+ },
|
|
+ [1] = {
|
|
+ .clk = {
|
|
+ .name = "pwm-tdiv",
|
|
+ .parent = &clk_timer_scaler[0],
|
|
+ .get_rate = clk_pwm_tdiv_get_rate,
|
|
+ .set_rate = clk_pwm_tdiv_set_rate,
|
|
+ .round_rate = clk_pwm_tdiv_round_rate,
|
|
+ }
|
|
+ },
|
|
+ [2] = {
|
|
+ .clk = {
|
|
+ .name = "pwm-tdiv",
|
|
+ .parent = &clk_timer_scaler[1],
|
|
+ .get_rate = clk_pwm_tdiv_get_rate,
|
|
+ .set_rate = clk_pwm_tdiv_set_rate,
|
|
+ .round_rate = clk_pwm_tdiv_round_rate,
|
|
+ },
|
|
+ },
|
|
+ [3] = {
|
|
+ .clk = {
|
|
+ .name = "pwm-tdiv",
|
|
+ .parent = &clk_timer_scaler[1],
|
|
+ .get_rate = clk_pwm_tdiv_get_rate,
|
|
+ .set_rate = clk_pwm_tdiv_set_rate,
|
|
+ .round_rate = clk_pwm_tdiv_round_rate,
|
|
+ },
|
|
+ },
|
|
+ [4] = {
|
|
+ .clk = {
|
|
+ .name = "pwm-tdiv",
|
|
+ .parent = &clk_timer_scaler[1],
|
|
+ .get_rate = clk_pwm_tdiv_get_rate,
|
|
+ .set_rate = clk_pwm_tdiv_set_rate,
|
|
+ .round_rate = clk_pwm_tdiv_round_rate,
|
|
+ },
|
|
+ },
|
|
+};
|
|
+
|
|
+static int __init clk_pwm_tdiv_register(unsigned int id)
|
|
+{
|
|
+ struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id];
|
|
+ unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
|
|
+
|
|
+ tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
|
|
+ tcfg1 &= S3C2410_TCFG1_MUX_MASK;
|
|
+
|
|
+ divclk->clk.id = id;
|
|
+ divclk->divisor = tcfg_to_divisor(tcfg1);
|
|
+
|
|
+ return s3c24xx_register_clock(&divclk->clk);
|
|
+}
|
|
+
|
|
+static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id)
|
|
+{
|
|
+ return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0];
|
|
+}
|
|
+
|
|
+static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id)
|
|
+{
|
|
+ return &clk_timer_tdiv[id].clk;
|
|
+}
|
|
+
|
|
+static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
|
|
+{
|
|
+ unsigned int id = clk->id;
|
|
+ unsigned long tcfg1;
|
|
+ unsigned long flags;
|
|
+ unsigned long bits;
|
|
+ unsigned long shift = S3C2410_TCFG1_SHIFT(id);
|
|
+
|
|
+ if (parent == s3c24xx_pwmclk_tclk(id))
|
|
+ bits = S3C2410_TCFG1_MUX_TCLK << shift;
|
|
+ else if (parent == s3c24xx_pwmclk_tdiv(id))
|
|
+ bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
|
|
+ else
|
|
+ return -EINVAL;
|
|
+
|
|
+ clk->parent = parent;
|
|
+
|
|
+ local_irq_save(flags);
|
|
+
|
|
+ tcfg1 = __raw_readl(S3C2410_TCFG1);
|
|
+ tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
|
|
+ __raw_writel(tcfg1 | bits, S3C2410_TCFG1);
|
|
+
|
|
+ local_irq_restore(flags);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static struct clk clk_tin[] = {
|
|
+ [0] = {
|
|
+ .name = "pwm-tin",
|
|
+ .id = 0,
|
|
+ .set_parent = clk_pwm_tin_set_parent,
|
|
+ },
|
|
+ [1] = {
|
|
+ .name = "pwm-tin",
|
|
+ .id = 1,
|
|
+ .set_parent = clk_pwm_tin_set_parent,
|
|
+ },
|
|
+ [2] = {
|
|
+ .name = "pwm-tin",
|
|
+ .id = 2,
|
|
+ .set_parent = clk_pwm_tin_set_parent,
|
|
+ },
|
|
+ [3] = {
|
|
+ .name = "pwm-tin",
|
|
+ .id = 3,
|
|
+ .set_parent = clk_pwm_tin_set_parent,
|
|
+ },
|
|
+ [4] = {
|
|
+ .name = "pwm-tin",
|
|
+ .id = 4,
|
|
+ .set_parent = clk_pwm_tin_set_parent,
|
|
+ },
|
|
+};
|
|
+
|
|
+static __init int clk_pwm_tin_register(struct clk *pwm)
|
|
+{
|
|
+ unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
|
|
+ unsigned int id = pwm->id;
|
|
+
|
|
+ struct clk *parent;
|
|
+ int ret;
|
|
+
|
|
+ ret = s3c24xx_register_clock(pwm);
|
|
+ if (ret < 0)
|
|
+ return ret;
|
|
+
|
|
+ tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
|
|
+ tcfg1 &= S3C2410_TCFG1_MUX_MASK;
|
|
+
|
|
+ if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)
|
|
+ parent = s3c24xx_pwmclk_tclk(id);
|
|
+ else
|
|
+ parent = s3c24xx_pwmclk_tdiv(id);
|
|
+
|
|
+ return clk_set_parent(pwm, parent);
|
|
+}
|
|
+
|
|
+static __init int s3c24xx_pwmclk_init(void)
|
|
+{
|
|
+ struct clk *clk_timers;
|
|
+ unsigned int clk;
|
|
+ int ret;
|
|
+
|
|
+ clk_timers = clk_get(NULL, "timers");
|
|
+ if (IS_ERR(clk_timers)) {
|
|
+ printk(KERN_ERR "%s: no parent clock\n", __func__);
|
|
+ return -EINVAL;
|
|
+ }
|
|
+
|
|
+ for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) {
|
|
+ clk_timer_scaler[clk].parent = clk_timers;
|
|
+ ret = s3c24xx_register_clock(&clk_timer_scaler[clk]);
|
|
+ if (ret < 0) {
|
|
+ printk(KERN_ERR "error adding pwm scaler%d clock\n", clk);
|
|
+ goto err;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ for (clk = 0; clk < ARRAY_SIZE(clk_timer_tclk); clk++) {
|
|
+ ret = s3c24xx_register_clock(&clk_timer_tclk[clk]);
|
|
+ if (ret < 0) {
|
|
+ printk(KERN_ERR "error adding pww tclk%d\n", clk);
|
|
+ goto err;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) {
|
|
+ ret = clk_pwm_tdiv_register(clk);
|
|
+ if (ret < 0) {
|
|
+ printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
|
|
+ goto err;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) {
|
|
+ ret = clk_pwm_tin_register(&clk_tin[clk]);
|
|
+ if (ret < 0) {
|
|
+ printk(KERN_ERR "error adding pwm%d tin clock\n", clk);
|
|
+ goto err;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+
|
|
+ err:
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+arch_initcall(s3c24xx_pwmclk_init);
|