mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-21 01:52:25 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@22323 3c298f89-4303-0410-b956-a3cf2f4a3e73
1072 lines
29 KiB
Diff
1072 lines
29 KiB
Diff
--- a/drivers/spi/Kconfig
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+++ b/drivers/spi/Kconfig
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@@ -236,6 +236,39 @@ config SPI_XILINX
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See the "OPB Serial Peripheral Interface (SPI) (v1.00e)"
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Product Specification document (DS464) for hardware details.
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+config SPI_CNS3XXX
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+ tristate "CNS3XXX SPI controller"
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+ depends on ARCH_CNS3XXX && SPI_MASTER && EXPERIMENTAL
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+ select SPI_BITBANG
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+ help
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+ This enables using the CNS3XXX SPI controller in master
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+ mode.
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+
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+config SPI_CNS3XXX_DEBUG
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+ boolean "Debug support for CNS3XXX SPI drivers"
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+ depends on SPI_CNS3XXX
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+ help
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+ Say "yes" to enable debug messaging
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+
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+config SPI_CNS3XXX_2IOREAD
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+ bool "CNS3XXX SPI 2 IO Read Mode"
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+ depends on SPI_CNS3XXX
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+ help
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+ This enables 2 IO Read Mode
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+
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+config SPI_CNS3XXX_USEDMA
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+ bool "CNS3XXX SPI DMA Mode"
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+ depends on SPI_CNS3XXX
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+ select CNS3XXX_DMAC
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+ help
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+ This enables DMA Mode
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+
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+config SPI_CNS3XXX_USEDMA_DEBUG
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+ boolean "Debug support for CNS3XXX SPI DMA drivers"
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+ depends on SPI_CNS3XXX_USEDMA
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+ help
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+ Say "yes" to enable debug messaging
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+
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#
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# Add new SPI master controllers in alphabetical order above this line
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#
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--- a/drivers/spi/Makefile
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+++ b/drivers/spi/Makefile
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@@ -32,6 +32,7 @@ obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24x
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obj-$(CONFIG_SPI_TXX9) += spi_txx9.o
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obj-$(CONFIG_SPI_XILINX) += xilinx_spi.o
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obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.o
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+obj-$(CONFIG_SPI_CNS3XXX) += spi_cns3xxx.o
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# ... add above this line ...
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# SPI protocol drivers (device/link on bus)
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--- a/drivers/spi/spi_bitbang.c
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+++ b/drivers/spi/spi_bitbang.c
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@@ -334,6 +334,14 @@ static void bitbang_work(struct work_str
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*/
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if (!m->is_dma_mapped)
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t->rx_dma = t->tx_dma = 0;
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+
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+#ifdef CONFIG_ARCH_CNS3XXX
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+ if (t->transfer_list.next == &m->transfers) {
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+ t->last_in_message_list = 1;
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+ } else {
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+ t->last_in_message_list = 0;
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+ }
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+#endif
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status = bitbang->txrx_bufs(spi, t);
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}
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if (status > 0)
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--- a/drivers/spi/spi.c
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+++ b/drivers/spi/spi.c
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@@ -769,6 +769,89 @@ int spi_write_then_read(struct spi_devic
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}
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EXPORT_SYMBOL_GPL(spi_write_then_read);
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+#ifdef CONFIG_ARCH_CNS3XXX
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+/**
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+ * spi_write_read_sync - SPI synchronous write & read
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+ * @spi: device with which data will be exchanged
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+ * @txbuf: data to be written (need not be dma-safe)
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+ * @n_tx: size of txbuf, in bytes
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+ * @rxbuf: buffer into which data will be read
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+ * @n_rx: size of rxbuf, in bytes (need not be dma-safe)
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+ *
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+ * This performs a half duplex MicroWire style transaction with the
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+ * device, sending txbuf and then reading rxbuf. The return value
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+ * is zero for success, else a negative errno status code.
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+ * This call may only be used from a context that may sleep.
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+ *
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+ * Parameters to this routine are always copied using a small buffer;
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+ * performance-sensitive or bulk transfer code should instead use
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+ * spi_{async,sync}() calls with dma-safe buffers.
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+ */
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+int spi_write_read_sync(struct spi_device *spi,
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+ const u8 *txbuf, unsigned n_tx,
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+ u8 *rxbuf, unsigned n_rx)
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+{
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+ static DECLARE_MUTEX(lock);
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+
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+ int status;
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+ struct spi_message message;
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+ struct spi_transfer x;
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+ u8 *local_buf;
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+
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+ /* Use preallocated DMA-safe buffer. We can't avoid copying here,
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+ * (as a pure convenience thing), but we can keep heap costs
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+ * out of the hot path ...
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+ */
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+#if 0
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+ while (!str8131_spi_bus_idle()){
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+ printk("spi bus is not idle \n"); // do nothing
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+ }
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+ while (!str8131_spi_tx_buffer_empty()){
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+ printk("spi tx buffer is not empty \n"); // do nothing
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+ }
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+#endif
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+ if ((n_tx + n_rx) > SPI_BUFSIZ)
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+ return -EINVAL;
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+ spi_message_init(&message);
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+ memset(&x, 0, sizeof x);
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+ x.len = n_tx;
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+ spi_message_add_tail(&x, &message);
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+
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+ /* ... unless someone else is using the pre-allocated buffer */
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+ if (down_trylock(&lock)) {
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+ local_buf = kmalloc(SPI_BUFSIZ, GFP_KERNEL);
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+ if (!local_buf)
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+ return -ENOMEM;
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+ } else
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+ local_buf = buf;
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+
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+ memcpy(local_buf, txbuf, n_tx);
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+ x.tx_buf = local_buf;
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+ x.rx_buf = local_buf + n_tx;
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+
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+ /* do the i/o */
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+ status = spi_sync(spi, &message);
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+ if (status == 0) {
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+ memcpy(rxbuf, x.rx_buf, n_rx);
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+ status = message.status;
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+ }
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+
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+ if (x.tx_buf == buf)
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+ up(&lock);
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+ else
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+ kfree(local_buf);
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+
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+ return status;
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+}
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+
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+EXPORT_SYMBOL_GPL(spi_write_read_sync);
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+#endif /* CONFIG_ARCH_CNS3XXX */
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+
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+
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+
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+
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+
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+
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/*-------------------------------------------------------------------------*/
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static int __init spi_init(void)
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--- /dev/null
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+++ b/drivers/spi/spi_cns3xxx.c
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@@ -0,0 +1,878 @@
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+/*******************************************************************************
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+ *
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+ * CNS3XXX SPI controller driver (master mode only)
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+ *
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+ * Copyright (c) 2008 Cavium Networks
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+ *
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+ * This file is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License, Version 2, as
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+ * published by the Free Software Foundation.
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+ *
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+ * This file is distributed in the hope that it will be useful,
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+ * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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+ * NONINFRINGEMENT. See the GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this file; if not, write to the Free Software
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+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA or
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+ * visit http://www.gnu.org/licenses/.
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+ *
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+ * This file may also be available under a different license from Cavium.
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+ * Contact Cavium Networks for more information
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+ *
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+ ******************************************************************************/
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+
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+#include <linux/init.h>
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+#include <linux/spinlock.h>
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+#include <linux/workqueue.h>
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+#include <linux/interrupt.h>
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+#include <linux/delay.h>
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+#include <linux/errno.h>
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+#include <linux/err.h>
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+#include <linux/clk.h>
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+#include <linux/platform_device.h>
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+
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+#include <linux/spi/spi.h>
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+#include <linux/spi/spi_bitbang.h>
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+#include <linux/mtd/partitions.h>
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+#include <linux/dma-mapping.h>
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+
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+#include <asm/io.h>
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+#include <asm/memory.h>
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+#include <asm/dma.h>
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+#include <asm/delay.h>
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+#include <mach/board.h>
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+#include <mach/dmac.h>
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+#include <linux/module.h>
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+#include <mach/misc.h>
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+#include <mach/gpio.h>
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+#include <mach/pm.h>
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+
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+#define LE8221_SPI_CS 1
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+#define SI3226_SPI_CS 1
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+
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+#define CNS3XXX_SPI_INTERRUPT
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+#undef CNS3XXX_SPI_INTERRUPT /* Interrupt is not supported for D2 and SEN */
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+
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+/*
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+ * define access macros
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+ */
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+#define SPI_MEM_MAP_VALUE(reg_offset) (*((u32 volatile *)(CNS3XXX_SSP_BASE_VIRT + reg_offset)))
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+
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+#define SPI_CONFIGURATION_REG SPI_MEM_MAP_VALUE(0x40)
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+#define SPI_SERVICE_STATUS_REG SPI_MEM_MAP_VALUE(0x44)
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+#define SPI_BIT_RATE_CONTROL_REG SPI_MEM_MAP_VALUE(0x48)
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+#define SPI_TRANSMIT_CONTROL_REG SPI_MEM_MAP_VALUE(0x4C)
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+#define SPI_TRANSMIT_BUFFER_REG SPI_MEM_MAP_VALUE(0x50)
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+#define SPI_RECEIVE_CONTROL_REG SPI_MEM_MAP_VALUE(0x54)
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+#define SPI_RECEIVE_BUFFER_REG SPI_MEM_MAP_VALUE(0x58)
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+#define SPI_FIFO_TRANSMIT_CONFIG_REG SPI_MEM_MAP_VALUE(0x5C)
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+#define SPI_FIFO_TRANSMIT_CONTROL_REG SPI_MEM_MAP_VALUE(0x60)
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+#define SPI_FIFO_RECEIVE_CONFIG_REG SPI_MEM_MAP_VALUE(0x64)
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+#define SPI_INTERRUPT_STATUS_REG SPI_MEM_MAP_VALUE(0x68)
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+#define SPI_INTERRUPT_ENABLE_REG SPI_MEM_MAP_VALUE(0x6C)
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+
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+#define SPI_TRANSMIT_BUFFER_REG_ADDR (CNS3XXX_SSP_BASE +0x50)
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+#define SPI_RECEIVE_BUFFER_REG_ADDR (CNS3XXX_SSP_BASE +0x58)
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+
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+/* Structure for SPI controller of CNS3XXX SOCs */
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+struct cns3xxx_spi {
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+ /* bitbang has to be first */
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+ struct spi_bitbang bitbang;
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+ struct completion done;
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+ wait_queue_head_t wait;
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+
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+ int len;
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+ int count;
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+ int last_in_message_list;
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+
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+ /* data buffers */
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+ const unsigned char *tx;
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+ unsigned char *rx;
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+
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+ struct spi_master *master;
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+ struct platform_device *pdev;
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+ struct device *dev;
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+};
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+
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+static inline u8 cns3xxx_spi_bus_idle(void)
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+{
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+ return ((SPI_SERVICE_STATUS_REG & 0x1) ? 0 : 1);
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+}
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+
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+static inline u8 cns3xxx_spi_tx_buffer_empty(void)
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+{
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+ return ((SPI_INTERRUPT_STATUS_REG & (0x1 << 3)) ? 1 : 0);
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+}
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+
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+static inline u8 cns3xxx_spi_rx_buffer_full(void)
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+{
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+ return ((SPI_INTERRUPT_STATUS_REG & (0x1 << 2)) ? 1 : 0);
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+}
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+
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+u8 cns3xxx_spi_tx_rx(u8 tx_channel, u8 tx_eof, u32 tx_data,
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+ u32 * rx_data)
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+{
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+ u8 rx_channel;
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+ u8 rx_eof;
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+
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+ while (!cns3xxx_spi_bus_idle()) ; // do nothing
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+
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+ while (!cns3xxx_spi_tx_buffer_empty()) ; // do nothing
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+
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+ SPI_TRANSMIT_CONTROL_REG &= ~(0x7);
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+ SPI_TRANSMIT_CONTROL_REG |= (tx_channel & 0x3) | ((tx_eof & 0x1) << 2);
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+
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+ SPI_TRANSMIT_BUFFER_REG = tx_data;
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+
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+ while (!cns3xxx_spi_rx_buffer_full()) ; // do nothing
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+
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+ rx_channel = SPI_RECEIVE_CONTROL_REG & 0x3;
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+ rx_eof = (SPI_RECEIVE_CONTROL_REG & (0x1 << 2)) ? 1 : 0;
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+
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+ *rx_data = SPI_RECEIVE_BUFFER_REG;
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+
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+ if ((tx_channel != rx_channel) || (tx_eof != rx_eof)) {
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+ return 0;
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+ } else {
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+ return 1;
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+ }
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+}
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+
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+u8 cns3xxx_spi_tx(u8 tx_channel, u8 tx_eof, u32 tx_data)
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+{
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+
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+ while (!cns3xxx_spi_bus_idle()) ; // do nothing
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+
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+ while (!cns3xxx_spi_tx_buffer_empty()) ; // do nothing
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+
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+ SPI_TRANSMIT_CONTROL_REG &= ~(0x7);
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+ SPI_TRANSMIT_CONTROL_REG |= (tx_channel & 0x3) | ((tx_eof & 0x1) << 2);
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+
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+ SPI_TRANSMIT_BUFFER_REG = tx_data;
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+
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+ return 1;
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+}
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+
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+
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+
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+#ifdef CONFIG_SPI_CNS3XXX_DEBUG
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+static void spi_slave_probe(void)
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+{
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+ int i;
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+ u32 rx_data1, rx_data2, rx_data3;
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+
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+ cns3xxx_spi_tx_rx(0, 0, 0x9f, &rx_data1);
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+ cns3xxx_spi_tx_rx(0, 0, 0xff, &rx_data1);
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+ cns3xxx_spi_tx_rx(0, 0, 0xff, &rx_data2);
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+ cns3xxx_spi_tx_rx(0, 1, 0xff, &rx_data3);
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+ printk("[SPI_CNS3XXX_DEBUG] manufacturer: %x\n", rx_data1);
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+ printk("[SPI_CNS3XXX_DEBUG] device: %x\n",
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+ ((rx_data2 & 0xff) << 8) | (u16) (rx_data3 & 0xff));
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+
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+ cns3xxx_spi_tx_rx(0, 0, 0x03, &rx_data1);
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+ cns3xxx_spi_tx_rx(0, 0, 0x00, &rx_data1);
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+ cns3xxx_spi_tx_rx(0, 0, 0x00, &rx_data1);
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+ cns3xxx_spi_tx_rx(0, 0, 0x00, &rx_data1);
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+ for (i = 0; i < 15; i++) {
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+ cns3xxx_spi_tx_rx(0, 0, 0xff, &rx_data1);
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+ printk("[SPI_CNS3XXX_DEBUG] flash[%02d]:0x%02x\n", i,
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+ rx_data1 & 0xff);
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+ }
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+ cns3xxx_spi_tx_rx(0, 1, 0xff, &rx_data1);
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+ printk("[SPI_CNS3XXX_DEBUG] flash[%02d]:0x%02x\n", i, rx_data1 & 0xff);
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+}
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+#else
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+#define spi_slave_probe() do{}while(0)
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+#endif
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+
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+static inline struct cns3xxx_spi *to_hw(struct spi_device *sdev)
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+{
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+ return spi_master_get_devdata(sdev->master);
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+}
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+
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+static int cns3xxx_spi_setup_transfer(struct spi_device *spi,
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+ struct spi_transfer *t)
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+{
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+ return 0;
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+}
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+
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+static void cns3xxx_spi_chipselect(struct spi_device *spi, int value)
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+{
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+ unsigned int spi_config;
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+
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+ switch (value) {
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+ case BITBANG_CS_INACTIVE:
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+ break;
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+
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+ case BITBANG_CS_ACTIVE:
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+ spi_config = SPI_CONFIGURATION_REG;
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+
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+ if (spi->mode & SPI_CPHA)
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+ spi_config |= (0x1 << 13);
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+ else
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+ spi_config &= ~(0x1 << 13);
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+
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+ if (spi->mode & SPI_CPOL)
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+ spi_config |= (0x1 << 14);
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+ else
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+ spi_config &= ~(0x1 << 14);
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+
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+ /* write new configration */
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+ SPI_CONFIGURATION_REG = spi_config;
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+
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+ SPI_TRANSMIT_CONTROL_REG &= ~(0x7);
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+ SPI_TRANSMIT_CONTROL_REG |= (spi->chip_select & 0x3);
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+
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+#if defined(CONFIG_LE8221_CONTROL)
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+ if (spi->chip_select == LE8221_SPI_CS) {
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+ SPI_CONFIGURATION_REG |= (0x1 << 9);
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+ }
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+#elif defined (CONFIG_SI3226_CONTROL_API)
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+ if (spi->chip_select == SI3226_SPI_CS) {
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+ SPI_CONFIGURATION_REG &= ~(0x1 << 9);
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+ }
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+#endif
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+ break;
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+ }
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+}
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+
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+static int cns3xxx_spi_setup(struct spi_device *spi)
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+{
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+ if (!spi->bits_per_word)
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+ spi->bits_per_word = 8;
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+
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+ return 0;
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+}
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+
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+#ifdef CONFIG_SPI_CNS3XXX_USEDMA
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+
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+int cns3xxx_spi_dma_irq_handler(void *pdata)
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+{
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+
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+ struct cns3xxx_spi *hw = pdata;
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+ complete(&hw->done);
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+
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+ return 0;
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+}
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+
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+static int cns3xxx_spi_dma_initialize(int *rxchan, int *txchan, int *rxevtno,
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+ int *txevtno, void *handlerargs)
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+{
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+ *rxchan = dmac_get_channel(cns3xxx_spi_dma_irq_handler, handlerargs);
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+ if ((*rxchan) == -1)
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+ goto fail1;
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+ *txchan = dmac_get_channel(NULL, NULL);
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+ if ((*txchan) == -1)
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+ goto fail2;
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+ *rxevtno = 9;
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+ if (dmac_get_event(*rxchan, *rxevtno) == -1)
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+ goto fail3;
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+ *txevtno = 10;
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+ if (dmac_get_event(*txchan, *txevtno) == -1)
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+ goto fail4;
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+ return 0;
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+
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+fail4:
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+ dmac_release_event(*rxchan, *rxevtno);
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+fail3:
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+ dmac_release_channel(*txchan);
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+fail2:
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+ dmac_release_channel(*rxchan);
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+fail1:
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+ return -1;
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+}
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+
|
|
+static int cns3xxx_spi_start_dma(int rch, int tch, int rev, int tev,
|
|
+ struct spi_transfer *t, struct cns3xxx_spi *hw)
|
|
+{
|
|
+ static void *dummy;
|
|
+ static dma_addr_t dummy_dma;
|
|
+ dma_addr_t rdma, tdma;
|
|
+ int rx_inc, tx_inc;
|
|
+ int lc0, totlps, lc1, rump;
|
|
+ u32 rx_data;
|
|
+
|
|
+ if (!dummy) {
|
|
+ dummy = dma_alloc_coherent(NULL, 16, &dummy_dma, GFP_KERNEL);
|
|
+#ifdef CONFIG_SPI_CNS3XXX_DEBUG_DMA
|
|
+ printk("Allocated Memory for dummy buffer va:%p,pa:%x\n", dummy,
|
|
+ dummy_dma);
|
|
+#endif
|
|
+ }
|
|
+ if (!dummy) {
|
|
+ return -1;
|
|
+ }
|
|
+ *((uint32_t *) dummy) = 0xffffffff;
|
|
+
|
|
+ (t->tx_buf) ? (tdma = t->tx_dma, tx_inc = 1) :
|
|
+ (tdma = dummy_dma, tx_inc = 0);
|
|
+ (t->rx_buf) ? (rdma = t->rx_dma, rx_inc = 1) :
|
|
+ (rdma = dummy_dma, rx_inc = 0);
|
|
+
|
|
+#ifdef CONFIG_SPI_CNS3XXX_DEBUG_DMA
|
|
+ printk("Here with tdma %x, rdma %x\n", tdma, rdma);
|
|
+#endif
|
|
+
|
|
+ if(t->len < 3) {
|
|
+ if(t->len == 2){
|
|
+ cns3xxx_spi_tx_rx(0,0,(t->tx_buf) ? hw->tx[0] : 0xff ,&rx_data);
|
|
+ if(!(t->tx_buf))
|
|
+ hw->rx[0] = rx_data & 0xff;
|
|
+ }
|
|
+ cns3xxx_spi_dma_irq_handler(hw);
|
|
+ return 0;
|
|
+ }
|
|
+
|
|
+
|
|
+ totlps = t->len - 1 -1;
|
|
+ if (totlps > 0x100) {
|
|
+ lc0 = 0x100;
|
|
+ lc1 = totlps / lc0;
|
|
+ rump = totlps % lc0;
|
|
+ } else {
|
|
+ lc0 = totlps;
|
|
+ lc1 = 0;
|
|
+ rump = 0;
|
|
+ }
|
|
+
|
|
+ if(t->tx_buf) {
|
|
+ cns3xxx_spi_tx(0,0,*((uint32_t *) t->tx_buf));
|
|
+ tdma+=1;
|
|
+ }
|
|
+ else {
|
|
+ cns3xxx_spi_tx(0,0,0xff);
|
|
+ }
|
|
+
|
|
+ //SPI_RECEIVE_BUFFER_REG;
|
|
+ {
|
|
+ DMAC_DMAMOV(tch, SAR, tdma);
|
|
+ DMAC_DMAMOV(tch, DAR, SPI_TRANSMIT_BUFFER_REG_ADDR);
|
|
+ DMAC_DMAMOV(tch, CCR,
|
|
+ dmac_create_ctrlval(tx_inc, 1, 1, 0, 1, 1, 0));
|
|
+ //DMAC_WFE(tch, rev);
|
|
+ if (lc1)
|
|
+ DMAC_DMALP(tch, 1, lc1);
|
|
+ DMAC_DMALP(tch, 0, lc0);
|
|
+ DMAC_WFE(tch, rev);
|
|
+ DMAC_DMALDS(tch);
|
|
+ DMAC_DMASTS(tch);
|
|
+ DMAC_DMAWMB(tch);
|
|
+ DMAC_DMASEV(tch, tev);
|
|
+ DMAC_DMALPEND(tch, 0,
|
|
+ DMAWFE_INSTR_SIZE + DMASEV_INSTR_SIZE +
|
|
+ DMAWMB_INSTR_SIZE + DMAST_INSTR_SIZE +
|
|
+ DMALD_INSTR_SIZE, 1);
|
|
+ if (lc1)
|
|
+ DMAC_DMALPEND(tch, 1,
|
|
+ DMALP_INSTR_SIZE + DMALPEND_INSTR_SIZE +
|
|
+ DMAWFE_INSTR_SIZE + DMASEV_INSTR_SIZE +
|
|
+ DMAWMB_INSTR_SIZE + DMAST_INSTR_SIZE +
|
|
+ DMALD_INSTR_SIZE, 1);
|
|
+
|
|
+ if (rump) {
|
|
+ DMAC_DMALP(tch, 0, rump);
|
|
+ DMAC_WFE(tch, rev);
|
|
+ DMAC_DMALDS(tch);
|
|
+ DMAC_DMASTS(tch);
|
|
+ DMAC_DMAWMB(tch);
|
|
+ DMAC_DMASEV(tch, tev);
|
|
+ DMAC_DMALPEND(tch, 0,
|
|
+ DMAWFE_INSTR_SIZE + DMASEV_INSTR_SIZE +
|
|
+ DMAWMB_INSTR_SIZE + DMAST_INSTR_SIZE +
|
|
+ DMALD_INSTR_SIZE, 1);
|
|
+ }
|
|
+
|
|
+
|
|
+ DMAC_DMAEND(tch);
|
|
+ DMAC_DMAGO(tch);
|
|
+ }
|
|
+ {
|
|
+ DMAC_DMAMOV(rch, SAR, SPI_RECEIVE_BUFFER_REG_ADDR);
|
|
+ DMAC_DMAMOV(rch, DAR, rdma);
|
|
+ DMAC_DMAMOV(rch, CCR,
|
|
+ dmac_create_ctrlval(0, 1, 1, rx_inc, 1, 1, 0));
|
|
+
|
|
+ if (lc1)
|
|
+ DMAC_DMALP(rch, 1, lc1);
|
|
+ DMAC_DMALP(rch, 0, lc0);
|
|
+ DMAC_DMAWFP(rch, DMAC_SPI_PERIPH_ID, PERIPHERAL);
|
|
+ DMAC_DMALDP(rch, DMAC_SPI_PERIPH_ID, 0);
|
|
+ DMAC_DMASTS(rch);
|
|
+ DMAC_DMAWMB(rch);
|
|
+ DMAC_DMASEV(rch, rev);
|
|
+ DMAC_WFE(rch, tev);
|
|
+ DMAC_DMALPEND(rch, 0,
|
|
+ DMAWFE_INSTR_SIZE + DMASEV_INSTR_SIZE +
|
|
+ DMAWMB_INSTR_SIZE + DMAST_INSTR_SIZE +
|
|
+ DMALDP_INSTR_SIZE + DMAWFP_INSTR_SIZE, 1);
|
|
+ if (lc1)
|
|
+ DMAC_DMALPEND(rch, 1,
|
|
+ DMAWFE_INSTR_SIZE +
|
|
+ DMASEV_INSTR_SIZE + DMAWMB_INSTR_SIZE +
|
|
+ DMAST_INSTR_SIZE + DMALDP_INSTR_SIZE +
|
|
+ DMAWFP_INSTR_SIZE + DMALP_INSTR_SIZE +
|
|
+ DMALPEND_INSTR_SIZE, 1);
|
|
+
|
|
+
|
|
+ if (rump) {
|
|
+ DMAC_DMALP(rch, 0, rump);
|
|
+ DMAC_DMAWFP(rch, DMAC_SPI_PERIPH_ID, PERIPHERAL);
|
|
+ DMAC_DMALDP(rch, DMAC_SPI_PERIPH_ID, 0);
|
|
+ DMAC_DMASTS(rch);
|
|
+ DMAC_DMAWMB(rch);
|
|
+ DMAC_DMASEV(rch, rev);
|
|
+ DMAC_WFE(rch, tev);
|
|
+ DMAC_DMALPEND(rch, 0,
|
|
+ DMAWFE_INSTR_SIZE +
|
|
+ DMASEV_INSTR_SIZE + DMAWMB_INSTR_SIZE +
|
|
+ DMAST_INSTR_SIZE + DMALDP_INSTR_SIZE +
|
|
+ DMAWFP_INSTR_SIZE, 1);
|
|
+ }
|
|
+ // extra RX
|
|
+ DMAC_DMAWFP(rch, DMAC_SPI_PERIPH_ID, PERIPHERAL);
|
|
+ DMAC_DMALDP(rch, DMAC_SPI_PERIPH_ID, 0);
|
|
+ DMAC_DMASTS(rch);
|
|
+ DMAC_DMAWMB(rch);
|
|
+
|
|
+ DMAC_DMAFLUSHP(rch, DMAC_SPI_PERIPH_ID);
|
|
+ DMAC_DMASEV(rch, rch); // This will generate an interrupt
|
|
+ DMAC_DMAEND(rch);
|
|
+ DMAC_DMAGO(rch);
|
|
+ }
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void cns3xxx_spi_dma_uninitialize(int rch, int tch, int revt, int tevt)
|
|
+{
|
|
+ dmac_release_event(rch, revt);
|
|
+ dmac_release_event(tch, tevt);
|
|
+ dmac_release_channel(rch);
|
|
+ dmac_release_channel(tch);
|
|
+ return;
|
|
+}
|
|
+
|
|
+#endif /* CONFIG_SPI_CNS3XXX_USEDMA */
|
|
+
|
|
+static int cns3xxx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
|
|
+{
|
|
+ struct cns3xxx_spi *hw = to_hw(spi);
|
|
+#ifdef CONFIG_SPI_CNS3XXX_USEDMA
|
|
+ int spi_rxchan, spi_txchan, spi_rxevt, spi_txevt;
|
|
+ int rx_data;
|
|
+#endif
|
|
+ dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", t->tx_buf, t->rx_buf,
|
|
+ t->len);
|
|
+
|
|
+ hw->tx = t->tx_buf;
|
|
+ hw->rx = t->rx_buf;
|
|
+ hw->len = t->len;
|
|
+ hw->count = 0;
|
|
+ hw->last_in_message_list = t->last_in_message_list;
|
|
+
|
|
+#ifdef CONFIG_SPI_CNS3XXX_USEDMA
|
|
+ init_completion(&hw->done);
|
|
+
|
|
+ if (cns3xxx_spi_dma_initialize
|
|
+ (&spi_rxchan, &spi_txchan, &spi_rxevt, &spi_txevt, hw)) {
|
|
+ dev_dbg(&spi->dev, "%s:%d Could not initialize DMA. \n",
|
|
+ __FUNCTION__, __LINE__);
|
|
+ return 0;
|
|
+ }
|
|
+
|
|
+ if (t->tx_buf)
|
|
+ t->tx_dma =
|
|
+ dma_map_single(NULL, t->tx_buf, t->len, DMA_TO_DEVICE);
|
|
+ if (t->rx_buf)
|
|
+ t->rx_dma =
|
|
+ dma_map_single(NULL, t->rx_buf, t->len, DMA_FROM_DEVICE);
|
|
+
|
|
+ if (cns3xxx_spi_start_dma
|
|
+ (spi_rxchan, spi_txchan, spi_rxevt, spi_txevt, t, hw)) {
|
|
+ dev_dbg(&spi->dev, "Could not start DMA. \n");
|
|
+ if (t->tx_buf)
|
|
+ dma_unmap_single(NULL, t->tx_dma, t->len,
|
|
+ DMA_TO_DEVICE);
|
|
+ t->tx_dma = 0;
|
|
+ if (t->rx_buf)
|
|
+ dma_unmap_single(NULL, t->rx_dma, t->len,
|
|
+ DMA_FROM_DEVICE);
|
|
+ t->rx_dma = 0;
|
|
+ cns3xxx_spi_dma_uninitialize(spi_rxchan, spi_txchan, spi_rxevt,
|
|
+ spi_txevt);
|
|
+ return 0;
|
|
+ }
|
|
+
|
|
+ wait_for_completion(&hw->done);
|
|
+
|
|
+ dev_dbg(&spi->dev, "DMA reported completion of transfer of %d bytes\n",
|
|
+ t->len - 1);
|
|
+
|
|
+ if (t->tx_buf)
|
|
+ dma_unmap_single(NULL, t->tx_dma, t->len, DMA_TO_DEVICE);
|
|
+ t->tx_dma = 0;
|
|
+ if (t->rx_buf)
|
|
+ dma_unmap_single(NULL, t->rx_dma, t->len, DMA_FROM_DEVICE);
|
|
+ t->rx_dma = 0;
|
|
+ cns3xxx_spi_dma_uninitialize(spi_rxchan, spi_txchan, spi_rxevt,
|
|
+ spi_txevt);
|
|
+
|
|
+ if (t->last_in_message_list)
|
|
+ cns3xxx_spi_tx_rx(spi->chip_select, 1,
|
|
+ (hw->tx) ? hw->tx[hw->len - 1] : 0xff,
|
|
+ &rx_data);
|
|
+ else
|
|
+ cns3xxx_spi_tx_rx(spi->chip_select, 0,
|
|
+ (hw->tx) ? hw->tx[hw->len - 1] : 0xff,
|
|
+ &rx_data);
|
|
+
|
|
+ if (hw->rx)
|
|
+ hw->rx[hw->len - 1] = rx_data & 0xff;
|
|
+
|
|
+ return hw->len;
|
|
+
|
|
+#else /* !CONFIG_SPI_CNS3XXX_USEDMA */
|
|
+
|
|
+#ifdef CNS3XXX_SPI_INTERRUPT
|
|
+
|
|
+ init_completion(&hw->done);
|
|
+
|
|
+ /* Effectively, we are enabling only the Receive Buffer Interrupt Enable */
|
|
+ /* TX Buf Underrun and RX Buf Overrun are not to happen */
|
|
+ SPI_INTERRUPT_ENABLE_REG = (0x1 << 2);
|
|
+// (0x0) | (0x1 << 2) | (0x0 << 3) | (0x1 << 6) | (0x1 << 7);
|
|
+
|
|
+ /* Write data and wait for completion */
|
|
+ SPI_TRANSMIT_CONTROL_REG &= ~(0x7);
|
|
+ SPI_TRANSMIT_CONTROL_REG |= (spi->chip_select & 0x3) |
|
|
+ ((((hw->last_in_message_list) && (hw->len == 1)) ? 0x1 : 0x0) << 2);
|
|
+
|
|
+ SPI_TRANSMIT_BUFFER_REG = (hw->tx) ? hw->tx[hw->count] : 0xff;
|
|
+
|
|
+ wait_for_completion(&hw->done);
|
|
+
|
|
+ SPI_INTERRUPT_ENABLE_REG = 0;
|
|
+
|
|
+ return hw->count;
|
|
+
|
|
+#else /* !CNS3XXX_SPI_INTERRUPT */
|
|
+
|
|
+ init_completion(&hw->done);
|
|
+
|
|
+ if (hw->tx) {
|
|
+ int i;
|
|
+ u32 rx_data;
|
|
+ for (i = 0; i < (hw->len - 1); i++) {
|
|
+ dev_dbg(&spi->dev,
|
|
+ "[SPI_CNS3XXX_DEBUG] hw->tx[%02d]: 0x%02x\n", i,
|
|
+ hw->tx[i]);
|
|
+ cns3xxx_spi_tx_rx(spi->chip_select, 0, hw->tx[i],
|
|
+ &rx_data);
|
|
+ if (hw->rx) {
|
|
+ hw->rx[i] = rx_data;
|
|
+ dev_dbg(&spi->dev,
|
|
+ "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n",
|
|
+ i, hw->rx[i]);
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (t->last_in_message_list) {
|
|
+ cns3xxx_spi_tx_rx(spi->chip_select, 1, hw->tx[i],
|
|
+ &rx_data);
|
|
+ if (hw->rx) {
|
|
+ hw->rx[i] = rx_data;
|
|
+ dev_dbg(&spi->dev,
|
|
+ "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n",
|
|
+ i, hw->rx[i]);
|
|
+ }
|
|
+ } else {
|
|
+ cns3xxx_spi_tx_rx(spi->chip_select, 0, hw->tx[i],
|
|
+ &rx_data);
|
|
+ }
|
|
+ goto done;
|
|
+ }
|
|
+
|
|
+ if (hw->rx) {
|
|
+ int i;
|
|
+ u32 rx_data;
|
|
+ for (i = 0; i < (hw->len - 1); i++) {
|
|
+ cns3xxx_spi_tx_rx(spi->chip_select, 0, 0xff, &rx_data);
|
|
+ hw->rx[i] = rx_data;
|
|
+ dev_dbg(&spi->dev,
|
|
+ "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n", i,
|
|
+ hw->rx[i]);
|
|
+ }
|
|
+
|
|
+ if (t->last_in_message_list) {
|
|
+ cns3xxx_spi_tx_rx(spi->chip_select, 1, 0xff, &rx_data);
|
|
+ } else {
|
|
+ cns3xxx_spi_tx_rx(spi->chip_select, 0, 0xff, &rx_data);
|
|
+ }
|
|
+ hw->rx[i] = rx_data;
|
|
+ dev_dbg(&spi->dev, "[SPI_CNS3XXX_DEBUG] hw->rx[%02d]: 0x%02x\n",
|
|
+ i, hw->rx[i]);
|
|
+ }
|
|
+done:
|
|
+ return hw->len;
|
|
+
|
|
+#endif /* CNS3XXX_SPI_INTERRUPT */
|
|
+
|
|
+#endif /* CONFIG_SPI_CNS3XXX_USEDMA */
|
|
+}
|
|
+
|
|
+#ifdef CNS3XXX_SPI_INTERRUPT
|
|
+/* Driver supports single master only.
|
|
+ * We have disabled fifo, so we wait for the receive buff full interrupt.
|
|
+ * Receive Buff overrun, transmit buff underrun are not to happen
|
|
+ */
|
|
+static irqreturn_t cns3xxx_spi_irq(int irq, void *dev)
|
|
+{
|
|
+ struct cns3xxx_spi *hw = dev;
|
|
+ uint32_t int_status;
|
|
+ uint8_t data;
|
|
+ unsigned int count = hw->count;
|
|
+
|
|
+ /* Read the interrupt status and clear interrupt */
|
|
+ int_status = SPI_INTERRUPT_STATUS_REG;
|
|
+
|
|
+ if (!(int_status & (0x1 << 2))) {
|
|
+ printk("DEBUG THIS ! Unexpected interrupt (status = 0x%x)", int_status);
|
|
+ /* Clearing spurious interrupts */
|
|
+ SPI_INTERRUPT_STATUS_REG = (0xF << 4);
|
|
+ goto irq_done;
|
|
+ }
|
|
+
|
|
+ /* Read to clear */
|
|
+ data = SPI_RECEIVE_BUFFER_REG & 0xff;
|
|
+
|
|
+ if (hw->rx)
|
|
+ hw->rx[hw->count] = data;
|
|
+
|
|
+ hw->count++;
|
|
+ hw->len--;
|
|
+
|
|
+ if (hw->len) {
|
|
+ SPI_TRANSMIT_CONTROL_REG |=
|
|
+ ((((hw->last_in_message_list) && (hw->len == 1)) ? 0x1 : 0x0) << 2);
|
|
+ SPI_TRANSMIT_BUFFER_REG = (hw->tx) ? hw->tx[hw->count] : 0xff;
|
|
+ } else {
|
|
+ complete(&hw->done);
|
|
+ }
|
|
+
|
|
+irq_done:
|
|
+ return IRQ_HANDLED;
|
|
+}
|
|
+#endif
|
|
+
|
|
+static void __init cns3xxx_spi_initial(void)
|
|
+{
|
|
+
|
|
+ /* share pin config. */
|
|
+#if 1
|
|
+#if 0
|
|
+ /* GPIOB18 is set to PCM by default */
|
|
+ MISC_GPIOB_PIN_ENABLE_REG &= ~(MISC_GSW_P0_CRS_PIN);
|
|
+ gpio_direction_output(50, 1);
|
|
+#endif
|
|
+ PM_PLL_HM_PD_CTRL_REG &= ~(0x1 << 5);
|
|
+ HAL_MISC_ENABLE_SPI_PINS();
|
|
+ HAL_MISC_ENABLE_PCM_PINS(); /* this just for PCM test */
|
|
+ cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SPI_PCM_I2C));
|
|
+ cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SPI_PCM_I2C));
|
|
+#endif
|
|
+
|
|
+ SPI_CONFIGURATION_REG = (((0x0 & 0x3) << 0) | /* 8bits shift length */
|
|
+ (0x0 << 9) | /* SPI mode */
|
|
+ (0x0 << 10) | /* disable FIFO */
|
|
+ (0x1 << 11) | /* SPI master mode */
|
|
+ (0x0 << 12) | /* disable SPI loopback mode */
|
|
+ (0x1 << 13) | /* clock phase */
|
|
+ (0x1 << 14) | /* clock polarity */
|
|
+ (0x0 << 24) | /* disable - SPI data swap */
|
|
+#ifdef CONFIG_SPI_CNS3XXX_2IOREAD
|
|
+ (0x1 << 29) | /* enable - 2IO Read mode */
|
|
+#else
|
|
+ (0x0 << 29) | /* disablea - 2IO Read mode */
|
|
+#endif
|
|
+ (0x0 << 30) | /* disable - SPI high speed read for system boot up */
|
|
+ (0x0 << 31)); /* disable - SPI */
|
|
+
|
|
+ /* Set SPI bit rate PCLK/2 */
|
|
+ SPI_BIT_RATE_CONTROL_REG = 0x1;
|
|
+
|
|
+ /* Set SPI Tx channel 0 */
|
|
+ SPI_TRANSMIT_CONTROL_REG = 0x0;
|
|
+
|
|
+ /* Set Tx FIFO Threshold, Tx FIFO has 2 words */
|
|
+ SPI_FIFO_TRANSMIT_CONFIG_REG &= ~(0x03 << 4);
|
|
+ SPI_FIFO_TRANSMIT_CONFIG_REG |= ((0x0 & 0x03) << 4);
|
|
+
|
|
+ /* Set Rx FIFO Threshold, Rx FIFO has 2 words */
|
|
+ SPI_FIFO_RECEIVE_CONFIG_REG &= ~(0x03 << 4);
|
|
+ SPI_FIFO_RECEIVE_CONFIG_REG |= ((0x0 & 0x03) << 4);
|
|
+
|
|
+ /* Disable all interrupt */
|
|
+ SPI_INTERRUPT_ENABLE_REG = 0x0;
|
|
+
|
|
+ /* Clear spurious interrupt sources */
|
|
+ SPI_INTERRUPT_STATUS_REG = (0x0F << 4);
|
|
+
|
|
+ /* Enable SPI */
|
|
+ SPI_CONFIGURATION_REG |= (0x1 << 31);
|
|
+
|
|
+ return;
|
|
+}
|
|
+
|
|
+static int __init cns3xxx_spi_probe(struct platform_device *pdev)
|
|
+{
|
|
+ struct spi_master *master;
|
|
+ struct cns3xxx_spi *hw;
|
|
+ int err = 0;
|
|
+
|
|
+ printk("%s: setup CNS3XXX SPI Controller", __FUNCTION__);
|
|
+#ifdef CONFIG_SPI_CNS3XXX_USEDMA
|
|
+ printk(" w/ DMA \n");
|
|
+#else
|
|
+#ifdef CNS3XXX_SPI_INTERRUPT
|
|
+ printk(" in Interrupt mode, w/o DMA \n");
|
|
+#else
|
|
+ printk(" in polling mode, w/o DMA \n");
|
|
+#endif
|
|
+#endif
|
|
+
|
|
+ /* share pin config. */
|
|
+// HAL_MISC_ENABLE_SPI_PINS();
|
|
+
|
|
+ /* Allocate master with space for cns3xxx_spi */
|
|
+ master = spi_alloc_master(&pdev->dev, sizeof(struct cns3xxx_spi));
|
|
+ if (master == NULL) {
|
|
+ dev_err(&pdev->dev, "No memory for spi_master\n");
|
|
+ err = -ENOMEM;
|
|
+ goto err_nomem;
|
|
+ }
|
|
+
|
|
+ hw = spi_master_get_devdata(master);
|
|
+ memset(hw, 0, sizeof(struct cns3xxx_spi));
|
|
+
|
|
+ hw->master = spi_master_get(master);
|
|
+ hw->dev = &pdev->dev;
|
|
+
|
|
+ platform_set_drvdata(pdev, hw);
|
|
+ init_completion(&hw->done);
|
|
+
|
|
+ /* setup the master state. */
|
|
+
|
|
+ master->num_chipselect = 4;
|
|
+ master->bus_num = 1;
|
|
+
|
|
+ /* setup the state for the bitbang driver */
|
|
+
|
|
+ hw->bitbang.master = hw->master;
|
|
+ hw->bitbang.setup_transfer = cns3xxx_spi_setup_transfer;
|
|
+ hw->bitbang.chipselect = cns3xxx_spi_chipselect;
|
|
+ hw->bitbang.txrx_bufs = cns3xxx_spi_txrx;
|
|
+ hw->bitbang.master->setup = cns3xxx_spi_setup;
|
|
+
|
|
+ dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
|
|
+
|
|
+#ifdef CNS3XXX_SPI_INTERRUPT
|
|
+ err = request_irq(IRQ_CNS3XXX_SPI, cns3xxx_spi_irq, IRQF_SHARED, "cns3xxx_spi", hw);
|
|
+ if (err) {
|
|
+ dev_err(&pdev->dev, "Cannot claim IRQ\n");
|
|
+ goto err_no_irq;
|
|
+ }
|
|
+#endif
|
|
+
|
|
+ /* SPI controller initializations */
|
|
+ cns3xxx_spi_initial();
|
|
+
|
|
+ /* register SPI controller */
|
|
+
|
|
+ err = spi_bitbang_start(&hw->bitbang);
|
|
+ if (err) {
|
|
+ dev_err(&pdev->dev, "Failed to register SPI master\n");
|
|
+ goto err_register;
|
|
+ }
|
|
+
|
|
+ spi_slave_probe();
|
|
+
|
|
+ return 0;
|
|
+
|
|
+err_register:
|
|
+#ifdef CNS3XXX_SPI_INTERRUPT
|
|
+err_no_irq:
|
|
+#endif
|
|
+ spi_master_put(hw->master);;
|
|
+
|
|
+err_nomem:
|
|
+ return err;
|
|
+}
|
|
+
|
|
+static int __devexit cns3xxx_spi_remove(struct platform_device *dev)
|
|
+{
|
|
+ struct cns3xxx_spi *hw = platform_get_drvdata(dev);
|
|
+
|
|
+ platform_set_drvdata(dev, NULL);
|
|
+
|
|
+ spi_unregister_master(hw->master);
|
|
+
|
|
+ //cns3xxx_spi_clk_disable();
|
|
+
|
|
+ spi_master_put(hw->master);
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+#ifdef CONFIG_PM
|
|
+
|
|
+static int cns3xxx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
|
|
+{
|
|
+ struct cns3xxx_spi *hw = platform_get_drvdata(pdev);
|
|
+
|
|
+ //cns3xxx_spi_clk_disable();
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int cns3xxx_spi_resume(struct platform_device *pdev)
|
|
+{
|
|
+ struct cns3xxx_spi *hw = platform_get_drvdata(pdev);
|
|
+
|
|
+ //cns3xxx_spi_clk_enable()
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+#else
|
|
+#define cns3xxx_spi_suspend NULL
|
|
+#define cns3xxx_spi_resume NULL
|
|
+#endif
|
|
+
|
|
+static struct platform_driver cns3xxx_spi_driver = {
|
|
+ .probe = cns3xxx_spi_probe,
|
|
+ .remove = __devexit_p(cns3xxx_spi_remove),
|
|
+ .suspend = cns3xxx_spi_suspend,
|
|
+ .resume = cns3xxx_spi_resume,
|
|
+ .driver = {
|
|
+ .name = "cns3xxx_spi",
|
|
+ .owner = THIS_MODULE,
|
|
+ },
|
|
+};
|
|
+
|
|
+static int __init cns3xxx_spi_init(void)
|
|
+{
|
|
+ return platform_driver_register(&cns3xxx_spi_driver);
|
|
+}
|
|
+
|
|
+static void __exit cns3xxx_spi_exit(void)
|
|
+{
|
|
+ platform_driver_unregister(&cns3xxx_spi_driver);
|
|
+}
|
|
+
|
|
+module_init(cns3xxx_spi_init);
|
|
+module_exit(cns3xxx_spi_exit);
|
|
+
|
|
+MODULE_AUTHOR("Cavium Networks");
|
|
+MODULE_DESCRIPTION("CNS3XXX SPI Controller Driver");
|
|
+MODULE_LICENSE("GPL");
|
|
+MODULE_ALIAS("platform:cns3xxx_spi");
|
|
+
|
|
+EXPORT_SYMBOL_GPL(cns3xxx_spi_tx_rx);
|
|
--- a/include/linux/spi/spi.h
|
|
+++ b/include/linux/spi/spi.h
|
|
@@ -424,6 +424,12 @@ struct spi_transfer {
|
|
u16 delay_usecs;
|
|
u32 speed_hz;
|
|
|
|
+#ifdef CONFIG_ARCH_CNS3XXX
|
|
+ unsigned last_in_message_list;
|
|
+#ifdef CONFIG_SPI_CNS3XXX_2IOREAD
|
|
+ u8 dio_read;
|
|
+#endif
|
|
+#endif
|
|
struct list_head transfer_list;
|
|
};
|
|
|
|
@@ -627,6 +633,13 @@ spi_read(struct spi_device *spi, u8 *buf
|
|
return spi_sync(spi, &m);
|
|
}
|
|
|
|
+#ifdef CONFIG_ARCH_CNS3XXX
|
|
+extern int spi_write_read_sync(struct spi_device *spi,
|
|
+ const u8 *txbuf, unsigned n_tx,
|
|
+ u8 *rxbuf, unsigned n_rx);
|
|
+
|
|
+#endif
|
|
+
|
|
/* this copies txbuf and rxbuf data; for small transfers only! */
|
|
extern int spi_write_then_read(struct spi_device *spi,
|
|
const u8 *txbuf, unsigned n_tx,
|