mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-21 12:21:30 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27297 3c298f89-4303-0410-b956-a3cf2f4a3e73
994 lines
26 KiB
Diff
994 lines
26 KiB
Diff
--- /dev/null
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+++ b/arch/arm/mach-cns3xxx/laguna.c
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@@ -0,0 +1,761 @@
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+/*
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+ * Gateworks Corporation Laguna Platform
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+ *
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+ * Copyright 2000 Deep Blue Solutions Ltd
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+ * Copyright 2008 ARM Limited
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+ * Copyright 2008 Cavium Networks
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+ * Scott Shu
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+ * Copyright 2010 MontaVista Software, LLC.
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+ * Anton Vorontsov <avorontsov@mvista.com>
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+ * Copyright 2011 Gateworks Corporation
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+ * Chris Lang <clang@gateworks.com>
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+ *
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+ * This file is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License, Version 2, as
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+ * published by the Free Software Foundation.
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+ */
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+
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+#include <linux/init.h>
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+#include <linux/kernel.h>
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+#include <linux/compiler.h>
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+#include <linux/io.h>
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+#include <linux/dma-mapping.h>
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+#include <linux/serial_core.h>
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+#include <linux/serial_8250.h>
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+#include <linux/platform_device.h>
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+#include <linux/mtd/mtd.h>
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+#include <linux/mtd/physmap.h>
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+#include <linux/mtd/partitions.h>
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+#include <linux/leds.h>
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+#include <linux/i2c.h>
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+#include <linux/i2c/at24.h>
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+#include <linux/i2c/pca953x.h>
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+#include <linux/spi/spi.h>
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+#include <linux/spi/flash.h>
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+#include <linux/if_ether.h>
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+#include <asm/setup.h>
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+#include <asm/mach-types.h>
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+#include <asm/mach/arch.h>
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+#include <asm/mach/map.h>
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+#include <asm/mach/time.h>
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+#include <mach/hardware.h>
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+#include <mach/cns3xxx.h>
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+#include <mach/irqs.h>
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+#include <mach/pm.h>
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+#include "core.h"
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+#include "devices.h"
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+
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+// Config 1 Bitmap
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+#define ETH0_LOAD BIT(0)
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+#define ETH1_LOAD BIT(1)
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+#define ETH2_LOAD BIT(2)
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+#define SATA0_LOAD BIT(3)
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+#define SATA1_LOAD BIT(4)
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+#define PCM_LOAD BIT(5)
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+#define I2S_LOAD BIT(6)
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+#define SPI0_LOAD BIT(7)
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+#define SPI1_LOAD BIT(8)
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+#define PCIE0_LOAD BIT(9)
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+#define PCIE1_LOAD BIT(10)
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+#define USB0_LOAD BIT(11)
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+#define USB1_LOAD BIT(12)
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+#define USB1_ROUTE BIT(13)
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+#define SD_LOAD BIT(14)
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+#define UART0_LOAD BIT(15)
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+#define UART1_LOAD BIT(16)
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+#define UART2_LOAD BIT(17)
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+#define MPCI0_LOAD BIT(18)
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+#define MPCI1_LOAD BIT(19)
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+#define MPCI2_LOAD BIT(20)
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+#define MPCI3_LOAD BIT(21)
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+#define FP_BUT_LOAD BIT(22)
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+#define FP_BUT_HEADER_LOAD BIT(23)
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+#define FP_LED_LOAD BIT(24)
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+#define FP_LED_HEADER_LOAD BIT(25)
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+#define FP_TAMPER_LOAD BIT(26)
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+#define HEADER_33V_LOAD BIT(27)
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+#define SATA_POWER_LOAD BIT(28)
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+#define FP_POWER_LOAD BIT(29)
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+#define GPIO_HEADER_LOAD BIT(30)
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+#define GSP_BAT_LOAD BIT(31)
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+
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+// Config 2 Bitmap
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+#define FAN_LOAD BIT(0)
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+#define SPI_FLASH_LOAD BIT(1)
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+#define NOR_FLASH_LOAD BIT(2)
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+#define GPS_LOAD BIT(3)
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+#define SUPPLY_5V_LOAD BIT(6)
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+#define SUPPLY_33V_LOAD BIT(7)
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+
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+struct laguna_board_info {
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+ char model[16];
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+ u32 config_bitmap;
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+ u32 config2_bitmap;
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+ u8 nor_flash_size;
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+ u8 spi_flash_size;
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+};
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+
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+static struct laguna_board_info laguna_info __initdata;
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+
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+/*
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+ * NOR Flash
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+ */
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+static struct mtd_partition laguna_nor_partitions[] = {
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+ {
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+ .name = "uboot",
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+ .size = SZ_256K,
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+ .offset = 0,
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+ .mask_flags = MTD_WRITEABLE,
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+ }, {
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+ .name = "params",
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+ .size = SZ_128K,
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+ .offset = SZ_256K,
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+ }, {
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+ .name = "kernel",
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+ .size = SZ_2M,
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+ .offset = SZ_256K + SZ_128K,
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+ }, {
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+ .name = "rootfs",
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+ .size = SZ_16M - SZ_256K - SZ_128K - SZ_2M,
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+ .offset = SZ_256K + SZ_128K + SZ_2M,
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+ },
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+};
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+
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+static struct physmap_flash_data laguna_nor_pdata = {
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+ .width = 2,
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+ .parts = laguna_nor_partitions,
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+ .nr_parts = ARRAY_SIZE(laguna_nor_partitions),
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+};
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+
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+static struct resource laguna_nor_res = {
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+ .start = CNS3XXX_FLASH_BASE,
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+ .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
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+ .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
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+};
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+
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+static struct platform_device laguna_nor_pdev = {
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+ .name = "physmap-flash",
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+ .id = 0,
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+ .resource = &laguna_nor_res,
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+ .num_resources = 1,
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+ .dev = {
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+ .platform_data = &laguna_nor_pdata,
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+ },
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+};
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+
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+/*
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+ * SPI
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+ */
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+static struct mtd_partition laguna_spi_partitions[] = {
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+ {
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+ .name = "uboot",
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+ .size = SZ_256K,
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+ .offset = 0,
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+ .mask_flags = MTD_WRITEABLE,
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+ }, {
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+ .name = "params",
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+ .size = SZ_256K,
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+ .offset = SZ_256K,
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+ }, {
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+ .name = "kernel",
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+ .size = SZ_1M + SZ_512K,
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+ .offset = SZ_512K,
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+ }, {
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+ .name = "rootfs",
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+ .size = SZ_16M - SZ_2M,
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+ .offset = SZ_2M,
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+ },
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+};
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+
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+static struct flash_platform_data laguna_spi_pdata = {
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+ .parts = laguna_spi_partitions,
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+ .nr_parts = ARRAY_SIZE(laguna_spi_partitions),
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+};
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+
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+static struct spi_board_info __initdata laguna_spi_devices[] = {
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+ {
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+ .modalias = "m25p80",
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+ .platform_data = &laguna_spi_pdata,
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+ .max_speed_hz = 50000000,
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+ .bus_num = 1,
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+ .chip_select = 0,
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+ },
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+};
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+
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+static struct platform_device laguna_spi_controller = {
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+ .name = "cns3xxx_spi",
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+};
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+
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+/*
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+ * LED's
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+ */
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+static struct gpio_led laguna_gpio_leds[] = {
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+ {
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+ .name = "user1", /* Green Led */
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+ .gpio = 115,
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+ .active_low = 1,
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+ },{
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+ .name = "user2", /* Red Led */
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+ .gpio = 114,
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+ .active_low = 1,
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+ },{
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+ .name = "pwr1", /* Green Led */
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+ .gpio = 116,
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+ .active_low = 1,
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+ },{
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+ .name = "pwr2", /* Yellow Led */
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+ .gpio = 117,
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+ .active_low = 1,
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+ },{
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+ .name = "txd1", /* Green Led */
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+ .gpio = 118,
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+ .active_low = 1,
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+ },{
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+ .name = "txd2", /* Yellow Led */
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+ .gpio = 119,
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+ .active_low = 1,
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+ },{
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+ .name = "rxd1", /* Green Led */
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+ .gpio = 120,
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+ .active_low = 1,
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+ },{
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+ .name = "rxd2", /* Yellow Led */
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+ .gpio = 121,
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+ .active_low = 1,
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+ },{
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+ .name = "ser1", /* Green Led */
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+ .gpio = 122,
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+ .active_low = 1,
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+ },{
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+ .name = "ser2", /* Yellow Led */
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+ .gpio = 123,
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+ .active_low = 1,
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+ },{
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+ .name = "enet1", /* Green Led */
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+ .gpio = 124,
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+ .active_low = 1,
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+ },{
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+ .name = "enet2", /* Yellow Led */
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+ .gpio = 125,
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+ .active_low = 1,
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+ },{
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+ .name = "sig1_1", /* Green Led */
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+ .gpio = 126,
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+ .active_low = 1,
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+ },{
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+ .name = "sig1_2", /* Yellow Led */
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+ .gpio = 127,
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+ .active_low = 1,
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+ },{
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+ .name = "sig2_1", /* Green Led */
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+ .gpio = 128,
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+ .active_low = 1,
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+ },{
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+ .name = "sig2_2", /* Yellow Led */
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+ .gpio = 129,
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+ .active_low = 1,
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+ },{
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+ .name = "sig3_1", /* Green Led */
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+ .gpio = 130,
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+ .active_low = 1,
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+ },{
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+ .name = "sig3_2", /* Yellow Led */
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+ .gpio = 131,
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+ .active_low = 1,
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+ },{
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+ .name = "net1", /*Green Led */
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+ .gpio = 109,
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+ .active_low = 1,
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+ },{
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+ .name = "net2", /* Red Led */
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+ .gpio = 110,
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+ .active_low = 1,
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+ },{
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+ .name = "mod1", /* Green Led */
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+ .gpio = 111,
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+ .active_low = 1,
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+ },{
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+ .name = "mod2", /* Red Led */
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+ .gpio = 112,
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+ .active_low = 1,
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+ },
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+};
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+
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+static struct gpio_led_platform_data laguna_gpio_leds_data = {
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+ .num_leds = 22,
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+ .leds = laguna_gpio_leds,
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+};
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+
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+static struct platform_device laguna_gpio_leds_device = {
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+ .name = "leds-gpio",
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+ .id = -1,
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+ .dev.platform_data = &laguna_gpio_leds_data,
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+};
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+
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+/*
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+ * Ethernet
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+ */
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+static struct cns3xxx_plat_info laguna_net_data = {
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+ .ports = 0,
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+ .phy = {
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+ 0,
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+ 1,
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+ 2,
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+ },
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+};
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+
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+static struct platform_device laguna_net_device = {
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+ .name = "cns3xxx_eth",
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+ .id = 0,
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+ .dev.platform_data = &laguna_net_data,
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+};
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+
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+/*
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+ * UART
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+ */
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+static void __init laguna_early_serial_setup(void)
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+{
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+#ifdef CONFIG_SERIAL_8250_CONSOLE
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+ static struct uart_port laguna_serial_port = {
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+ .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
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+ .mapbase = CNS3XXX_UART0_BASE,
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+ .irq = IRQ_CNS3XXX_UART0,
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+ .iotype = UPIO_MEM,
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+ .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
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+ .regshift = 2,
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+ .uartclk = 24000000,
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+ .line = 0,
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+ .type = PORT_16550A,
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+ .fifosize = 16,
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+ };
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+
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+ early_serial_setup(&laguna_serial_port);
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+#endif
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+}
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+
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+static struct resource laguna_uart_resources[] = {
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+ {
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+ .start = CNS3XXX_UART0_BASE,
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+ .end = CNS3XXX_UART0_BASE + SZ_4K - 1,
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+ .flags = IORESOURCE_MEM
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+ },{
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+ .start = CNS3XXX_UART2_BASE,
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+ .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
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+ .flags = IORESOURCE_MEM
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+ },{
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+ .start = CNS3XXX_UART2_BASE,
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+ .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
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+ .flags = IORESOURCE_MEM
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+ },
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+};
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+
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+static struct plat_serial8250_port laguna_uart_data[] = {
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+ {
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+ .membase = (char*) (CNS3XXX_UART0_BASE_VIRT),
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+ .mapbase = (CNS3XXX_UART0_BASE),
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+ .irq = IRQ_CNS3XXX_UART0,
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+ .iotype = UPIO_MEM,
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+ .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
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+ .regshift = 2,
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+ .uartclk = 24000000,
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+ .type = PORT_16550A,
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+ },{
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+ .membase = (char*) (CNS3XXX_UART1_BASE_VIRT),
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+ .mapbase = (CNS3XXX_UART1_BASE),
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+ .irq = IRQ_CNS3XXX_UART1,
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+ .iotype = UPIO_MEM,
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+ .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
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+ .regshift = 2,
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+ .uartclk = 24000000,
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+ .type = PORT_16550A,
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+ },{
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+ .membase = (char*) (CNS3XXX_UART2_BASE_VIRT),
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+ .mapbase = (CNS3XXX_UART2_BASE),
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+ .irq = IRQ_CNS3XXX_UART2,
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+ .iotype = UPIO_MEM,
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+ .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
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+ .regshift = 2,
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+ .uartclk = 24000000,
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+ .type = PORT_16550A,
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+ },
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+};
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+
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+static struct platform_device laguna_uart = {
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+ .name = "serial8250",
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+ .id = PLAT8250_DEV_PLATFORM,
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+ .dev.platform_data = laguna_uart_data,
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+ .num_resources = 3,
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+ .resource = laguna_uart_resources
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+};
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+
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+/*
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+ * USB
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+ */
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+static struct resource cns3xxx_usb_ehci_resources[] = {
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+ [0] = {
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+ .start = CNS3XXX_USB_BASE,
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+ .end = CNS3XXX_USB_BASE + SZ_16M - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ [1] = {
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+ .start = IRQ_CNS3XXX_USB_EHCI,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
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+
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+static struct platform_device cns3xxx_usb_ehci_device = {
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+ .name = "cns3xxx-ehci",
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+ .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
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+ .resource = cns3xxx_usb_ehci_resources,
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+ .dev = {
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+ .dma_mask = &cns3xxx_usb_ehci_dma_mask,
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+ .coherent_dma_mask = DMA_BIT_MASK(32),
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+ },
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+};
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+
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+static struct resource cns3xxx_usb_ohci_resources[] = {
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+ [0] = {
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+ .start = CNS3XXX_USB_OHCI_BASE,
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+ .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ [1] = {
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+ .start = IRQ_CNS3XXX_USB_OHCI,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
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+
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+static struct platform_device cns3xxx_usb_ohci_device = {
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+ .name = "cns3xxx-ohci",
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+ .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
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+ .resource = cns3xxx_usb_ohci_resources,
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+ .dev = {
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+ .dma_mask = &cns3xxx_usb_ohci_dma_mask,
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+ .coherent_dma_mask = DMA_BIT_MASK(32),
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+ },
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+};
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+
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+static struct resource cns3xxx_usb_otg_resources[] = {
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+ [0] = {
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+ .start = CNS3XXX_USBOTG_BASE,
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+ .end = CNS3XXX_USBOTG_BASE + SZ_16M - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+ [1] = {
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+ .start = IRQ_CNS3XXX_USB_OTG,
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+ .flags = IORESOURCE_IRQ,
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+ },
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+};
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+
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+static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32);
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+
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+static struct platform_device cns3xxx_usb_otg_device = {
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+ .name = "dwc_otg",
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+ .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources),
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+ .resource = cns3xxx_usb_otg_resources,
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+ .dev = {
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+ .dma_mask = &cns3xxx_usb_otg_dma_mask,
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+ .coherent_dma_mask = DMA_BIT_MASK(32),
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+ },
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+};
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+
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+/*
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+ * I2C
|
|
+ */
|
|
+static struct resource laguna_i2c_resource[] = {
|
|
+ {
|
|
+ .start = CNS3XXX_SSP_BASE + 0x20,
|
|
+ .end = 0x7100003f,
|
|
+ .flags = IORESOURCE_MEM,
|
|
+ },{
|
|
+ .start = IRQ_CNS3XXX_I2C,
|
|
+ .flags = IORESOURCE_IRQ,
|
|
+ },
|
|
+};
|
|
+
|
|
+static struct platform_device laguna_i2c_controller = {
|
|
+ .name = "cns3xxx-i2c",
|
|
+ .num_resources = 2,
|
|
+ .resource = laguna_i2c_resource,
|
|
+};
|
|
+
|
|
+static struct memory_accessor *at24_mem_acc;
|
|
+
|
|
+static void at24_setup(struct memory_accessor *mem_acc, void *context)
|
|
+{
|
|
+ char buf[8];
|
|
+
|
|
+ at24_mem_acc = mem_acc;
|
|
+
|
|
+ /* Read MAC addresses */
|
|
+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x100, 6) == 6)
|
|
+ memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN);
|
|
+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x106, 6) == 6)
|
|
+ memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN);
|
|
+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x10C, 6) == 6)
|
|
+ memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN);
|
|
+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x112, 6) == 6)
|
|
+ memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN);
|
|
+
|
|
+ /* Read out Model Information */
|
|
+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x130, 16) == 16)
|
|
+ memcpy(&laguna_info.model, buf, 16);
|
|
+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x140, 1) == 1)
|
|
+ memcpy(&laguna_info.nor_flash_size, buf, 1);
|
|
+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x141, 1) == 1)
|
|
+ memcpy(&laguna_info.spi_flash_size, buf, 1);
|
|
+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x142, 4) == 4)
|
|
+ memcpy(&laguna_info.config_bitmap, buf, 4);
|
|
+ if (at24_mem_acc->read(at24_mem_acc, buf, 0x146, 4) == 4)
|
|
+ memcpy(&laguna_info.config2_bitmap, buf, 4);
|
|
+};
|
|
+
|
|
+static struct at24_platform_data laguna_eeprom_info = {
|
|
+ .byte_len = 1024,
|
|
+ .page_size = 16,
|
|
+ .flags = AT24_FLAG_READONLY,
|
|
+ .setup = at24_setup,
|
|
+};
|
|
+
|
|
+static struct pca953x_platform_data laguna_pca_data = {
|
|
+ .gpio_base = 100,
|
|
+ .irq_base = -1,
|
|
+};
|
|
+
|
|
+static struct pca953x_platform_data laguna_pca2_data = {
|
|
+ .gpio_base = 116,
|
|
+ .irq_base = -1,
|
|
+};
|
|
+
|
|
+static struct i2c_board_info __initdata laguna_i2c_devices[] = {
|
|
+ {
|
|
+ I2C_BOARD_INFO("pca9555", 0x23),
|
|
+ .platform_data = &laguna_pca_data,
|
|
+ },{
|
|
+ I2C_BOARD_INFO("pca9555", 0x27),
|
|
+ .platform_data = &laguna_pca2_data,
|
|
+ },{
|
|
+ I2C_BOARD_INFO("gsp", 0x29),
|
|
+ },{
|
|
+ I2C_BOARD_INFO ("24c08",0x50),
|
|
+ .platform_data = &laguna_eeprom_info,
|
|
+ },{
|
|
+ I2C_BOARD_INFO("ds1672", 0x68),
|
|
+ },
|
|
+};
|
|
+
|
|
+/*
|
|
+ * Watchdog
|
|
+ */
|
|
+
|
|
+static struct resource laguna_watchdog_resource[] = {
|
|
+ {
|
|
+ .start = CNS3XXX_TC11MP_TWD_BASE,
|
|
+ .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
|
|
+ .flags = IORESOURCE_MEM,
|
|
+ },{
|
|
+ .start = IRQ_LOCALWDOG,
|
|
+ .end = IRQ_LOCALWDOG,
|
|
+ .flags = IORESOURCE_IRQ,
|
|
+ }
|
|
+};
|
|
+
|
|
+static struct platform_device laguna_watchdog = {
|
|
+ .name = "mpcore_wdt",
|
|
+ .id = -1,
|
|
+ .num_resources = ARRAY_SIZE(laguna_watchdog_resource),
|
|
+ .resource = laguna_watchdog_resource,
|
|
+};
|
|
+
|
|
+/*
|
|
+ * Initialization
|
|
+ */
|
|
+
|
|
+static void __init laguna_init(void)
|
|
+{
|
|
+ platform_device_register(&laguna_watchdog);
|
|
+
|
|
+ platform_device_register(&laguna_i2c_controller);
|
|
+
|
|
+ i2c_register_board_info(0, laguna_i2c_devices,
|
|
+ ARRAY_SIZE(laguna_i2c_devices));
|
|
+
|
|
+
|
|
+ pm_power_off = cns3xxx_power_off;
|
|
+}
|
|
+
|
|
+static struct map_desc laguna_io_desc[] __initdata = {
|
|
+ {
|
|
+ .virtual = CNS3XXX_UART0_BASE_VIRT,
|
|
+ .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
|
|
+ .length = SZ_4K,
|
|
+ .type = MT_DEVICE,
|
|
+ },{
|
|
+ .virtual = CNS3XXX_UART1_BASE_VIRT,
|
|
+ .pfn = __phys_to_pfn(CNS3XXX_UART1_BASE),
|
|
+ .length = SZ_4K,
|
|
+ .type = MT_DEVICE,
|
|
+ },{
|
|
+ .virtual = CNS3XXX_UART2_BASE_VIRT,
|
|
+ .pfn = __phys_to_pfn(CNS3XXX_UART2_BASE),
|
|
+ .length = SZ_4K,
|
|
+ .type = MT_DEVICE,
|
|
+ },
|
|
+};
|
|
+
|
|
+static void __init laguna_map_io(void)
|
|
+{
|
|
+ cns3xxx_map_io();
|
|
+ iotable_init(laguna_io_desc, ARRAY_SIZE(laguna_io_desc));
|
|
+
|
|
+ laguna_early_serial_setup();
|
|
+}
|
|
+
|
|
+
|
|
+static int __init laguna_model_setup(void)
|
|
+{
|
|
+ u32 __iomem *mem;
|
|
+ u32 reg;
|
|
+ u8 pcie_bitmap = 0;
|
|
+
|
|
+ printk("Running on Gateworks Laguna %s\n", laguna_info.model);
|
|
+
|
|
+ if (strncmp(laguna_info.model, "GW", 2) == 0) {
|
|
+ if (laguna_info.config_bitmap & ETH0_LOAD)
|
|
+ laguna_net_data.ports |= BIT(0);
|
|
+ if (laguna_info.config_bitmap & ETH1_LOAD)
|
|
+ laguna_net_data.ports |= BIT(1);
|
|
+ if (laguna_info.config_bitmap & ETH2_LOAD)
|
|
+ laguna_net_data.ports |= BIT(2);
|
|
+ if (laguna_net_data.ports)
|
|
+ platform_device_register(&laguna_net_device);
|
|
+
|
|
+ if ((laguna_info.config_bitmap & SATA0_LOAD) ||
|
|
+ (laguna_info.config_bitmap & SATA1_LOAD))
|
|
+ cns3xxx_ahci_init();
|
|
+
|
|
+ if (laguna_info.config_bitmap & (PCIE0_LOAD))
|
|
+ pcie_bitmap |= 0x1;
|
|
+
|
|
+ if (laguna_info.config_bitmap & (PCIE1_LOAD))
|
|
+ pcie_bitmap |= 0x2;
|
|
+
|
|
+ cns3xxx_pcie_init(pcie_bitmap);
|
|
+
|
|
+ if (laguna_info.config_bitmap & (USB0_LOAD)) {
|
|
+ cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
|
|
+
|
|
+ /* DRVVBUS pins share with GPIOA */
|
|
+ mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014);
|
|
+ reg = __raw_readl(mem);
|
|
+ reg |= 0x8;
|
|
+ __raw_writel(reg, mem);
|
|
+
|
|
+ /* Enable OTG */
|
|
+ mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808);
|
|
+ reg = __raw_readl(mem);
|
|
+ reg &= ~(1 << 10);
|
|
+ __raw_writel(reg, mem);
|
|
+
|
|
+ platform_device_register(&cns3xxx_usb_otg_device);
|
|
+ }
|
|
+
|
|
+ if (laguna_info.config_bitmap & (USB1_LOAD)) {
|
|
+ platform_device_register(&cns3xxx_usb_ehci_device);
|
|
+ platform_device_register(&cns3xxx_usb_ohci_device);
|
|
+ }
|
|
+
|
|
+ if (laguna_info.config_bitmap & (SD_LOAD))
|
|
+ cns3xxx_sdhci_init();
|
|
+
|
|
+ if (laguna_info.config_bitmap & (UART0_LOAD))
|
|
+ laguna_uart.num_resources = 1;
|
|
+ if (laguna_info.config_bitmap & (UART1_LOAD))
|
|
+ laguna_uart.num_resources = 2;
|
|
+ if (laguna_info.config_bitmap & (UART2_LOAD))
|
|
+ laguna_uart.num_resources = 3;
|
|
+ platform_device_register(&laguna_uart);
|
|
+
|
|
+ if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
|
|
+ switch (laguna_info.nor_flash_size) {
|
|
+ case 1:
|
|
+ laguna_nor_partitions[3].size = SZ_8M - SZ_256K - SZ_128K - SZ_2M;
|
|
+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_8M - 1;
|
|
+ break;
|
|
+ case 2:
|
|
+ laguna_nor_partitions[3].size = SZ_16M - SZ_256K - SZ_128K - SZ_2M;
|
|
+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_16M - 1;
|
|
+ break;
|
|
+ case 3:
|
|
+ laguna_nor_partitions[3].size = SZ_32M - SZ_256K - SZ_128K - SZ_2M;
|
|
+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_32M - 1;
|
|
+ break;
|
|
+ case 4:
|
|
+ laguna_nor_partitions[3].size = SZ_64M - SZ_256K - SZ_128K - SZ_2M;
|
|
+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_64M - 1;
|
|
+ break;
|
|
+ case 5:
|
|
+ laguna_nor_partitions[3].size = SZ_128M - SZ_256K - SZ_128K - SZ_2M;
|
|
+ laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_128M - 1;
|
|
+ break;
|
|
+ }
|
|
+ platform_device_register(&laguna_nor_pdev);
|
|
+ }
|
|
+
|
|
+ if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
|
|
+ switch (laguna_info.spi_flash_size) {
|
|
+ case 1:
|
|
+ laguna_spi_partitions[3].size = SZ_4M - SZ_2M;
|
|
+ break;
|
|
+ case 2:
|
|
+ laguna_spi_partitions[3].size = SZ_8M - SZ_2M;
|
|
+ break;
|
|
+ case 3:
|
|
+ laguna_spi_partitions[3].size = SZ_16M - SZ_2M;
|
|
+ break;
|
|
+ case 4:
|
|
+ laguna_spi_partitions[3].size = SZ_32M - SZ_2M;
|
|
+ break;
|
|
+ case 5:
|
|
+ laguna_spi_partitions[3].size = SZ_64M - SZ_2M;
|
|
+ break;
|
|
+ }
|
|
+ spi_register_board_info(laguna_spi_devices, ARRAY_SIZE(laguna_spi_devices));
|
|
+ }
|
|
+
|
|
+ if ((laguna_info.config_bitmap & SPI0_LOAD) ||
|
|
+ (laguna_info.config_bitmap & SPI1_LOAD))
|
|
+ platform_device_register(&laguna_spi_controller);
|
|
+
|
|
+ /*
|
|
+ * Do any model specific setup not known by the bitmap by matching
|
|
+ * the first 6 characters of the model name
|
|
+ */
|
|
+
|
|
+ if (strncmp(laguna_info.model, "GW2388", 6) == 0) {
|
|
+ laguna_gpio_leds_data.num_leds = 2;
|
|
+ } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) {
|
|
+ laguna_gpio_leds[0].gpio = 107;
|
|
+ laguna_gpio_leds[1].gpio = 106;
|
|
+ laguna_gpio_leds_data.num_leds = 2;
|
|
+ }
|
|
+ platform_device_register(&laguna_gpio_leds_device);
|
|
+ } else {
|
|
+ // Do some defaults here, not sure what yet
|
|
+ }
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+late_initcall(laguna_model_setup);
|
|
+
|
|
+MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
|
|
+ .boot_params = 0x00000100,
|
|
+ .map_io = laguna_map_io,
|
|
+ .init_irq = cns3xxx_init_irq,
|
|
+ .timer = &cns3xxx_timer,
|
|
+ .init_machine = laguna_init,
|
|
+MACHINE_END
|
|
--- a/arch/arm/mach-cns3xxx/Kconfig
|
|
+++ b/arch/arm/mach-cns3xxx/Kconfig
|
|
@@ -10,4 +10,13 @@ config MACH_CNS3420VB
|
|
This is a platform with an on-board ARM11 MPCore and has support
|
|
for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
|
|
|
|
+config MACH_GW2388
|
|
+ bool "Support for Gateworks Laguna Platform"
|
|
+ select MIGHT_HAVE_PCI
|
|
+ help
|
|
+ Include support for the Gateworks Laguna Platform
|
|
+
|
|
+ This is a platform with an on-board ARM11 MPCore and has support
|
|
+ for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, I2C, GIG, etc.
|
|
+
|
|
endmenu
|
|
--- a/arch/arm/mach-cns3xxx/core.c
|
|
+++ b/arch/arm/mach-cns3xxx/core.c
|
|
@@ -16,6 +16,7 @@
|
|
#include <asm/mach/time.h>
|
|
#include <asm/mach/irq.h>
|
|
#include <asm/hardware/gic.h>
|
|
+#include <asm/smp_twd.h>
|
|
#include <mach/cns3xxx.h>
|
|
#include "core.h"
|
|
|
|
@@ -60,11 +61,24 @@ static struct map_desc cns3xxx_io_desc[]
|
|
.pfn = __phys_to_pfn(CNS3XXX_PM_BASE),
|
|
.length = SZ_4K,
|
|
.type = MT_DEVICE,
|
|
+ }, {
|
|
+ .virtual = CNS3XXX_SWITCH_BASE_VIRT,
|
|
+ .pfn = __phys_to_pfn(CNS3XXX_SWITCH_BASE),
|
|
+ .length = SZ_4K,
|
|
+ .type = MT_DEVICE,
|
|
+ }, {
|
|
+ .virtual = CNS3XXX_SSP_BASE_VIRT,
|
|
+ .pfn = __phys_to_pfn(CNS3XXX_SSP_BASE),
|
|
+ .length = SZ_4K,
|
|
+ .type = MT_DEVICE,
|
|
},
|
|
};
|
|
|
|
void __init cns3xxx_map_io(void)
|
|
{
|
|
+#ifdef CONFIG_LOCAL_TIMERS
|
|
+ twd_base = (void __iomem *) CNS3XXX_TC11MP_TWD_BASE_VIRT;
|
|
+#endif
|
|
iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
|
|
}
|
|
|
|
--- a/arch/arm/Kconfig
|
|
+++ b/arch/arm/Kconfig
|
|
@@ -313,6 +313,7 @@ config ARCH_CLPS711X
|
|
config ARCH_CNS3XXX
|
|
bool "Cavium Networks CNS3XXX family"
|
|
select CPU_V6
|
|
+ select ARCH_WANT_OPTIONAL_GPIOLIB
|
|
select GENERIC_CLOCKEVENTS
|
|
select ARM_GIC
|
|
select MIGHT_HAVE_PCI
|
|
--- /dev/null
|
|
+++ b/arch/arm/mach-cns3xxx/include/mach/gpio.h
|
|
@@ -0,0 +1,98 @@
|
|
+/*
|
|
+ * arch/arm/mach-cns3xxx/include/mach/gpio.h
|
|
+ *
|
|
+ * CNS3xxx GPIO wrappers for arch-neutral GPIO calls
|
|
+ *
|
|
+ * Copyright 2011 Gateworks Corporation
|
|
+ * Chris Lang <clang@gateworks.com>
|
|
+ *
|
|
+ * Based on IXP implementation by Milan Svoboda <msvoboda@ra.rockwell.com>
|
|
+ * Based on PXA implementation by Philipp Zabel <philipp.zabel@gmail.com>
|
|
+ *
|
|
+ * This program is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License as published by
|
|
+ * the Free Software Foundation; either version 2 of the License, or
|
|
+ * (at your option) any later version.
|
|
+ *
|
|
+ * This program is distributed in the hope that it will be useful,
|
|
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
+ * GNU General Public License for more details.
|
|
+ *
|
|
+ * You should have received a copy of the GNU General Public License
|
|
+ * along with this program; if not, write to the Free Software
|
|
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
|
+ *
|
|
+ */
|
|
+
|
|
+#ifndef __ASM_ARCH_CNS3XXX_GPIO_H
|
|
+#define __ASM_ARCH_CNS3XXX_GPIO_H
|
|
+
|
|
+#include <linux/kernel.h>
|
|
+#include <linux/io.h>
|
|
+#include <mach/hardware.h>
|
|
+#include <asm-generic/gpio.h> /* cansleep wrappers */
|
|
+
|
|
+#define NR_BUILTIN_GPIO 64
|
|
+
|
|
+#define CNS3XXX_GPIO_IN 0x0
|
|
+#define CNS3XXX_GPIO_OUT 0x1
|
|
+
|
|
+#define CNS3XXX_GPIO_LO 0
|
|
+#define CNS3XXX_GPIO_HI 1
|
|
+
|
|
+#define CNS3XXX_GPIO_OUTPUT 0x00
|
|
+#define CNS3XXX_GPIO_INPUT 0x04
|
|
+#define CNS3XXX_GPIO_DIR 0x08
|
|
+#define CNS3XXX_GPIO_SET 0x10
|
|
+#define CNS3XXX_GPIO_CLEAR 0x14
|
|
+
|
|
+static inline void gpio_line_get(u8 line, int *value)
|
|
+{
|
|
+ if (line < 32)
|
|
+ *value = ((__raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_INPUT) >> line) & 0x1);
|
|
+ else
|
|
+ *value = ((__raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_INPUT) >> (line - 32)) & 0x1);
|
|
+}
|
|
+
|
|
+static inline void gpio_line_set(u8 line, int value)
|
|
+{
|
|
+ if (line < 32) {
|
|
+ if (value)
|
|
+ __raw_writel((1 << line), CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_SET);
|
|
+ else
|
|
+ __raw_writel((1 << line), CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_CLEAR);
|
|
+ } else {
|
|
+ if (value)
|
|
+ __raw_writel((1 << line), CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_SET);
|
|
+ else
|
|
+ __raw_writel((1 << line), CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_CLEAR);
|
|
+ }
|
|
+}
|
|
+
|
|
+static inline int gpio_get_value(unsigned gpio)
|
|
+{
|
|
+ if (gpio < NR_BUILTIN_GPIO)
|
|
+ {
|
|
+ int value;
|
|
+ gpio_line_get(gpio, &value);
|
|
+ return value;
|
|
+ }
|
|
+ else
|
|
+ return __gpio_get_value(gpio);
|
|
+}
|
|
+
|
|
+static inline void gpio_set_value(unsigned gpio, int value)
|
|
+{
|
|
+ if (gpio < NR_BUILTIN_GPIO)
|
|
+ gpio_line_set(gpio, value);
|
|
+ else
|
|
+ __gpio_set_value(gpio, value);
|
|
+}
|
|
+
|
|
+#define gpio_cansleep __gpio_cansleep
|
|
+
|
|
+extern int gpio_to_irq(int gpio);
|
|
+extern int irq_to_gpio(int gpio);
|
|
+
|
|
+#endif
|
|
--- a/arch/arm/mach-cns3xxx/Makefile
|
|
+++ b/arch/arm/mach-cns3xxx/Makefile
|
|
@@ -1,6 +1,7 @@
|
|
obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
|
|
obj-$(CONFIG_PCI) += pcie.o
|
|
obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
|
|
+obj-$(CONFIG_MACH_GW2388) += laguna.o
|
|
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
|
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
|
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
|
|
--- a/arch/arm/tools/mach-types
|
|
+++ b/arch/arm/tools/mach-types
|
|
@@ -438,6 +438,7 @@ icontrol MACH_ICONTROL ICONTROL 2624
|
|
qsd8x50a_st1_5 MACH_QSD8X50A_ST1_5 QSD8X50A_ST1_5 2627
|
|
mx23evk MACH_MX23EVK MX23EVK 2629
|
|
ap4evb MACH_AP4EVB AP4EVB 2630
|
|
+gw2388 MACH_GW2388 GW2388 2635
|
|
mityomapl138 MACH_MITYOMAPL138 MITYOMAPL138 2650
|
|
guruplug MACH_GURUPLUG GURUPLUG 2659
|
|
spear310 MACH_SPEAR310 SPEAR310 2660
|
|
--- a/arch/arm/mach-cns3xxx/pcie.c
|
|
+++ b/arch/arm/mach-cns3xxx/pcie.c
|
|
@@ -365,7 +365,7 @@ static int cns3xxx_pcie_abort_handler(un
|
|
return 0;
|
|
}
|
|
|
|
-static int __init cns3xxx_pcie_init(void)
|
|
+int cns3xxx_pcie_init(u8 bitmap)
|
|
{
|
|
int i;
|
|
|
|
@@ -373,6 +373,9 @@ static int __init cns3xxx_pcie_init(void
|
|
"imprecise external abort");
|
|
|
|
for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
|
|
+ if (!(bitmap & (1 << i)))
|
|
+ continue;
|
|
+
|
|
iotable_init(cns3xxx_pcie[i].cfg_bases,
|
|
ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
|
|
cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
|
|
@@ -384,4 +387,3 @@ static int __init cns3xxx_pcie_init(void
|
|
|
|
return 0;
|
|
}
|
|
-device_initcall(cns3xxx_pcie_init);
|
|
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
|
|
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
|
|
@@ -175,6 +175,8 @@ static void __init cns3420_init(void)
|
|
cns3xxx_ahci_init();
|
|
cns3xxx_sdhci_init();
|
|
|
|
+ cns3xxx_pcie_init(0x3);
|
|
+
|
|
pm_power_off = cns3xxx_power_off;
|
|
}
|
|
|
|
--- a/arch/arm/mach-cns3xxx/include/mach/platform.h
|
|
+++ b/arch/arm/mach-cns3xxx/include/mach/platform.h
|
|
@@ -22,5 +22,7 @@ struct cns3xxx_plat_info {
|
|
u32 phy[3];
|
|
};
|
|
|
|
+extern int cns3xxx_pcie_init(u8 bitmap);
|
|
+
|
|
#endif /* __ASM_ARCH_PLATFORM_H */
|
|
#endif
|