mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-22 08:04:36 +03:00
fd8ccf9c65
* backport 2.6.8 patches to .39 / .32.33 * remove lqtapi * bump tapi/dsl to .39 * migrate to new ltq_ style api * add amazon_se support git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27026 3c298f89-4303-0410-b956-a3cf2f4a3e73
77 lines
1.9 KiB
Diff
77 lines
1.9 KiB
Diff
--- a/arch/mips/Makefile
|
|
+++ b/arch/mips/Makefile
|
|
@@ -179,6 +179,16 @@
|
|
#
|
|
|
|
#
|
|
+# Lantiq
|
|
+#
|
|
+
|
|
+core-$(CONFIG_LANTIQ) += arch/mips/lantiq/
|
|
+cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq
|
|
+load-$(CONFIG_LANTIQ) = 0xffffffff80002000
|
|
+cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
|
|
+cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
|
|
+
|
|
+#
|
|
# Texas Instruments AR7
|
|
#
|
|
core-$(CONFIG_AR7) += arch/mips/ar7/
|
|
--- a/include/linux/compiler.h
|
|
+++ b/include/linux/compiler.h
|
|
@@ -144,6 +144,11 @@
|
|
# define barrier() __memory_barrier()
|
|
#endif
|
|
|
|
+/* Unreachable code */
|
|
+#ifndef unreachable
|
|
+# define unreachable() do { } while (1)
|
|
+#endif
|
|
+
|
|
#ifndef RELOC_HIDE
|
|
# define RELOC_HIDE(ptr, off) \
|
|
({ unsigned long __ptr; \
|
|
--- /dev/null
|
|
+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
|
|
@@ -0,0 +1,40 @@
|
|
+/*
|
|
+ * This program is free software; you can redistribute it and/or modify it
|
|
+ * under the terms of the GNU General Public License version 2 as published
|
|
+ * by the Free Software Foundation.
|
|
+ *
|
|
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
|
|
+ */
|
|
+
|
|
+#ifndef _LTQ_FALCON_H__
|
|
+#define _LTQ_FALCON_H__
|
|
+
|
|
+#ifdef CONFIG_SOC_FALCON
|
|
+
|
|
+#include <lantiq.h>
|
|
+
|
|
+/* Chip IDs */
|
|
+#define SOC_ID_FALCON 0x01B8
|
|
+
|
|
+/* SoC Types */
|
|
+#define SOC_TYPE_FALCON 0x01
|
|
+
|
|
+/* ASC0/1 - serial port */
|
|
+#define LTQ_ASC0_BASE_ADDR 0x1E100C00
|
|
+#define LTQ_ASC1_BASE_ADDR 0x1E100B00
|
|
+#define LTQ_ASC_SIZE 0x100
|
|
+
|
|
+#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8))
|
|
+#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1)
|
|
+#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2)
|
|
+
|
|
+/* ICU - interrupt control unit */
|
|
+#define LTQ_ICU_BASE_ADDR 0x1F880200
|
|
+#define LTQ_ICU_SIZE 0x100
|
|
+
|
|
+/* WDT */
|
|
+#define LTQ_WDT_BASE_ADDR 0x1F8803F0
|
|
+#define LTQ_WDT_SIZE 0x10
|
|
+
|
|
+#endif /* CONFIG_SOC_FALCON */
|
|
+#endif /* _LTQ_XWAY_H__ */
|