mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-22 02:58:58 +03:00
patch from Peter Wagner git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27104 3c298f89-4303-0410-b956-a3cf2f4a3e73
943 lines
24 KiB
Diff
943 lines
24 KiB
Diff
From 435de86088af82496bcba69165cd7422bb4622ec Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 6 May 2011 00:10:01 +0200
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Subject: [PATCH 11/13] MIPS: Lantiq: Add ethernet driver
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This patch adds the driver for the ETOP Packet Processing Engine (PPE32)
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found inside the XWAY family of Lantiq MIPS SoCs. This driver makes 100MBit
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ethernet work. Support for all 8 dma channels, gbit and the embedded switch
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found on the ar9/vr9 still needs to be implemented.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
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Cc: linux-mips@linux-mips.org
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Cc: netdev@vger.kernel.org
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Patchwork: https://patchwork.linux-mips.org/patch/2357/
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Acked-by: David S. Miller <davem@davemloft.net>
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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.../mips/include/asm/mach-lantiq/lantiq_platform.h | 7 +
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.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 4 +-
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arch/mips/lantiq/xway/devices.c | 23 +
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arch/mips/lantiq/xway/devices.h | 1 +
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drivers/net/Kconfig | 7 +
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drivers/net/Makefile | 1 +
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drivers/net/lantiq_etop.c | 805 ++++++++++++++++++++
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7 files changed, 846 insertions(+), 2 deletions(-)
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create mode 100644 drivers/net/lantiq_etop.c
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--- a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
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+++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h
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@@ -10,6 +10,7 @@
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#define _LANTIQ_PLATFORM_H__
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#include <linux/mtd/partitions.h>
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+#include <linux/socket.h>
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/* struct used to pass info to the pci core */
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enum {
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@@ -43,4 +44,10 @@ struct ltq_pci_data {
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int irq[16];
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};
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+/* struct used to pass info to network drivers */
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+struct ltq_eth_data {
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+ struct sockaddr mac;
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+ int mii_mode;
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+};
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+
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#endif
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--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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@@ -82,8 +82,8 @@
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#define PMU_SWITCH 0x10000000
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/* ETOP - ethernet */
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-#define LTQ_PPE32_BASE_ADDR 0xBE180000
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-#define LTQ_PPE32_SIZE 0x40000
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+#define LTQ_ETOP_BASE_ADDR 0x1E180000
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+#define LTQ_ETOP_SIZE 0x40000
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/* DMA */
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#define LTQ_DMA_BASE_ADDR 0x1E104100
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--- a/arch/mips/lantiq/xway/devices.c
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+++ b/arch/mips/lantiq/xway/devices.c
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@@ -96,3 +96,26 @@ void __init ltq_register_ase_asc(void)
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platform_device_register_simple("ltq_asc", 0,
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ltq_ase_asc_resources, ARRAY_SIZE(ltq_ase_asc_resources));
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}
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+
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+/* ethernet */
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+static struct resource ltq_etop_resources = {
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+ .name = "etop",
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+ .start = LTQ_ETOP_BASE_ADDR,
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+ .end = LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1,
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+ .flags = IORESOURCE_MEM,
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+};
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+
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+static struct platform_device ltq_etop = {
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+ .name = "ltq_etop",
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+ .resource = <q_etop_resources,
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+ .num_resources = 1,
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+};
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+
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+void __init
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+ltq_register_etop(struct ltq_eth_data *eth)
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+{
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+ if (eth) {
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+ ltq_etop.dev.platform_data = eth;
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+ platform_device_register(<q_etop);
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+ }
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+}
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--- a/arch/mips/lantiq/xway/devices.h
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+++ b/arch/mips/lantiq/xway/devices.h
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@@ -15,5 +15,6 @@
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extern void ltq_register_gpio(void);
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extern void ltq_register_gpio_stp(void);
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extern void ltq_register_ase_asc(void);
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+extern void ltq_register_etop(struct ltq_eth_data *eth);
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#endif
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--- a/drivers/net/Kconfig
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+++ b/drivers/net/Kconfig
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@@ -2017,6 +2017,13 @@ config FTMAC100
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from Faraday. It is used on Faraday A320, Andes AG101 and some
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other ARM/NDS32 SoC's.
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+config LANTIQ_ETOP
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+ tristate "Lantiq SoC ETOP driver"
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+ depends on SOC_TYPE_XWAY
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+ help
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+ Support for the MII0 inside the Lantiq SoC
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+
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+
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source "drivers/net/fs_enet/Kconfig"
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source "drivers/net/octeon/Kconfig"
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--- a/drivers/net/Makefile
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+++ b/drivers/net/Makefile
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@@ -259,6 +259,7 @@ obj-$(CONFIG_MLX4_CORE) += mlx4/
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obj-$(CONFIG_ENC28J60) += enc28j60.o
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obj-$(CONFIG_ETHOC) += ethoc.o
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obj-$(CONFIG_GRETH) += greth.o
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+obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o
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obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o
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--- /dev/null
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+++ b/drivers/net/lantiq_etop.c
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@@ -0,0 +1,813 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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+ *
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+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/slab.h>
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+#include <linux/errno.h>
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+#include <linux/types.h>
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+#include <linux/interrupt.h>
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+#include <linux/uaccess.h>
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+#include <linux/in.h>
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+#include <linux/netdevice.h>
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+#include <linux/etherdevice.h>
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+#include <linux/phy.h>
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+#include <linux/ip.h>
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+#include <linux/tcp.h>
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+#include <linux/skbuff.h>
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+#include <linux/mm.h>
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+#include <linux/platform_device.h>
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+#include <linux/ethtool.h>
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+#include <linux/init.h>
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+#include <linux/delay.h>
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+#include <linux/io.h>
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+
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+#include <asm/checksum.h>
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+
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+#include <lantiq_soc.h>
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+#include <xway_dma.h>
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+#include <lantiq_platform.h>
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+
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+#define LTQ_ETOP_MDIO 0x11804
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+#define MDIO_REQUEST 0x80000000
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+#define MDIO_READ 0x40000000
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+#define MDIO_ADDR_MASK 0x1f
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+#define MDIO_ADDR_OFFSET 0x15
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+#define MDIO_REG_MASK 0x1f
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+#define MDIO_REG_OFFSET 0x10
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+#define MDIO_VAL_MASK 0xffff
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+
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+#define PPE32_CGEN 0x800
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+#define LTQ_PPE32_ENET_MAC_CFG 0x1840
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+
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+#define LTQ_ETOP_ENETS0 0x11850
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+#define LTQ_ETOP_MAC_DA0 0x1186C
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+#define LTQ_ETOP_MAC_DA1 0x11870
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+#define LTQ_ETOP_CFG 0x16020
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+#define LTQ_ETOP_IGPLEN 0x16080
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+
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+#define MAX_DMA_CHAN 0x8
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+#define MAX_DMA_CRC_LEN 0x4
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+#define MAX_DMA_DATA_LEN 0x600
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+
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+#define ETOP_FTCU BIT(28)
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+#define ETOP_MII_MASK 0xf
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+#define ETOP_MII_NORMAL 0xd
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+#define ETOP_MII_REVERSE 0xe
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+#define ETOP_PLEN_UNDER 0x40
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+#define ETOP_CGEN 0x800
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+
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+/* use 2 static channels for TX/RX */
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+#define LTQ_ETOP_TX_CHANNEL 1
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+#define LTQ_ETOP_RX_CHANNEL 6
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+#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
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+#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
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+
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+#define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
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+#define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
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+#define ltq_etop_w32_mask(x, y, z) \
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+ ltq_w32_mask(x, y, ltq_etop_membase + (z))
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+
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+#define DRV_VERSION "1.0"
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+
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+#ifndef netdev_err
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+#define netdev_err(a, b, ...) printk(b, ##__VA_ARGS__)
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+#endif
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+
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+#ifndef pr_warn
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+#define pr_warn pr_warning
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+#endif
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+
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+static void __iomem *ltq_etop_membase;
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+
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+struct ltq_etop_chan {
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+ int idx;
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+ int tx_free;
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+ struct net_device *netdev;
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+ struct napi_struct napi;
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+ struct ltq_dma_channel dma;
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+ struct sk_buff *skb[LTQ_DESC_NUM];
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+};
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+
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+struct ltq_etop_priv {
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+ struct net_device *netdev;
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+ struct ltq_eth_data *pldata;
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+ struct resource *res;
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+
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+ struct mii_bus *mii_bus;
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+ struct phy_device *phydev;
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+
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+ struct ltq_etop_chan ch[MAX_DMA_CHAN];
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+ int tx_free[MAX_DMA_CHAN >> 1];
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+
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+ spinlock_t lock;
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+};
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+
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+static int
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+ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
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+{
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+ ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
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+ if (!ch->skb[ch->dma.desc])
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+ return -ENOMEM;
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+ ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
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+ ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN,
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+ DMA_FROM_DEVICE);
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+ ch->dma.desc_base[ch->dma.desc].addr =
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+ CPHYSADDR(ch->skb[ch->dma.desc]->data);
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+ ch->dma.desc_base[ch->dma.desc].ctl =
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+ LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
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+ MAX_DMA_DATA_LEN;
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+ skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
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+ return 0;
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+}
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+
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+static void
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+ltq_etop_hw_receive(struct ltq_etop_chan *ch)
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+{
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+ struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
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+ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
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+ struct sk_buff *skb = ch->skb[ch->dma.desc];
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+ int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN;
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&priv->lock, flags);
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+ if (ltq_etop_alloc_skb(ch)) {
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+ netdev_err(ch->netdev,
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+ "failed to allocate new rx buffer, stopping DMA\n");
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+ ltq_dma_close(&ch->dma);
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+ }
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+ ch->dma.desc++;
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+ ch->dma.desc %= LTQ_DESC_NUM;
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+ spin_unlock_irqrestore(&priv->lock, flags);
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+
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+ skb_put(skb, len);
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+ skb->dev = ch->netdev;
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+ skb->protocol = eth_type_trans(skb, ch->netdev);
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+ netif_receive_skb(skb);
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+}
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+
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+static int
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+ltq_etop_poll_rx(struct napi_struct *napi, int budget)
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+{
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+ struct ltq_etop_chan *ch = container_of(napi,
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+ struct ltq_etop_chan, napi);
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+ int rx = 0;
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+ int complete = 0;
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+
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+ while ((rx < budget) && !complete) {
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+ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
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+
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+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
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+ ltq_etop_hw_receive(ch);
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+ rx++;
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+ } else {
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+ complete = 1;
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+ }
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+ }
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+ if (complete || !rx) {
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+ napi_complete(&ch->napi);
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+ ltq_dma_ack_irq(&ch->dma);
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+ }
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+ return rx;
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+}
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+
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+static int
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+ltq_etop_poll_tx(struct napi_struct *napi, int budget)
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+{
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+ struct ltq_etop_chan *ch =
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+ container_of(napi, struct ltq_etop_chan, napi);
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+ struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
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+ struct netdev_queue *txq =
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+ netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&priv->lock, flags);
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+ while ((ch->dma.desc_base[ch->tx_free].ctl &
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+ (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
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+ dev_kfree_skb_any(ch->skb[ch->tx_free]);
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+ ch->skb[ch->tx_free] = NULL;
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+ memset(&ch->dma.desc_base[ch->tx_free], 0,
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+ sizeof(struct ltq_dma_desc));
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+ ch->tx_free++;
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+ ch->tx_free %= LTQ_DESC_NUM;
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+ }
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+ spin_unlock_irqrestore(&priv->lock, flags);
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+
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+ if (netif_tx_queue_stopped(txq))
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+ netif_tx_start_queue(txq);
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+ napi_complete(&ch->napi);
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+ ltq_dma_ack_irq(&ch->dma);
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+ return 1;
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+}
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+
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+static irqreturn_t
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+ltq_etop_dma_irq(int irq, void *_priv)
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+{
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+ struct ltq_etop_priv *priv = _priv;
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+ int ch = irq - LTQ_DMA_CH0_INT;
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+
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+ napi_schedule(&priv->ch[ch].napi);
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+ return IRQ_HANDLED;
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+}
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+
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+static void
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+ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
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+{
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+ struct ltq_etop_priv *priv = netdev_priv(dev);
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+
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+ ltq_dma_free(&ch->dma);
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+ if (ch->dma.irq)
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+ free_irq(ch->dma.irq, priv);
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+ if (IS_RX(ch->idx)) {
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+ int desc;
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+ for (desc = 0; desc < LTQ_DESC_NUM; desc++)
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+ dev_kfree_skb_any(ch->skb[ch->dma.desc]);
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+ }
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+}
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+
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+static void
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+ltq_etop_hw_exit(struct net_device *dev)
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+{
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+ struct ltq_etop_priv *priv = netdev_priv(dev);
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+ int i;
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+
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+ ltq_pmu_disable(PMU_PPE);
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+ for (i = 0; i < MAX_DMA_CHAN; i++)
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+ if (IS_TX(i) || IS_RX(i))
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+ ltq_etop_free_channel(dev, &priv->ch[i]);
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+}
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+
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+static int
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+ltq_etop_hw_init(struct net_device *dev)
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+{
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+ struct ltq_etop_priv *priv = netdev_priv(dev);
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+ int i;
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+
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+ ltq_pmu_enable(PMU_PPE);
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+
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+ switch (priv->pldata->mii_mode) {
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+ case PHY_INTERFACE_MODE_RMII:
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+ ltq_etop_w32_mask(ETOP_MII_MASK,
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+ ETOP_MII_REVERSE, LTQ_ETOP_CFG);
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+ break;
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+
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+ case PHY_INTERFACE_MODE_MII:
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+ ltq_etop_w32_mask(ETOP_MII_MASK,
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+ ETOP_MII_NORMAL, LTQ_ETOP_CFG);
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+ break;
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+
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+ default:
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+ netdev_err(dev, "unknown mii mode %d\n",
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+ priv->pldata->mii_mode);
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+ return -ENOTSUPP;
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+ }
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+
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+ /* enable crc generation */
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+ ltq_etop_w32(PPE32_CGEN, LTQ_PPE32_ENET_MAC_CFG);
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+
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+ ltq_dma_init_port(DMA_PORT_ETOP);
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+
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+ for (i = 0; i < MAX_DMA_CHAN; i++) {
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+ int irq = LTQ_DMA_CH0_INT + i;
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+ struct ltq_etop_chan *ch = &priv->ch[i];
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+
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+ ch->idx = ch->dma.nr = i;
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+
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+ if (IS_TX(i)) {
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+ ltq_dma_alloc_tx(&ch->dma);
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+ request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
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+ "etop_tx", priv);
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+ } else if (IS_RX(i)) {
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+ ltq_dma_alloc_rx(&ch->dma);
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+ for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
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+ ch->dma.desc++)
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+ if (ltq_etop_alloc_skb(ch))
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+ return -ENOMEM;
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+ ch->dma.desc = 0;
|
|
+ request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
|
|
+ "etop_rx", priv);
|
|
+ }
|
|
+ ch->dma.irq = irq;
|
|
+ }
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void
|
|
+ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
|
|
+{
|
|
+ strcpy(info->driver, "Lantiq ETOP");
|
|
+ strcpy(info->bus_info, "internal");
|
|
+ strcpy(info->version, DRV_VERSION);
|
|
+}
|
|
+
|
|
+static int
|
|
+ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
|
|
+{
|
|
+ struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
+
|
|
+ return phy_ethtool_gset(priv->phydev, cmd);
|
|
+}
|
|
+
|
|
+static int
|
|
+ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
|
|
+{
|
|
+ struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
+
|
|
+ return phy_ethtool_sset(priv->phydev, cmd);
|
|
+}
|
|
+
|
|
+static int
|
|
+ltq_etop_nway_reset(struct net_device *dev)
|
|
+{
|
|
+ struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
+
|
|
+ return phy_start_aneg(priv->phydev);
|
|
+}
|
|
+
|
|
+static const struct ethtool_ops ltq_etop_ethtool_ops = {
|
|
+ .get_drvinfo = ltq_etop_get_drvinfo,
|
|
+ .get_settings = ltq_etop_get_settings,
|
|
+ .set_settings = ltq_etop_set_settings,
|
|
+ .nway_reset = ltq_etop_nway_reset,
|
|
+};
|
|
+
|
|
+static int
|
|
+ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
|
|
+{
|
|
+ u32 val = MDIO_REQUEST |
|
|
+ ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
|
|
+ ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
|
|
+ phy_data;
|
|
+
|
|
+ while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
|
|
+ ;
|
|
+ ltq_etop_w32(val, LTQ_ETOP_MDIO);
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int
|
|
+ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg)
|
|
+{
|
|
+ u32 val = MDIO_REQUEST | MDIO_READ |
|
|
+ ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
|
|
+ ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
|
|
+
|
|
+ while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
|
|
+ ;
|
|
+ ltq_etop_w32(val, LTQ_ETOP_MDIO);
|
|
+ while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
|
|
+ ;
|
|
+ val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
|
|
+ return val;
|
|
+}
|
|
+
|
|
+static void
|
|
+ltq_etop_mdio_link(struct net_device *dev)
|
|
+{
|
|
+ /* nothing to do */
|
|
+}
|
|
+
|
|
+static int
|
|
+ltq_etop_mdio_probe(struct net_device *dev)
|
|
+{
|
|
+ struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
+ struct phy_device *phydev = NULL;
|
|
+ int phy_addr;
|
|
+
|
|
+ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
|
|
+ if (priv->mii_bus->phy_map[phy_addr]) {
|
|
+ phydev = priv->mii_bus->phy_map[phy_addr];
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ if (!phydev) {
|
|
+ netdev_err(dev, "no PHY found\n");
|
|
+ return -ENODEV;
|
|
+ }
|
|
+
|
|
+ phydev = phy_connect(dev, dev_name(&phydev->dev), <q_etop_mdio_link,
|
|
+ 0, priv->pldata->mii_mode);
|
|
+
|
|
+ if (IS_ERR(phydev)) {
|
|
+ netdev_err(dev, "Could not attach to PHY\n");
|
|
+ return PTR_ERR(phydev);
|
|
+ }
|
|
+
|
|
+ phydev->supported &= (SUPPORTED_10baseT_Half
|
|
+ | SUPPORTED_10baseT_Full
|
|
+ | SUPPORTED_100baseT_Half
|
|
+ | SUPPORTED_100baseT_Full
|
|
+ | SUPPORTED_Autoneg
|
|
+ | SUPPORTED_MII
|
|
+ | SUPPORTED_TP);
|
|
+
|
|
+ phydev->advertising = phydev->supported;
|
|
+ priv->phydev = phydev;
|
|
+ pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
|
|
+ dev->name, phydev->drv->name,
|
|
+ dev_name(&phydev->dev), phydev->irq);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int
|
|
+ltq_etop_mdio_init(struct net_device *dev)
|
|
+{
|
|
+ struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
+ int i;
|
|
+ int err;
|
|
+
|
|
+ priv->mii_bus = mdiobus_alloc();
|
|
+ if (!priv->mii_bus) {
|
|
+ netdev_err(dev, "failed to allocate mii bus\n");
|
|
+ err = -ENOMEM;
|
|
+ goto err_out;
|
|
+ }
|
|
+
|
|
+ priv->mii_bus->priv = dev;
|
|
+ priv->mii_bus->read = ltq_etop_mdio_rd;
|
|
+ priv->mii_bus->write = ltq_etop_mdio_wr;
|
|
+ priv->mii_bus->name = "ltq_mii";
|
|
+ snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
|
|
+ priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
|
|
+ if (!priv->mii_bus->irq) {
|
|
+ err = -ENOMEM;
|
|
+ goto err_out_free_mdiobus;
|
|
+ }
|
|
+
|
|
+ for (i = 0; i < PHY_MAX_ADDR; ++i)
|
|
+ priv->mii_bus->irq[i] = PHY_POLL;
|
|
+
|
|
+ if (mdiobus_register(priv->mii_bus)) {
|
|
+ err = -ENXIO;
|
|
+ goto err_out_free_mdio_irq;
|
|
+ }
|
|
+
|
|
+ if (ltq_etop_mdio_probe(dev)) {
|
|
+ err = -ENXIO;
|
|
+ goto err_out_unregister_bus;
|
|
+ }
|
|
+ return 0;
|
|
+
|
|
+err_out_unregister_bus:
|
|
+ mdiobus_unregister(priv->mii_bus);
|
|
+err_out_free_mdio_irq:
|
|
+ kfree(priv->mii_bus->irq);
|
|
+err_out_free_mdiobus:
|
|
+ mdiobus_free(priv->mii_bus);
|
|
+err_out:
|
|
+ return err;
|
|
+}
|
|
+
|
|
+static void
|
|
+ltq_etop_mdio_cleanup(struct net_device *dev)
|
|
+{
|
|
+ struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
+
|
|
+ phy_disconnect(priv->phydev);
|
|
+ mdiobus_unregister(priv->mii_bus);
|
|
+ kfree(priv->mii_bus->irq);
|
|
+ mdiobus_free(priv->mii_bus);
|
|
+}
|
|
+
|
|
+static int
|
|
+ltq_etop_open(struct net_device *dev)
|
|
+{
|
|
+ struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
+ int i;
|
|
+
|
|
+ for (i = 0; i < MAX_DMA_CHAN; i++) {
|
|
+ struct ltq_etop_chan *ch = &priv->ch[i];
|
|
+
|
|
+ if (!IS_TX(i) && (!IS_RX(i)))
|
|
+ continue;
|
|
+ ltq_dma_open(&ch->dma);
|
|
+ napi_enable(&ch->napi);
|
|
+ }
|
|
+ phy_start(priv->phydev);
|
|
+ netif_tx_start_all_queues(dev);
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int
|
|
+ltq_etop_stop(struct net_device *dev)
|
|
+{
|
|
+ struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
+ int i;
|
|
+
|
|
+ netif_tx_stop_all_queues(dev);
|
|
+ phy_stop(priv->phydev);
|
|
+ for (i = 0; i < MAX_DMA_CHAN; i++) {
|
|
+ struct ltq_etop_chan *ch = &priv->ch[i];
|
|
+
|
|
+ if (!IS_RX(i) && !IS_TX(i))
|
|
+ continue;
|
|
+ napi_disable(&ch->napi);
|
|
+ ltq_dma_close(&ch->dma);
|
|
+ }
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int
|
|
+ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
|
|
+{
|
|
+ int queue = skb_get_queue_mapping(skb);
|
|
+ struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
|
|
+ struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
+ struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
|
|
+ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
|
|
+ int len;
|
|
+ unsigned long flags;
|
|
+ u32 byte_offset;
|
|
+
|
|
+ len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
|
|
+
|
|
+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
|
|
+ dev_kfree_skb_any(skb);
|
|
+ netdev_err(dev, "tx ring full\n");
|
|
+ netif_tx_stop_queue(txq);
|
|
+ return NETDEV_TX_BUSY;
|
|
+ }
|
|
+
|
|
+ /* dma needs to start on a 16 byte aligned address */
|
|
+ byte_offset = CPHYSADDR(skb->data) % 16;
|
|
+ ch->skb[ch->dma.desc] = skb;
|
|
+
|
|
+ dev->trans_start = jiffies;
|
|
+
|
|
+ spin_lock_irqsave(&priv->lock, flags);
|
|
+ desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
|
|
+ DMA_TO_DEVICE)) - byte_offset;
|
|
+ wmb();
|
|
+ desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
|
|
+ LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
|
|
+ ch->dma.desc++;
|
|
+ ch->dma.desc %= LTQ_DESC_NUM;
|
|
+ spin_unlock_irqrestore(&priv->lock, flags);
|
|
+
|
|
+ if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
|
|
+ netif_tx_stop_queue(txq);
|
|
+
|
|
+ return NETDEV_TX_OK;
|
|
+}
|
|
+
|
|
+static int
|
|
+ltq_etop_change_mtu(struct net_device *dev, int new_mtu)
|
|
+{
|
|
+ int ret = eth_change_mtu(dev, new_mtu);
|
|
+
|
|
+ if (!ret) {
|
|
+ struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
+ unsigned long flags;
|
|
+
|
|
+ spin_lock_irqsave(&priv->lock, flags);
|
|
+ ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu,
|
|
+ LTQ_ETOP_IGPLEN);
|
|
+ spin_unlock_irqrestore(&priv->lock, flags);
|
|
+ }
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static int
|
|
+ltq_etop_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
|
|
+{
|
|
+ struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
+
|
|
+ /* TODO: mii-toll reports "No MII transceiver present!." ?!*/
|
|
+ return phy_mii_ioctl(priv->phydev, rq, cmd);
|
|
+}
|
|
+
|
|
+static int
|
|
+ltq_etop_set_mac_address(struct net_device *dev, void *p)
|
|
+{
|
|
+ int ret = eth_mac_addr(dev, p);
|
|
+
|
|
+ if (!ret) {
|
|
+ struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
+ unsigned long flags;
|
|
+
|
|
+ /* store the mac for the unicast filter */
|
|
+ spin_lock_irqsave(&priv->lock, flags);
|
|
+ ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0);
|
|
+ ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16,
|
|
+ LTQ_ETOP_MAC_DA1);
|
|
+ spin_unlock_irqrestore(&priv->lock, flags);
|
|
+ }
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static void
|
|
+ltq_etop_set_multicast_list(struct net_device *dev)
|
|
+{
|
|
+ struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
+ unsigned long flags;
|
|
+
|
|
+ /* ensure that the unicast filter is not enabled in promiscious mode */
|
|
+ spin_lock_irqsave(&priv->lock, flags);
|
|
+ if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI))
|
|
+ ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0);
|
|
+ else
|
|
+ ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0);
|
|
+ spin_unlock_irqrestore(&priv->lock, flags);
|
|
+}
|
|
+
|
|
+static u16
|
|
+ltq_etop_select_queue(struct net_device *dev, struct sk_buff *skb)
|
|
+{
|
|
+ /* we are currently only using the first queue */
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int
|
|
+ltq_etop_init(struct net_device *dev)
|
|
+{
|
|
+ struct ltq_etop_priv *priv = netdev_priv(dev);
|
|
+ struct sockaddr mac;
|
|
+ int err;
|
|
+
|
|
+ ether_setup(dev);
|
|
+ dev->watchdog_timeo = 10 * HZ;
|
|
+ err = ltq_etop_hw_init(dev);
|
|
+ if (err)
|
|
+ goto err_hw;
|
|
+ ltq_etop_change_mtu(dev, 1500);
|
|
+
|
|
+ memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
|
|
+ if (!is_valid_ether_addr(mac.sa_data)) {
|
|
+ pr_warn("etop: invalid MAC, using random\n");
|
|
+ random_ether_addr(mac.sa_data);
|
|
+ }
|
|
+
|
|
+ err = ltq_etop_set_mac_address(dev, &mac);
|
|
+ if (err)
|
|
+ goto err_netdev;
|
|
+ ltq_etop_set_multicast_list(dev);
|
|
+ err = ltq_etop_mdio_init(dev);
|
|
+ if (err)
|
|
+ goto err_netdev;
|
|
+ return 0;
|
|
+
|
|
+err_netdev:
|
|
+ unregister_netdev(dev);
|
|
+ free_netdev(dev);
|
|
+err_hw:
|
|
+ ltq_etop_hw_exit(dev);
|
|
+ return err;
|
|
+}
|
|
+
|
|
+static void
|
|
+ltq_etop_tx_timeout(struct net_device *dev)
|
|
+{
|
|
+ int err;
|
|
+
|
|
+ ltq_etop_hw_exit(dev);
|
|
+ err = ltq_etop_hw_init(dev);
|
|
+ if (err)
|
|
+ goto err_hw;
|
|
+ dev->trans_start = jiffies;
|
|
+ netif_wake_queue(dev);
|
|
+ return;
|
|
+
|
|
+err_hw:
|
|
+ ltq_etop_hw_exit(dev);
|
|
+ netdev_err(dev, "failed to restart etop after TX timeout\n");
|
|
+}
|
|
+
|
|
+static const struct net_device_ops ltq_eth_netdev_ops = {
|
|
+ .ndo_open = ltq_etop_open,
|
|
+ .ndo_stop = ltq_etop_stop,
|
|
+ .ndo_start_xmit = ltq_etop_tx,
|
|
+ .ndo_change_mtu = ltq_etop_change_mtu,
|
|
+ .ndo_do_ioctl = ltq_etop_ioctl,
|
|
+ .ndo_set_mac_address = ltq_etop_set_mac_address,
|
|
+ .ndo_validate_addr = eth_validate_addr,
|
|
+ .ndo_set_multicast_list = ltq_etop_set_multicast_list,
|
|
+ .ndo_select_queue = ltq_etop_select_queue,
|
|
+ .ndo_init = ltq_etop_init,
|
|
+ .ndo_tx_timeout = ltq_etop_tx_timeout,
|
|
+};
|
|
+
|
|
+static int __init
|
|
+ltq_etop_probe(struct platform_device *pdev)
|
|
+{
|
|
+ struct net_device *dev;
|
|
+ struct ltq_etop_priv *priv;
|
|
+ struct resource *res;
|
|
+ int err;
|
|
+ int i;
|
|
+
|
|
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
+ if (!res) {
|
|
+ dev_err(&pdev->dev, "failed to get etop resource\n");
|
|
+ err = -ENOENT;
|
|
+ goto err_out;
|
|
+ }
|
|
+
|
|
+ res = devm_request_mem_region(&pdev->dev, res->start,
|
|
+ resource_size(res), dev_name(&pdev->dev));
|
|
+ if (!res) {
|
|
+ dev_err(&pdev->dev, "failed to request etop resource\n");
|
|
+ err = -EBUSY;
|
|
+ goto err_out;
|
|
+ }
|
|
+
|
|
+ ltq_etop_membase = devm_ioremap_nocache(&pdev->dev,
|
|
+ res->start, resource_size(res));
|
|
+ if (!ltq_etop_membase) {
|
|
+ dev_err(&pdev->dev, "failed to remap etop engine %d\n",
|
|
+ pdev->id);
|
|
+ err = -ENOMEM;
|
|
+ goto err_out;
|
|
+ }
|
|
+
|
|
+ dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
|
|
+ strcpy(dev->name, "eth%d");
|
|
+ dev->netdev_ops = <q_eth_netdev_ops;
|
|
+ dev->ethtool_ops = <q_etop_ethtool_ops;
|
|
+ priv = netdev_priv(dev);
|
|
+ priv->res = res;
|
|
+ priv->pldata = dev_get_platdata(&pdev->dev);
|
|
+ priv->netdev = dev;
|
|
+ spin_lock_init(&priv->lock);
|
|
+
|
|
+ for (i = 0; i < MAX_DMA_CHAN; i++) {
|
|
+ if (IS_TX(i))
|
|
+ netif_napi_add(dev, &priv->ch[i].napi,
|
|
+ ltq_etop_poll_tx, 8);
|
|
+ else if (IS_RX(i))
|
|
+ netif_napi_add(dev, &priv->ch[i].napi,
|
|
+ ltq_etop_poll_rx, 32);
|
|
+ priv->ch[i].netdev = dev;
|
|
+ }
|
|
+
|
|
+ err = register_netdev(dev);
|
|
+ if (err)
|
|
+ goto err_free;
|
|
+
|
|
+ platform_set_drvdata(pdev, dev);
|
|
+ return 0;
|
|
+
|
|
+err_free:
|
|
+ kfree(dev);
|
|
+err_out:
|
|
+ return err;
|
|
+}
|
|
+
|
|
+static int __devexit
|
|
+ltq_etop_remove(struct platform_device *pdev)
|
|
+{
|
|
+ struct net_device *dev = platform_get_drvdata(pdev);
|
|
+
|
|
+ if (dev) {
|
|
+ netif_tx_stop_all_queues(dev);
|
|
+ ltq_etop_hw_exit(dev);
|
|
+ ltq_etop_mdio_cleanup(dev);
|
|
+ unregister_netdev(dev);
|
|
+ }
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static struct platform_driver ltq_mii_driver = {
|
|
+ .remove = __devexit_p(ltq_etop_remove),
|
|
+ .driver = {
|
|
+ .name = "ltq_etop",
|
|
+ .owner = THIS_MODULE,
|
|
+ },
|
|
+};
|
|
+
|
|
+int __init
|
|
+init_ltq_etop(void)
|
|
+{
|
|
+ int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe);
|
|
+
|
|
+ if (ret)
|
|
+ pr_err("ltq_etop: Error registering platfom driver!");
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static void __exit
|
|
+exit_ltq_etop(void)
|
|
+{
|
|
+ platform_driver_unregister(<q_mii_driver);
|
|
+}
|
|
+
|
|
+module_init(init_ltq_etop);
|
|
+module_exit(exit_ltq_etop);
|
|
+
|
|
+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
|
|
+MODULE_DESCRIPTION("Lantiq SoC ETOP");
|
|
+MODULE_LICENSE("GPL");
|