mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-08-22 01:23:40 +03:00
e056550af0
patch from Peter Wagner git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27104 3c298f89-4303-0410-b956-a3cf2f4a3e73
498 lines
12 KiB
Diff
498 lines
12 KiB
Diff
--- a/drivers/spi/Makefile
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+++ b/drivers/spi/Makefile
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@@ -55,6 +55,7 @@ obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.
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obj-$(CONFIG_SPI_SH_MSIOF) += spi_sh_msiof.o
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obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o
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obj-$(CONFIG_SPI_NUC900) += spi_nuc900.o
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+obj-$(CONFIG_SPI_FALCON) += spi_falcon.o
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# special build for s3c24xx spi driver with fiq support
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spi_s3c24xx_hw-y := spi_s3c24xx.o
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--- /dev/null
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+++ b/drivers/spi/spi_falcon.c
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@@ -0,0 +1,471 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/device.h>
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+#include <linux/platform_device.h>
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+#include <linux/spi/spi.h>
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+#include <linux/delay.h>
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+#include <linux/workqueue.h>
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+
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+#include <lantiq.h> /* ebu_lock */
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+#include <falcon/ebu_reg.h>
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+#include <falcon/sys1_reg.h>
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+
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+#define DRV_NAME "falcon_spi"
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+
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+#define FALCON_SPI_XFER_BEGIN (1 << 0)
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+#define FALCON_SPI_XFER_END (1 << 1)
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+
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+/* mapping for access macros */
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+#define reg_r32(reg) __raw_readl(reg)
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+#define reg_w32(val, reg) __raw_writel(val, reg)
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+#define reg_w32_mask(clear, set, reg) reg_w32((reg_r32(reg) \
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+ & ~(clear)) | (set), reg)
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+#define reg_r32_table(reg, idx) reg_r32(&((uint32_t *)®)[idx])
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+#define reg_w32_table(val, reg, idx) reg_w32(val, &((uint32_t *)®)[idx])
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+
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+#define ebu (priv->ebu_membase)
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+#define sys1 (priv->sys1_membase)
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+
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+struct falcon_spi {
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+ u32 sfcmd; /* for caching of opcode, direction, ... */
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+
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+ struct spi_master *master;
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+
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+ struct gpon_reg_ebu __iomem *ebu_membase;
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+ struct gpon_reg_sys1 __iomem *sys1_membase;
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+};
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+
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+int falcon_spi_xfer(struct spi_device *spi,
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+ struct spi_transfer *t,
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+ unsigned long flags)
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+{
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+ struct device *dev = &spi->dev;
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+ struct falcon_spi *priv = spi_master_get_devdata(spi->master);
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+ const u8 *txp = t->tx_buf;
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+ u8 *rxp = t->rx_buf;
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+ unsigned int bytelen = ((8 * t->len + 7) / 8);
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+ unsigned int len, alen, dumlen;
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+ u32 val;
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+ enum {
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+ state_init,
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+ state_command_prepare,
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+ state_write,
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+ state_read,
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+ state_disable_cs,
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+ state_end
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+ } state = state_init;
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+
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+ do {
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+ switch (state) {
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+ case state_init: /* detect phase of upper layer sequence */
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+ {
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+ /* initial write ? */
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+ if (flags & FALCON_SPI_XFER_BEGIN) {
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+ if (!txp) {
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+ dev_err(dev,
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+ "BEGIN without tx data!\n");
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+ return -1;
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+ }
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+ /*
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+ * Prepare the parts of the sfcmd register,
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+ * which should not
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+ * change during a sequence!
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+ * Only exception are the length fields,
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+ * especially alen and dumlen.
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+ */
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+
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+ priv->sfcmd = ((spi->chip_select
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+ << SFCMD_CS_OFFSET)
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+ & SFCMD_CS_MASK);
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+ priv->sfcmd |= SFCMD_KEEP_CS_KEEP_SELECTED;
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+ priv->sfcmd |= *txp;
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+ txp++;
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+ bytelen--;
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+ if (bytelen) {
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+ /* more data:
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+ * maybe address and/or dummy */
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+ state = state_command_prepare;
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+ break;
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+ } else {
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+ dev_dbg(dev, "write cmd %02X\n",
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+ priv->sfcmd & SFCMD_OPC_MASK);
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+ }
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+ }
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+ /* continued write ? */
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+ if (txp && bytelen) {
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+ state = state_write;
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+ break;
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+ }
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+ /* read data? */
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+ if (rxp && bytelen) {
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+ state = state_read;
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+ break;
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+ }
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+ /* end of sequence? */
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+ if (flags & FALCON_SPI_XFER_END)
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+ state = state_disable_cs;
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+ else
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+ state = state_end;
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+ break;
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+ }
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+ case state_command_prepare: /* collect tx data for
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+ address and dummy phase */
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+ {
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+ /* txp is valid, already checked */
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+ val = 0;
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+ alen = 0;
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+ dumlen = 0;
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+ while (bytelen > 0) {
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+ if (alen < 3) {
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+ val = (val<<8)|(*txp++);
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+ alen++;
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+ } else if ((dumlen < 15) && (*txp == 0)) {
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+ /*
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+ * assume dummy bytes are set to 0
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+ * from upper layer
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+ */
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+ dumlen++;
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+ txp++;
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+ } else
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+ break;
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+ bytelen--;
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+ }
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+ priv->sfcmd &= ~(SFCMD_ALEN_MASK | SFCMD_DUMLEN_MASK);
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+ priv->sfcmd |= (alen << SFCMD_ALEN_OFFSET) |
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+ (dumlen << SFCMD_DUMLEN_OFFSET);
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+ if (alen > 0)
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+ ebu_w32(val, sfaddr);
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+
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+ dev_dbg(dev, "write cmd %02X, alen=%d "
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+ "(addr=%06X) dumlen=%d\n",
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+ priv->sfcmd & SFCMD_OPC_MASK,
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+ alen, val, dumlen);
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+
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+ if (bytelen > 0) {
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+ /* continue with write */
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+ state = state_write;
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+ } else if (flags & FALCON_SPI_XFER_END) {
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+ /* end of sequence? */
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+ state = state_disable_cs;
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+ } else {
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+ /* go to end and expect another
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+ * call (read or write) */
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+ state = state_end;
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+ }
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+ break;
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+ }
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+ case state_write:
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+ {
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+ /* txp still valid */
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+ priv->sfcmd |= SFCMD_DIR_WRITE;
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+ len = 0;
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+ val = 0;
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+ do {
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+ if (bytelen--)
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+ val |= (*txp++) << (8 * len++);
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+ if ((flags & FALCON_SPI_XFER_END)
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+ && (bytelen == 0)) {
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+ priv->sfcmd &=
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+ ~SFCMD_KEEP_CS_KEEP_SELECTED;
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+ }
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+ if ((len == 4) || (bytelen == 0)) {
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+ ebu_w32(val, sfdata);
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+ ebu_w32(priv->sfcmd
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+ | (len<<SFCMD_DLEN_OFFSET),
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+ sfcmd);
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+ len = 0;
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+ val = 0;
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+ priv->sfcmd &= ~(SFCMD_ALEN_MASK
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+ | SFCMD_DUMLEN_MASK);
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+ }
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+ } while (bytelen);
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+ state = state_end;
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+ break;
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+ }
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+ case state_read:
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+ {
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+ /* read data */
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+ priv->sfcmd &= ~SFCMD_DIR_WRITE;
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+ do {
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+ if ((flags & FALCON_SPI_XFER_END)
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+ && (bytelen <= 4)) {
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+ priv->sfcmd &=
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+ ~SFCMD_KEEP_CS_KEEP_SELECTED;
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+ }
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+ len = (bytelen > 4) ? 4 : bytelen;
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+ bytelen -= len;
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+ ebu_w32(priv->sfcmd
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+ |(len<<SFCMD_DLEN_OFFSET), sfcmd);
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+ priv->sfcmd &= ~(SFCMD_ALEN_MASK
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+ | SFCMD_DUMLEN_MASK);
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+ do {
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+ val = ebu_r32(sfstat);
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+ if (val & SFSTAT_CMD_ERR) {
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+ /* reset error status */
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+ dev_err(dev, "SFSTAT: CMD_ERR "
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+ "(%x)\n", val);
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+ ebu_w32(SFSTAT_CMD_ERR, sfstat);
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+ return -1;
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+ }
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+ } while (val & SFSTAT_CMD_PEND);
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+ val = ebu_r32(sfdata);
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+ do {
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+ *rxp = (val & 0xFF);
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+ rxp++;
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+ val >>= 8;
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+ len--;
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+ } while (len);
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+ } while (bytelen);
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+ state = state_end;
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+ break;
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+ }
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+ case state_disable_cs:
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+ {
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+ priv->sfcmd &= ~SFCMD_KEEP_CS_KEEP_SELECTED;
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+ ebu_w32(priv->sfcmd | (0<<SFCMD_DLEN_OFFSET), sfcmd);
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+ val = ebu_r32(sfstat);
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+ if (val & SFSTAT_CMD_ERR) {
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+ /* reset error status */
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+ dev_err(dev, "SFSTAT: CMD_ERR (%x)\n", val);
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+ ebu_w32(SFSTAT_CMD_ERR, sfstat);
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+ return -1;
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+ }
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+ state = state_end;
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+ break;
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+ }
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+ case state_end:
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+ break;
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+ }
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+ } while (state != state_end);
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+
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+ return 0;
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+}
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+
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+static int falcon_spi_setup(struct spi_device *spi)
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+{
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+ struct device *dev = &spi->dev;
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+ struct falcon_spi *priv = spi_master_get_devdata(spi->master);
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+ const u32 ebuclk = 100*1000*1000;
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+ unsigned int i;
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+ unsigned long flags;
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+
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+ dev_dbg(dev, "setup\n");
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+
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+ if (spi->master->bus_num > 0 || spi->chip_select > 0)
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+ return -ENODEV;
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+
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+ spin_lock_irqsave(&ebu_lock, flags);
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+
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+ if (ebuclk < spi->max_speed_hz) {
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+ /* set EBU clock to 100 MHz */
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+ sys1_w32_mask(0, EBUCC_EBUDIV_SELF100, ebucc);
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+ i = 1; /* divider */
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+ } else {
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+ /* set EBU clock to 50 MHz */
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+ sys1_w32_mask(EBUCC_EBUDIV_SELF100, 0, ebucc);
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+
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+ /* search for suitable divider */
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+ for (i = 1; i < 7; i++) {
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+ if (ebuclk / i <= spi->max_speed_hz)
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+ break;
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+ }
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+ }
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+
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+ /* setup period of serial clock */
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+ ebu_w32_mask(SFTIME_SCKF_POS_MASK
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+ | SFTIME_SCKR_POS_MASK
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+ | SFTIME_SCK_PER_MASK,
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+ (i << SFTIME_SCKR_POS_OFFSET)
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+ | (i << (SFTIME_SCK_PER_OFFSET + 1)),
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+ sftime);
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+
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+ /* set some bits of unused_wd, to not trigger HOLD/WP
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+ * signals on non QUAD flashes */
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+ ebu_w32((SFIO_UNUSED_WD_MASK & (0x8|0x4)), sfio);
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+
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+ ebu_w32(BUSRCON0_AGEN_SERIAL_FLASH | BUSRCON0_PORTW_8_BIT_MUX,
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+ busrcon0);
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+ ebu_w32(BUSWCON0_AGEN_SERIAL_FLASH, buswcon0);
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+ /* set address wrap around to maximum for 24-bit addresses */
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+ ebu_w32_mask(SFCON_DEV_SIZE_MASK, SFCON_DEV_SIZE_A23_0, sfcon);
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+
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+ spin_unlock_irqrestore(&ebu_lock, flags);
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+
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+ return 0;
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+}
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+
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+static int falcon_spi_transfer(struct spi_device *spi, struct spi_message *m)
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+{
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+ struct falcon_spi *priv = spi_master_get_devdata(spi->master);
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+ struct spi_transfer *t;
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+ unsigned long spi_flags;
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+ unsigned long flags;
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+ int ret = 0;
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+
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+ priv->sfcmd = 0;
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+ m->actual_length = 0;
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+
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+ spi_flags = FALCON_SPI_XFER_BEGIN;
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+ list_for_each_entry(t, &m->transfers, transfer_list) {
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+ if (list_is_last(&t->transfer_list, &m->transfers))
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+ spi_flags |= FALCON_SPI_XFER_END;
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+
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+ spin_lock_irqsave(&ebu_lock, flags);
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+ ret = falcon_spi_xfer(spi, t, spi_flags);
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+ spin_unlock_irqrestore(&ebu_lock, flags);
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+
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+ if (ret)
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+ break;
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+
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+ m->actual_length += t->len;
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+
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+ if (t->delay_usecs || t->cs_change)
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+ BUG();
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+
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+ spi_flags = 0;
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+ }
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+
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+ m->status = ret;
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+ m->complete(m->context);
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+
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+ return 0;
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+}
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+
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+static void falcon_spi_cleanup(struct spi_device *spi)
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+{
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+ struct device *dev = &spi->dev;
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+
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+ dev_dbg(dev, "cleanup\n");
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+}
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+
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+static int __devinit falcon_spi_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct falcon_spi *priv;
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+ struct spi_master *master;
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+ struct resource *memres_ebu, *memres_sys1;
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+ int ret;
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+
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+ dev_dbg(dev, "probing\n");
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+
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+ memres_ebu = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ebu");
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+ memres_sys1 = platform_get_resource_byname(pdev, IORESOURCE_MEM,
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+ "sys1");
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+
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+ if (!memres_ebu || !memres_sys1) {
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+ dev_err(dev, "no resources\n");
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+ return -ENODEV;
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+ }
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+
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+ master = spi_alloc_master(&pdev->dev, sizeof(*priv));
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+ if (!master) {
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+ dev_err(dev, "no memory for spi_master\n");
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+ return -ENOMEM;
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+ }
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+
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+ priv = spi_master_get_devdata(master);
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+
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+ priv->ebu_membase = ioremap_nocache(memres_ebu->start & ~KSEG1,
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+ resource_size(memres_ebu));
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+
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+ if (!priv->ebu_membase) {
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+ dev_err(dev, "can't map ebu memory\n");
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+
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+ ret = -ENOMEM;
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+ goto free_master;
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+ }
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+
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+ priv->sys1_membase = ioremap_nocache(memres_sys1->start & ~KSEG1,
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+ resource_size(memres_sys1));
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+
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+ if (!priv->sys1_membase) {
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+ dev_err(dev, "can't map sys1 memory\n");
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+
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+ ret = -ENOMEM;
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+ goto unmap_ebu;
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+ }
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+
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+ priv->master = master;
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+
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+ master->mode_bits = SPI_MODE_3;
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+ master->num_chipselect = 1;
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+ master->bus_num = 0;
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+
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+ master->setup = falcon_spi_setup;
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+ master->transfer = falcon_spi_transfer;
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+ master->cleanup = falcon_spi_cleanup;
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+
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+ platform_set_drvdata(pdev, priv);
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+
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+ ret = spi_register_master(master);
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+ if (ret)
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+ goto unmap_sys1;
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+
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+ return 0;
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+
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+unmap_sys1:
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+ iounmap(priv->sys1_membase);
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+
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+unmap_ebu:
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+ iounmap(priv->ebu_membase);
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+
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+free_master:
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+ spi_master_put(master);
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+
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+ return ret;
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+}
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+
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+static int __devexit falcon_spi_remove(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct falcon_spi *priv = platform_get_drvdata(pdev);
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+
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+ dev_dbg(dev, "removed\n");
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+
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+ spi_unregister_master(priv->master);
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+
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+ iounmap(priv->sys1_membase);
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+ iounmap(priv->ebu_membase);
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+
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+ return 0;
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+}
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+
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+static struct platform_driver falcon_spi_driver = {
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+ .probe = falcon_spi_probe,
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+ .remove = __devexit_p(falcon_spi_remove),
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+ .driver = {
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+ .name = DRV_NAME,
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+ .owner = THIS_MODULE
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+ }
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+};
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+
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+static int __init falcon_spi_init(void)
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+{
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+ return platform_driver_register(&falcon_spi_driver);
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+}
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+
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+static void __exit falcon_spi_exit(void)
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+{
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+ platform_driver_unregister(&falcon_spi_driver);
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+}
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+
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+module_init(falcon_spi_init);
|
|
+module_exit(falcon_spi_exit);
|
|
+
|
|
+MODULE_LICENSE("GPL");
|
|
+MODULE_DESCRIPTION("Lantiq Falcon SPI controller driver");
|
|
--- a/drivers/spi/Kconfig
|
|
+++ b/drivers/spi/Kconfig
|
|
@@ -210,6 +210,10 @@ config SPI_MPC52xx
|
|
This drivers supports the MPC52xx SPI controller in master SPI
|
|
mode.
|
|
|
|
+config SPI_FALCON
|
|
+ tristate "Falcon SPI controller support"
|
|
+ depends on SOC_FALCON
|
|
+
|
|
config SPI_MPC52xx_PSC
|
|
tristate "Freescale MPC52xx PSC SPI controller"
|
|
depends on PPC_MPC52xx && EXPERIMENTAL
|