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05c930e80a
attention: if caches enabled the network is broken attention: the network of the flash image doesn't work because of enabled caches git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20606 3c298f89-4303-0410-b956-a3cf2f4a3e73
52 lines
1.5 KiB
C
52 lines
1.5 KiB
C
/* Settings for Denali DDR SDRAM controller */
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/* Optimise for AR9 Ref Board DDR 221 Mhz - by Ng Aik Ann 16th May 2008 */
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#define MC_DC0_VALUE 0x1B1B
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#define MC_DC1_VALUE 0x0
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#define MC_DC2_VALUE 0x0
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#define MC_DC3_VALUE 0x0
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#define MC_DC4_VALUE 0x0
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#define MC_DC5_VALUE 0x200
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#define MC_DC6_VALUE 0x306
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#define MC_DC7_VALUE 0x403
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#define MC_DC8_VALUE 0x103
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#define MC_DC9_VALUE 0xb0e
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#define MC_DC10_VALUE 0x204
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#define MC_DC11_VALUE 0x1102
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#define MC_DC12_VALUE 0x2c8
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#define MC_DC13_VALUE 0x1
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#define MC_DC14_VALUE 0x0
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#define MC_DC15_VALUE 0x155 /* WDQS tuning for clk_wr*/
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#define MC_DC16_VALUE 0xc800
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#define MC_DC17_VALUE 0x13
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#define MC_DC18_VALUE 0x401
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#define MC_DC19_VALUE 0x200
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#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */
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#define MC_DC21_VALUE 0xc00
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#define MC_DC22_VALUE 0xc0c
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#define MC_DC23_VALUE 0x0
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#define MC_DC24_VALUE 0x74 /* WDQS Tuning for DQS */
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#define MC_DC25_VALUE 0x0
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#define MC_DC26_VALUE 0x0
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#define MC_DC27_VALUE 0x0
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#define MC_DC28_VALUE 0x798
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#define MC_DC29_VALUE 0x445d
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#define MC_DC30_VALUE 0xc351
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#define MC_DC31_VALUE 0x0
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#define MC_DC32_VALUE 0x0
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#define MC_DC33_VALUE 0x0
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#define MC_DC34_VALUE 0x0
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#define MC_DC35_VALUE 0x0
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#define MC_DC36_VALUE 0x0
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#define MC_DC37_VALUE 0x0
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#define MC_DC38_VALUE 0x0
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#define MC_DC39_VALUE 0x0
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#define MC_DC40_VALUE 0x0
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#define MC_DC41_VALUE 0x0
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#define MC_DC42_VALUE 0x0
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#define MC_DC43_VALUE 0x0
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#define MC_DC44_VALUE 0x0
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#define MC_DC45_VALUE 0x600
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//#define MC_DC45_VALUE 0x400
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#define MC_DC46_VALUE 0x0
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