mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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5a2708d192
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30888 3c298f89-4303-0410-b956-a3cf2f4a3e73
154 lines
3.9 KiB
C
154 lines
3.9 KiB
C
/*
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* Ralink RT288x SoC specific setup
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*
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* Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Parts of this file are based on Ralink's 2.6.21 BSP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <asm/mach-ralink/common.h>
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#include <asm/mach-ralink/ramips_gpio.h>
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#include <asm/mach-ralink/rt288x.h>
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#include <asm/mach-ralink/rt288x_regs.h>
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void __iomem * rt288x_sysc_base;
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void __iomem * rt288x_memc_base;
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void __init ramips_soc_prom_init(void)
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{
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void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT2880_SYSC_BASE);
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u32 n0;
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u32 n1;
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u32 id;
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n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
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n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
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id = __raw_readl(sysc + SYSC_REG_CHIP_ID);
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snprintf(ramips_sys_type, RAMIPS_SYS_TYPE_LEN,
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"Ralink %c%c%c%c%c%c%c%c id:%u rev:%u",
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(char) (n0 & 0xff), (char) ((n0 >> 8) & 0xff),
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(char) ((n0 >> 16) & 0xff), (char) ((n0 >> 24) & 0xff),
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(char) (n1 & 0xff), (char) ((n1 >> 8) & 0xff),
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(char) ((n1 >> 16) & 0xff), (char) ((n1 >> 24) & 0xff),
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(id >> CHIP_ID_ID_SHIFT) & CHIP_ID_ID_MASK,
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(id & CHIP_ID_REV_MASK));
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ramips_mem_base = RT2880_SDRAM_BASE;
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ramips_mem_size_min = RT288X_MEM_SIZE_MIN;
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ramips_mem_size_max = RT288X_MEM_SIZE_MAX;
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}
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static struct ramips_gpio_chip rt288x_gpio_chips[] = {
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{
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.chip = {
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.label = "RT288X-GPIO0",
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.base = 0,
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.ngpio = 24,
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},
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.regs = {
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[RAMIPS_GPIO_REG_INT] = 0x00,
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[RAMIPS_GPIO_REG_EDGE] = 0x04,
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[RAMIPS_GPIO_REG_RENA] = 0x08,
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[RAMIPS_GPIO_REG_FENA] = 0x0c,
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[RAMIPS_GPIO_REG_DATA] = 0x20,
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[RAMIPS_GPIO_REG_DIR] = 0x24,
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[RAMIPS_GPIO_REG_POL] = 0x28,
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[RAMIPS_GPIO_REG_SET] = 0x2c,
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[RAMIPS_GPIO_REG_RESET] = 0x30,
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[RAMIPS_GPIO_REG_TOGGLE] = 0x34,
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},
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.map_base = RT2880_PIO_BASE,
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.map_size = RT2880_PIO_SIZE,
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},
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{
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.chip = {
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.label = "RT288X-GPIO1",
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.base = 24,
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.ngpio = 16,
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},
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.regs = {
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[RAMIPS_GPIO_REG_INT] = 0x38,
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[RAMIPS_GPIO_REG_EDGE] = 0x3c,
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[RAMIPS_GPIO_REG_RENA] = 0x40,
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[RAMIPS_GPIO_REG_FENA] = 0x44,
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[RAMIPS_GPIO_REG_DATA] = 0x48,
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[RAMIPS_GPIO_REG_DIR] = 0x4c,
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[RAMIPS_GPIO_REG_POL] = 0x50,
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[RAMIPS_GPIO_REG_SET] = 0x54,
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[RAMIPS_GPIO_REG_RESET] = 0x58,
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[RAMIPS_GPIO_REG_TOGGLE] = 0x5c,
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},
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.map_base = RT2880_PIO_BASE,
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.map_size = RT2880_PIO_SIZE,
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},
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{
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.chip = {
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.label = "RT288X-GPIO2",
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.base = 40,
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.ngpio = 32,
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},
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.regs = {
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[RAMIPS_GPIO_REG_INT] = 0x60,
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[RAMIPS_GPIO_REG_EDGE] = 0x64,
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[RAMIPS_GPIO_REG_RENA] = 0x68,
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[RAMIPS_GPIO_REG_FENA] = 0x6c,
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[RAMIPS_GPIO_REG_DATA] = 0x70,
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[RAMIPS_GPIO_REG_DIR] = 0x74,
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[RAMIPS_GPIO_REG_POL] = 0x78,
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[RAMIPS_GPIO_REG_SET] = 0x7c,
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[RAMIPS_GPIO_REG_RESET] = 0x80,
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[RAMIPS_GPIO_REG_TOGGLE] = 0x84,
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},
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.map_base = RT2880_PIO_BASE,
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.map_size = RT2880_PIO_SIZE,
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},
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};
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static struct ramips_gpio_data rt288x_gpio_data = {
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.chips = rt288x_gpio_chips,
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.num_chips = ARRAY_SIZE(rt288x_gpio_chips),
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};
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static void rt288x_gpio_reserve(int first, int last)
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{
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for (; first <= last; first++)
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gpio_request(first, "reserved");
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}
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void __init rt288x_gpio_init(u32 mode)
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{
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rt288x_sysc_wr(mode, SYSC_REG_GPIO_MODE);
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ramips_gpio_init(&rt288x_gpio_data);
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if ((mode & RT2880_GPIO_MODE_I2C) == 0)
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rt288x_gpio_reserve(1, 2);
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if ((mode & RT2880_GPIO_MODE_SPI) == 0)
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rt288x_gpio_reserve(3, 6);
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if ((mode & RT2880_GPIO_MODE_UART0) == 0)
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rt288x_gpio_reserve(7, 14);
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if ((mode & RT2880_GPIO_MODE_JTAG) == 0)
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rt288x_gpio_reserve(17, 21);
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if ((mode & RT2880_GPIO_MODE_MDIO) == 0)
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rt288x_gpio_reserve(22, 23);
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if ((mode & RT2880_GPIO_MODE_SDRAM) == 0)
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rt288x_gpio_reserve(24, 39);
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if ((mode & RT2880_GPIO_MODE_PCI) == 0)
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rt288x_gpio_reserve(40, 71);
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}
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