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git://projects.qi-hardware.com/openwrt-xburst.git
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2cea1e6b9a
openwrt. this gives us the ability to better support different hardware models, without changing any external tar-balls. only et.o and wl.o is missing and is fetched from my webserver. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@379 3c298f89-4303-0410-b956-a3cf2f4a3e73
368 lines
12 KiB
C
368 lines
12 KiB
C
/*
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* SiliconBackplane Chipcommon core hardware definitions.
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*
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* The chipcommon core provides chip identification, SB control,
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* jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
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* gpio interface, extbus, and support for serial and parallel flashes.
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*
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* $Id$
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* Copyright 2004, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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*/
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#ifndef _SBCHIPC_H
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#define _SBCHIPC_H
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#ifndef _LANGUAGE_ASSEMBLY
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/* cpp contortions to concatenate w/arg prescan */
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#ifndef PAD
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#define _PADLINE(line) pad ## line
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#define _XSTR(line) _PADLINE(line)
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#define PAD _XSTR(__LINE__)
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#endif /* PAD */
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typedef volatile struct {
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uint32 chipid; /* 0x0 */
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uint32 capabilities;
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uint32 corecontrol; /* corerev >= 1 */
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uint32 bist;
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/* OTP */
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uint32 otpstatus; /* 0x10, corerev >= 10 */
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uint32 otpcontrol;
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uint32 otpprog;
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uint32 PAD;
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/* Interrupt control */
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uint32 intstatus; /* 0x20 */
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uint32 intmask;
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uint32 PAD[2];
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/* Jtag Master */
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uint32 jtagcmd; /* 0x30, rev >= 10 */
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uint32 jtagir;
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uint32 jtagdr;
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uint32 jtagctrl;
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/* serial flash interface registers */
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uint32 flashcontrol; /* 0x40 */
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uint32 flashaddress;
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uint32 flashdata;
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uint32 PAD[1];
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/* Silicon backplane configuration broadcast control */
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uint32 broadcastaddress; /* 0x50 */
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uint32 broadcastdata;
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uint32 PAD[2];
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/* gpio - cleared only by power-on-reset */
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uint32 gpioin; /* 0x60 */
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uint32 gpioout;
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uint32 gpioouten;
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uint32 gpiocontrol;
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uint32 gpiointpolarity;
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uint32 gpiointmask;
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uint32 PAD[2];
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/* Watchdog timer */
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uint32 watchdog; /* 0x80 */
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uint32 PAD[3];
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/* clock control */
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uint32 clockcontrol_n; /* 0x90 */
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uint32 clockcontrol_sb; /* aka m0 */
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uint32 clockcontrol_pci; /* aka m1 */
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uint32 clockcontrol_m2; /* mii/uart/mipsref */
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uint32 clockcontrol_mips; /* aka m3 */
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uint32 clkdiv; /* corerev >= 3 */
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uint32 PAD[2];
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/* pll delay registers (corerev >= 4) */
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uint32 pll_on_delay; /* 0xb0 */
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uint32 fref_sel_delay;
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uint32 slow_clk_ctl; /* 5 < corerev < 10 */
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uint32 PAD[1];
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/* Instaclock registers (corerev >= 10) */
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uint32 system_clk_ctl; /* 0xc0 */
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uint32 clkstatestretch;
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uint32 PAD[14];
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/* ExtBus control registers (corerev >= 3) */
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uint32 pcmcia_config; /* 0x100 */
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uint32 pcmcia_memwait;
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uint32 pcmcia_attrwait;
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uint32 pcmcia_iowait;
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uint32 ide_config;
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uint32 ide_memwait;
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uint32 ide_attrwait;
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uint32 ide_iowait;
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uint32 prog_config;
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uint32 prog_waitcount;
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uint32 flash_config;
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uint32 flash_waitcount;
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uint32 PAD[116];
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/* uarts */
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uint8 uart0data; /* 0x300 */
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uint8 uart0imr;
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uint8 uart0fcr;
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uint8 uart0lcr;
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uint8 uart0mcr;
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uint8 uart0lsr;
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uint8 uart0msr;
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uint8 uart0scratch;
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uint8 PAD[248]; /* corerev >= 1 */
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uint8 uart1data; /* 0x400 */
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uint8 uart1imr;
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uint8 uart1fcr;
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uint8 uart1lcr;
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uint8 uart1mcr;
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uint8 uart1lsr;
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uint8 uart1msr;
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uint8 uart1scratch;
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} chipcregs_t;
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#endif /* _LANGUAGE_ASSEMBLY */
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#define CC_CHIPID 0
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#define CC_CAPABILITIES 4
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#define CC_JTAGCMD 0x30
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#define CC_JTAGIR 0x34
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#define CC_JTAGDR 0x38
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#define CC_JTAGCTRL 0x3c
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#define CC_CLKDIV 0xa4
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/* chipid */
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#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
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#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
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#define CID_REV_SHIFT 16 /* Chip Revision shift */
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#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
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#define CID_PKG_SHIFT 20 /* Package Option shift */
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#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
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#define CID_CC_SHIFT 24
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/* capabilities */
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#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
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#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
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#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
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#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
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#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
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#define CAP_EXTBUS 0x00000040 /* External bus present */
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#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
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#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
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#define CAP_PWR_CTL 0x00040000 /* Power control */
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#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
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#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
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#define CAP_ROM 0x00800000 /* Internal boot rom active */
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/* PLL type */
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#define PLL_NONE 0x00000000
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#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
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#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
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#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
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#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
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/* corecontrol */
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#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
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#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
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/* jtagcmd */
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#define JCMD_START 0x80000000
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#define JCMD_BUSY 0x80000000
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#define JCMD_PAUSE 0x40000000
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#define JCMD0_ACC_MASK 0x0000f000
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#define JCMD0_ACC_IRDR 0x00000000
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#define JCMD0_ACC_DR 0x00001000
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#define JCMD0_ACC_IR 0x00002000
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#define JCMD0_ACC_RESET 0x00003000
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#define JCMD0_ACC_IRPDR 0x00004000
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#define JCMD0_ACC_PDR 0x00005000
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#define JCMD0_IRW_MASK 0x00000f00
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#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
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#define JCMD_ACC_IRDR 0x00000000
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#define JCMD_ACC_DR 0x00010000
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#define JCMD_ACC_IR 0x00020000
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#define JCMD_ACC_RESET 0x00030000
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#define JCMD_ACC_IRPDR 0x00040000
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#define JCMD_ACC_PDR 0x00050000
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#define JCMD_IRW_MASK 0x00001f00
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#define JCMD_IRW_SHIFT 8
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#define JCMD_DRW_MASK 0x0000003f
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/* jtagctrl */
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#define JCTRL_FORCE_CLK 4 /* Force clock */
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#define JCTRL_EXT_EN 2 /* Enable external targets */
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#define JCTRL_EN 1 /* Enable Jtag master */
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/* Fields in clkdiv */
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#define CLKD_SFLASH 0x0f000000
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#define CLKD_SFLASH_SHIFT 24
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#define CLKD_OTP 0x000f0000
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#define CLKD_OTP_SHIFT 16
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#define CLKD_JTAG 0x00000f00
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#define CLKD_JTAG_SHIFT 8
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#define CLKD_UART 0x000000ff
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/* intstatus/intmask */
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#define CI_GPIO 0x00000001 /* gpio intr */
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#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
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#define CI_WDREST 0x80000000 /* watchdog reset occurred */
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/* slow_clk_ctl */
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#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
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#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
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#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
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#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
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#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
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#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
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#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
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#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
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#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
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#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
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#define SCC_CD_MASK 0xffff0000 /* ClockDivider mask, SlowClk = 1/(4+divisor) * crystal/PCI clock */
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#define SCC_CD_SHF 16 /* CLockDivider shift */
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/* sys_clk_ctl */
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#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
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#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
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#define SYCC_FP 0x00000004 /* ForcePLLOn */
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#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
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#define SYCC_HR 0x00000010 /* Force HT */
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#define SYCC_CD_MASK 0xffff0000 /* ClockDivider mask, SlowClk = 1/(4+divisor) * crystal/PCI clock */
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#define SYCC_CD_SHF 16 /* CLockDivider shift */
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/* clockcontrol_n */
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#define CN_N1_MASK 0x3f /* n1 control */
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#define CN_N2_MASK 0x3f00 /* n2 control */
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#define CN_N2_SHIFT 8
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/* clockcontrol_sb/pci/uart */
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#define CC_M1_MASK 0x3f /* m1 control */
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#define CC_M2_MASK 0x3f00 /* m2 control */
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#define CC_M2_SHIFT 8
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#define CC_M3_MASK 0x3f0000 /* m3 control */
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#define CC_M3_SHIFT 16
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#define CC_MC_MASK 0x1f000000 /* mux control */
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#define CC_MC_SHIFT 24
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/* N3M Clock control values for 125Mhz */
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#define CC_125_N 0x0802 /* Default values for bcm4310 */
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#define CC_125_M 0x04020009
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#define CC_125_M25 0x11090009
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#define CC_125_M33 0x11090005
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/* N3M Clock control magic field values */
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#define CC_F6_2 0x02 /* A factor of 2 in */
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#define CC_F6_3 0x03 /* 6-bit fields like */
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#define CC_F6_4 0x05 /* N1, M1 or M3 */
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#define CC_F6_5 0x09
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#define CC_F6_6 0x11
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#define CC_F6_7 0x21
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#define CC_F5_BIAS 5 /* 5-bit fields get this added */
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#define CC_MC_BYPASS 0x08
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#define CC_MC_M1 0x04
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#define CC_MC_M1M2 0x02
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#define CC_MC_M1M2M3 0x01
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#define CC_MC_M1M3 0x11
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/* Type 2 Clock control magic field values */
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#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
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#define CC_T2M2_BIAS 3 /* m2 bias */
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#define CC_T2MC_M1BYP 1
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#define CC_T2MC_M2BYP 2
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#define CC_T2MC_M3BYP 4
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/* Common clock base */
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#define CC_CLOCK_BASE 24000000 /* Half the clock freq */
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/* Flash types in the chipcommon capabilities register */
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#define FLASH_NONE 0x000 /* No flash */
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#define SFLASH_ST 0x100 /* ST serial flash */
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#define SFLASH_AT 0x200 /* Atmel serial flash */
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#define PFLASH 0x700 /* Parallel flash */
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/* Prefered flash window in chipcommon */
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#define CC_FLASH_BASE 0xbc000000 /* Chips with chipcommon cores */
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#define CC_FLASH_MAX 0x02000000 /* Maximum flash size with chipc */
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/* Bits in the config registers */
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#define CC_CFG_EN 0x0001 /* Enable */
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#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
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#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
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#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
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#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
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#define CC_CFG_EM_IDE 0x000a /* IDE */
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#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
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#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
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#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
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#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
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/* Start/busy bit in flashcontrol */
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#define SFLASH_START 0x80000000
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#define SFLASH_BUSY SFLASH_START
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/* flashcontrol opcodes for ST flashes */
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#define SFLASH_ST_WREN 0x0006 /* Write Enable */
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#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
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#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
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#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
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#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
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#define SFLASH_ST_PP 0x0302 /* Page Program */
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#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
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#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
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#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
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#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
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/* Status register bits for ST flashes */
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#define SFLASH_ST_WIP 0x01 /* Write In Progress */
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#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
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#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
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#define SFLASH_ST_BP_SHIFT 2
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#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
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/* flashcontrol opcodes for Atmel flashes */
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#define SFLASH_AT_READ 0x07e8
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#define SFLASH_AT_PAGE_READ 0x07d2
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#define SFLASH_AT_BUF1_READ
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#define SFLASH_AT_BUF2_READ
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#define SFLASH_AT_STATUS 0x01d7
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#define SFLASH_AT_BUF1_WRITE 0x0384
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#define SFLASH_AT_BUF2_WRITE 0x0387
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#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
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#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
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#define SFLASH_AT_BUF1_PROGRAM 0x0288
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#define SFLASH_AT_BUF2_PROGRAM 0x0289
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#define SFLASH_AT_PAGE_ERASE 0x0281
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#define SFLASH_AT_BLOCK_ERASE 0x0250
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#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
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#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
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#define SFLASH_AT_BUF1_LOAD 0x0253
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#define SFLASH_AT_BUF2_LOAD 0x0255
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#define SFLASH_AT_BUF1_COMPARE 0x0260
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#define SFLASH_AT_BUF2_COMPARE 0x0261
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#define SFLASH_AT_BUF1_REPROGRAM 0x0258
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#define SFLASH_AT_BUF2_REPROGRAM 0x0259
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/* Status register bits for Atmel flashes */
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#define SFLASH_AT_READY 0x80
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#define SFLASH_AT_MISMATCH 0x40
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#define SFLASH_AT_ID_MASK 0x38
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#define SFLASH_AT_ID_SHIFT 3
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#endif /* _SBCHIPC_H */
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