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git://projects.qi-hardware.com/openwrt-xburst.git
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726 lines
18 KiB
C
Executable File
726 lines
18 KiB
C
Executable File
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/ac97_codec.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <sound/soc-dapm.h>
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#include "../jz4740/jz4740-pcm.h"
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#include "jzcodec.h"
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#define AUDIO_NAME "jzcodec"
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#define JZCODEC_VERSION "1.0"
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/*
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* Debug
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*/
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#define JZCODEC_DEBUG 0
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#ifdef JZCODEC_DEBUG
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#define dbg(format, arg...) \
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printk(KERN_DEBUG AUDIO_NAME ": " format "\n" , ## arg)
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#else
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#define dbg(format, arg...) do {} while (0)
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#endif
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#define err(format, arg...) \
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printk(KERN_ERR AUDIO_NAME ": " format "\n" , ## arg)
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#define info(format, arg...) \
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printk(KERN_INFO AUDIO_NAME ": " format "\n" , ## arg)
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#define warn(format, arg...) \
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printk(KERN_WARNING AUDIO_NAME ": " format "\n" , ## arg)
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struct snd_soc_codec_device soc_codec_dev_jzcodec;
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/* codec private data */
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struct jzcodec_priv {
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unsigned int sysclk;
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};
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/*
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* jzcodec register cache
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*/
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static u32 jzcodec_reg[JZCODEC_CACHEREGNUM / 2];
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/*
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* codec register is 16 bits width in ALSA, so we define array to store 16 bits configure paras
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*/
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static u16 jzcodec_reg_LH[JZCODEC_CACHEREGNUM];
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/*
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* read jzcodec register cache
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*/
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static inline unsigned int jzcodec_read_reg_cache(struct snd_soc_codec *codec,
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unsigned int reg)
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{
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u16 *cache = codec->reg_cache;
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if (reg >= JZCODEC_CACHEREGNUM)
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return -1;
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return cache[reg];
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}
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/*
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* write jzcodec register cache
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*/
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static inline void jzcodec_write_reg_cache(struct snd_soc_codec *codec,
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unsigned int reg, u16 value)
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{
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u16 *cache = codec->reg_cache;
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u32 reg_val;
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if (reg >= JZCODEC_CACHEREGNUM) {
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return;
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}
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cache[reg] = value;
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/* update internal codec register value */
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switch (reg) {
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case 0:
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case 1:
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reg_val = cache[0] & 0xffff;
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reg_val = reg_val | (cache[1] << 16);
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jzcodec_reg[0] = reg_val;
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break;
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case 2:
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case 3:
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reg_val = cache[2] & 0xffff;
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reg_val = reg_val | (cache[3] << 16);
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jzcodec_reg[1] = reg_val;
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break;
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}
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}
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/*
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* write to the jzcodec register space
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*/
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static int jzcodec_write(struct snd_soc_codec *codec, unsigned int reg,
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unsigned int value)
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{
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jzcodec_write_reg_cache(codec, reg, value);
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if(codec->hw_write)
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codec->hw_write(&value, NULL, reg);
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return 0;
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}
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static int jzcodec_reset(struct snd_soc_codec *codec)
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{
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u16 val;
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val = jzcodec_read_reg_cache(codec, ICODEC_1_LOW);
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val = val | 0x1;
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jzcodec_write(codec, ICODEC_1_LOW, val);
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mdelay(1);
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val = jzcodec_read_reg_cache(codec, ICODEC_1_LOW);
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val = val & ~0x1;
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jzcodec_write(codec, ICODEC_1_LOW, val);
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mdelay(1);
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return 0;
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}
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static const struct snd_kcontrol_new jzcodec_snd_controls[] = {
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//SOC_DOUBLE_R("Master Playback Volume", 1, 1, 0, 3, 0),
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SOC_DOUBLE_R("Master Playback Volume", ICODEC_2_LOW, ICODEC_2_LOW, 0, 3, 0),
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//SOC_DOUBLE_R("MICBG", ICODEC_2_LOW, ICODEC_2_LOW, 4, 3, 0),
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//SOC_DOUBLE_R("Line", 2, 2, 0, 31, 0),
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SOC_DOUBLE_R("Line", ICODEC_2_HIGH, ICODEC_2_HIGH, 0, 31, 0),
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};
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/* add non dapm controls */
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static int jzcodec_add_controls(struct snd_soc_codec *codec)
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{
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int err, i;
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for (i = 0; i < ARRAY_SIZE(jzcodec_snd_controls); i++) {
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if ((err = snd_ctl_add(codec->card,
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snd_soc_cnew(&jzcodec_snd_controls[i], codec, NULL))) < 0)
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return err;
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}
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return 0;
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}
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static const struct snd_soc_dapm_widget jzcodec_dapm_widgets[] = {
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SND_SOC_DAPM_OUTPUT("LOUT"),
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SND_SOC_DAPM_OUTPUT("LHPOUT"),
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SND_SOC_DAPM_OUTPUT("ROUT"),
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SND_SOC_DAPM_OUTPUT("RHPOUT"),
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SND_SOC_DAPM_INPUT("MICIN"),
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SND_SOC_DAPM_INPUT("RLINEIN"),
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SND_SOC_DAPM_INPUT("LLINEIN"),
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};
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static const char *intercon[][3] = {
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/* output mixer */
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{"Output Mixer", "Line Bypass Switch", "Line Input"},
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{"Output Mixer", "HiFi Playback Switch", "DAC"},
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{"Output Mixer", "Mic Sidetone Switch", "Mic Bias"},
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/* outputs */
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{"RHPOUT", NULL, "Output Mixer"},
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{"ROUT", NULL, "Output Mixer"},
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{"LHPOUT", NULL, "Output Mixer"},
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{"LOUT", NULL, "Output Mixer"},
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/* input mux */
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{"Input Mux", "Line In", "Line Input"},
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{"Input Mux", "Mic", "Mic Bias"},
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{"ADC", NULL, "Input Mux"},
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/* inputs */
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{"Line Input", NULL, "LLINEIN"},
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{"Line Input", NULL, "RLINEIN"},
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{"Mic Bias", NULL, "MICIN"},
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/* terminator */
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{NULL, NULL, NULL},
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};
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static int jzcodec_add_widgets(struct snd_soc_codec *codec)
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{
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int i,cnt;
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cnt = ARRAY_SIZE(jzcodec_dapm_widgets);
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for(i = 0; i < ARRAY_SIZE(jzcodec_dapm_widgets); i++) {
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snd_soc_dapm_new_control(codec, &jzcodec_dapm_widgets[i]);
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}
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#if 1
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/* set up audio path interconnects */
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for(i = 0; intercon[i][0] != NULL; i++) {
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snd_soc_dapm_connect_input(codec, intercon[i][0],
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intercon[i][1], intercon[i][2]);
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}
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#endif
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snd_soc_dapm_new_widgets(codec);
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return 0;
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}
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static int jzcodec_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_device *socdev = rtd->socdev;
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struct snd_soc_codec *codec = socdev->codec;
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u16 reg_val = jzcodec_read_reg_cache(codec, ICODEC_2_LOW);
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#if 0
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/* bit size. codec side */
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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break;
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}
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#endif
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/* sample rate */
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reg_val = reg_val & ~(0xf << 8);
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switch (params_rate(params)) {
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case 8000:
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reg_val |= (0x0 << 8);
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break;
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case 11025:
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reg_val |= (0x1 << 8);
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break;
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case 12000:
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reg_val |= (0x2 << 8);
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break;
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case 16000:
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reg_val |= (0x3 << 8);
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break;
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case 22050:
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reg_val |= (0x4 << 8);
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break;
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case 24000:
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reg_val |= (0x5 << 8);
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break;
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case 32000:
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reg_val |= (0x6 << 8);
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break;
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case 44100:
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reg_val |= (0x7 << 8);
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break;
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case 48000:
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reg_val |= (0x8 << 8);
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break;
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default:
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printk(" invalid rate :0x%08x\n",params_rate(params));
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}
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jzcodec_write(codec, ICODEC_2_LOW, reg_val);
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return 0;
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}
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static int jzcodec_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
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{
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int ret = 0;
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u16 val;
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_device *socdev = rtd->socdev;
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struct snd_soc_codec *codec = socdev->codec;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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//case SNDRV_PCM_TRIGGER_RESUME:
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//case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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val = 0x7302;
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jzcodec_write(codec, ICODEC_1_LOW, val);
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val = 0x0003;
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jzcodec_write(codec, ICODEC_1_HIGH, val);
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mdelay(2);
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val = 0x6000;
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jzcodec_write(codec, ICODEC_1_LOW, val);
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val = 0x0300;
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jzcodec_write(codec, ICODEC_1_HIGH, val);
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mdelay(2);
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val = 0x2000;
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jzcodec_write(codec, ICODEC_1_LOW, val);
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val = 0x0300;
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jzcodec_write(codec, ICODEC_1_HIGH, val);
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} else {
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val = 0x4300;
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jzcodec_write(codec, ICODEC_1_LOW, val);
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val = 0x1402;
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jzcodec_write(codec, ICODEC_1_HIGH, val);
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}
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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//case SNDRV_PCM_TRIGGER_SUSPEND:
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//case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
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val = 0x3300;
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jzcodec_write(codec, ICODEC_1_LOW, val);
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val = 0x0003;
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jzcodec_write(codec, ICODEC_1_HIGH, val);
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} else {
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val = 0x3300;
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jzcodec_write(codec, ICODEC_1_LOW, val);
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val = 0x0003;
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jzcodec_write(codec, ICODEC_1_HIGH, val);
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}
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break;
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default:
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ret = -EINVAL;
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}
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return ret;
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}
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static int jzcodec_pcm_prepare(struct snd_pcm_substream *substream)
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{
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/*struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_device *socdev = rtd->socdev;
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struct snd_soc_codec *codec = socdev->codec; */
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return 0;
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}
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static void jzcodec_shutdown(struct snd_pcm_substream *substream)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_device *socdev = rtd->socdev;
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struct snd_soc_codec *codec = socdev->codec;
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/* deactivate */
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if (!codec->active) {
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udelay(50);
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}
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}
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static int jzcodec_mute(struct snd_soc_dai *dai, int mute)
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{
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struct snd_soc_codec *codec = dai->codec;
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u16 reg_val = jzcodec_read_reg_cache(codec, ICODEC_1_LOW);
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if (mute != 0)
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mute = 1;
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if (mute)
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reg_val = reg_val | (0x1 << 14);
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else
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reg_val = reg_val & ~(0x1 << 14);
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jzcodec_write(codec, ICODEC_1_LOW, reg_val);
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return 0;
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}
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static int jzcodec_set_dai_sysclk(struct snd_soc_dai *codec_dai,
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int clk_id, unsigned int freq, int dir)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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struct jzcodec_priv *jzcodec = codec->private_data;
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jzcodec->sysclk = freq;
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return 0;
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}
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/*
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* Set's ADC and Voice DAC format. called by pavo_hw_params() in pavo.c
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*/
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static int jzcodec_set_dai_fmt(struct snd_soc_dai *codec_dai,
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unsigned int fmt)
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{
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struct snd_soc_codec *codec = codec_dai->codec;
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/* set master/slave audio interface. codec side */
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM:
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/* set master mode for codec */
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break;
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case SND_SOC_DAIFMT_CBS_CFS:
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/* set slave mode for codec */
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break;
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default:
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return -EINVAL;
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}
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/* interface format . set some parameter for codec side */
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_I2S:
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/* set I2S mode for codec */
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break;
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case SND_SOC_DAIFMT_RIGHT_J:
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/* set right J mode */
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break;
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case SND_SOC_DAIFMT_LEFT_J:
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/* set left J mode */
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break;
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case SND_SOC_DAIFMT_DSP_A:
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/* set dsp A mode */
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break;
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case SND_SOC_DAIFMT_DSP_B:
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/* set dsp B mode */
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break;
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default:
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return -EINVAL;
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}
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/* clock inversion. codec side */
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switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
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case SND_SOC_DAIFMT_NB_NF:
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break;
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case SND_SOC_DAIFMT_IB_IF:
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break;
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case SND_SOC_DAIFMT_IB_NF:
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break;
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case SND_SOC_DAIFMT_NB_IF:
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break;
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default:
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return -EINVAL;
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}
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/* jzcodec_write(codec, 0, val); */
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return 0;
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}
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#if 1
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static int jzcodec_dapm_event(struct snd_soc_codec *codec, int event)
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{
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/* u16 reg_val; */
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switch (event) {
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case SNDRV_CTL_POWER_D0: /* full On */
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/* vref/mid, osc on, dac unmute */
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/* u16 reg_val = jzcodec_read_reg_cache(codec, ICODEC_1_LOW); */
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/* jzcodec_write(codec, 0, val); */
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break;
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case SNDRV_CTL_POWER_D1: /* partial On */
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case SNDRV_CTL_POWER_D2: /* partial On */
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break;
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case SNDRV_CTL_POWER_D3hot: /* Off, with power */
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/* everything off except vref/vmid, */
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/*reg_val = 0x0800;
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jzcodec_write_reg_cache(codec, ICODEC_1_LOW, reg_val);
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reg_val = 0x0017;
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jzcodec_write_reg_cache(codec, ICODEC_1_HIGH, reg_val);
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REG_ICDC_CDCCR1 = jzcodec_reg[0];
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mdelay(2);
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reg_val = 0x2102;
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jzcodec_write_reg_cache(codec, ICODEC_1_LOW, reg_val);
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reg_val = 0x001f;
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jzcodec_write_reg_cache(codec, ICODEC_1_HIGH, reg_val);
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REG_ICDC_CDCCR1 = jzcodec_reg[0];
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mdelay(2);
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reg_val = 0x3302;
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jzcodec_write_reg_cache(codec, ICODEC_1_LOW, reg_val);
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reg_val = 0x0003;
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jzcodec_write_reg_cache(codec, ICODEC_1_HIGH, reg_val);
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REG_ICDC_CDCCR1 = jzcodec_reg[0];*/
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break;
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case SNDRV_CTL_POWER_D3cold: /* Off, without power */
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/* everything off, dac mute, inactive */
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/*reg_val = 0x2302;
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jzcodec_write(codec, ICODEC_1_LOW, reg_val);
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reg_val = 0x001b;
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jzcodec_write(codec, ICODEC_1_HIGH, reg_val);
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mdelay(1);
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reg_val = 0x2102;
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jzcodec_write(codec, ICODEC_1_LOW, reg_val);
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reg_val = 0x001b;
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jzcodec_write(codec, ICODEC_1_HIGH, reg_val);*/
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break;
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}
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//codec->dapm_state = event;
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return 0;
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}
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#endif
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#define JZCODEC_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
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SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
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SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
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SNDRV_PCM_RATE_48000)
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#define JZCODEC_FORMATS (SNDRV_PCM_FORMAT_S8 | SNDRV_PCM_FMTBIT_S16_LE)
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struct snd_soc_dai jzcodec_dai = {
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.name = "JZCODEC",
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.playback = {
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.stream_name = "Playback",
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.channels_min = 1,
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.channels_max = 2,
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.rates = JZCODEC_RATES,
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.formats = JZCODEC_FORMATS,},
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.capture = {
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.stream_name = "Capture",
|
|
.channels_min = 1,
|
|
.channels_max = 2,
|
|
.rates = JZCODEC_RATES,
|
|
.formats = JZCODEC_FORMATS,},
|
|
.ops = {
|
|
.trigger = jzcodec_pcm_trigger,
|
|
.prepare = jzcodec_pcm_prepare,
|
|
.hw_params = jzcodec_hw_params,
|
|
.shutdown = jzcodec_shutdown,
|
|
},
|
|
.dai_ops = {
|
|
.digital_mute = jzcodec_mute,
|
|
.set_sysclk = jzcodec_set_dai_sysclk,
|
|
.set_fmt = jzcodec_set_dai_fmt,
|
|
}
|
|
};
|
|
EXPORT_SYMBOL_GPL(jzcodec_dai);
|
|
|
|
#ifdef CONFIG_PM
|
|
static u16 jzcodec_reg_pm[JZCODEC_CACHEREGNUM];
|
|
static int jzcodec_suspend(struct platform_device *pdev, pm_message_t state)
|
|
{
|
|
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
|
|
struct snd_soc_codec *codec = socdev->codec;
|
|
|
|
jzcodec_reg_pm[ICODEC_1_LOW] = jzcodec_read_reg_cache(codec, ICODEC_1_LOW);
|
|
jzcodec_reg_pm[ICODEC_1_HIGH] = jzcodec_read_reg_cache(codec, ICODEC_1_HIGH);
|
|
jzcodec_reg_pm[ICODEC_2_LOW] = jzcodec_read_reg_cache(codec, ICODEC_2_LOW);
|
|
jzcodec_reg_pm[ICODEC_2_HIGH] = jzcodec_read_reg_cache(codec, ICODEC_2_HIGH);
|
|
|
|
jzcodec_dapm_event(codec, SNDRV_CTL_POWER_D3cold);
|
|
return 0;
|
|
}
|
|
|
|
static int jzcodec_resume(struct platform_device *pdev)
|
|
{
|
|
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
|
|
struct snd_soc_codec *codec = socdev->codec;
|
|
u16 reg_val;
|
|
|
|
jzcodec_dapm_event(codec, SNDRV_CTL_POWER_D3hot);
|
|
reg_val = jzcodec_reg_pm[ICODEC_1_LOW];
|
|
jzcodec_write(codec, ICODEC_1_LOW, reg_val);
|
|
reg_val = jzcodec_reg_pm[ICODEC_1_HIGH];
|
|
jzcodec_write(codec, ICODEC_1_HIGH, reg_val);
|
|
reg_val = jzcodec_reg_pm[ICODEC_2_LOW];
|
|
jzcodec_write(codec, ICODEC_2_LOW, reg_val);
|
|
reg_val = jzcodec_reg_pm[ICODEC_2_HIGH];
|
|
jzcodec_write(codec, ICODEC_2_HIGH, reg_val);
|
|
|
|
jzcodec_dapm_event(codec, codec->suspend_dapm_state);
|
|
return 0;
|
|
}
|
|
#else
|
|
#define jzcodec_suspend NULL
|
|
#define jzcodec_resume NULL
|
|
#endif
|
|
/*
|
|
* initialise the JZCODEC driver
|
|
* register the mixer and dsp interfaces with the kernel
|
|
*/
|
|
static int jzcodec_init(struct snd_soc_device *socdev)
|
|
{
|
|
struct snd_soc_codec *codec = socdev->codec;
|
|
int reg, ret = 0;
|
|
u16 reg_val;
|
|
|
|
for (reg = 0; reg < JZCODEC_CACHEREGNUM / 2; reg++) {
|
|
switch (reg) {
|
|
case 0:
|
|
jzcodec_reg[reg] = REG_ICDC_CDCCR1;
|
|
jzcodec_reg_LH[ICODEC_1_LOW] = jzcodec_reg[reg] & 0xffff;
|
|
jzcodec_reg_LH[ICODEC_1_HIGH] = (jzcodec_reg[reg] & 0xffff0000) >> 16;
|
|
break;
|
|
case 1:
|
|
jzcodec_reg[reg] = REG_ICDC_CDCCR2;
|
|
jzcodec_reg_LH[ICODEC_2_LOW] = jzcodec_reg[reg] & 0xffff;
|
|
jzcodec_reg_LH[ICODEC_2_HIGH] = (jzcodec_reg[reg] & 0xffff0000) >> 16;
|
|
break;
|
|
}
|
|
}
|
|
|
|
codec->name = "JZCODEC";
|
|
codec->owner = THIS_MODULE;
|
|
codec->read = jzcodec_read_reg_cache;
|
|
codec->write = jzcodec_write;
|
|
//codec->dapm_event = jzcodec_dapm_event;
|
|
codec->dai = &jzcodec_dai;
|
|
codec->num_dai = 1;
|
|
codec->reg_cache_size = sizeof(jzcodec_reg_LH);
|
|
codec->reg_cache = kmemdup(jzcodec_reg_LH, sizeof(jzcodec_reg_LH), GFP_KERNEL);
|
|
if (codec->reg_cache == NULL)
|
|
return -ENOMEM;
|
|
|
|
jzcodec_reset(codec);
|
|
/* register pcms */
|
|
ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
|
|
if (ret < 0) {
|
|
printk(KERN_ERR "jzcodec: failed to create pcms\n");
|
|
goto pcm_err;
|
|
}
|
|
|
|
/* power on device */
|
|
jzcodec_dapm_event(codec, SNDRV_CTL_POWER_D3hot);
|
|
|
|
/* clear suspend bit of jz4740 internal codec */
|
|
reg_val = jzcodec_read_reg_cache(codec, ICODEC_1_LOW);
|
|
reg_val = reg_val & ~(0x2);
|
|
jzcodec_write(codec, ICODEC_1_LOW, reg_val);
|
|
/* set vol bits */
|
|
reg_val = jzcodec_read_reg_cache(codec, ICODEC_2_LOW);
|
|
reg_val = reg_val | 0x3;
|
|
jzcodec_write(codec, ICODEC_2_LOW, reg_val);
|
|
/* set line in capture gain bits */
|
|
reg_val = jzcodec_read_reg_cache(codec, ICODEC_2_HIGH);
|
|
reg_val = reg_val | 0x1f;
|
|
jzcodec_write(codec, ICODEC_2_HIGH, reg_val);
|
|
/* set mic boost gain bits */
|
|
reg_val = jzcodec_read_reg_cache(codec, ICODEC_2_LOW);
|
|
reg_val = reg_val | (0x3 << 4);
|
|
jzcodec_write(codec, ICODEC_2_LOW, reg_val);
|
|
mdelay(5);
|
|
reg_val = 0x3300;
|
|
jzcodec_write(codec, ICODEC_1_LOW, reg_val);
|
|
reg_val = 0x0003;
|
|
jzcodec_write(codec, ICODEC_1_HIGH, reg_val);
|
|
jzcodec_add_controls(codec);
|
|
jzcodec_add_widgets(codec);
|
|
|
|
ret = snd_soc_register_card(socdev);
|
|
if (ret < 0) {
|
|
printk(KERN_ERR "jzcodec: failed to register card\n");
|
|
goto card_err;
|
|
}
|
|
return ret;
|
|
|
|
card_err:
|
|
snd_soc_free_pcms(socdev);
|
|
snd_soc_dapm_free(socdev);
|
|
pcm_err:
|
|
kfree(codec->reg_cache);
|
|
return ret;
|
|
}
|
|
|
|
static struct snd_soc_device *jzcodec_socdev;
|
|
|
|
static int write_codec_reg(u16 * add, char * name, int reg)
|
|
{
|
|
switch (reg) {
|
|
case 0:
|
|
case 1:
|
|
REG_ICDC_CDCCR1 = jzcodec_reg[0];
|
|
break;
|
|
case 2:
|
|
case 3:
|
|
REG_ICDC_CDCCR2 = jzcodec_reg[1];
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int jzcodec_probe(struct platform_device *pdev)
|
|
{
|
|
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
|
|
struct snd_soc_codec *codec;
|
|
struct jzcodec_priv *jzcodec;
|
|
int ret = 0;
|
|
|
|
codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
|
|
if (codec == NULL)
|
|
return -ENOMEM;
|
|
|
|
jzcodec = kzalloc(sizeof(struct jzcodec_priv), GFP_KERNEL);
|
|
if (jzcodec == NULL) {
|
|
kfree(codec);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
codec->private_data = jzcodec;
|
|
socdev->codec = codec;
|
|
mutex_init(&codec->mutex);
|
|
INIT_LIST_HEAD(&codec->dapm_widgets);
|
|
INIT_LIST_HEAD(&codec->dapm_paths);
|
|
|
|
jzcodec_socdev = socdev;
|
|
|
|
/* Add other interfaces here ,no I2C connection */
|
|
codec->hw_write = (hw_write_t)write_codec_reg;
|
|
ret = jzcodec_init(jzcodec_socdev);
|
|
|
|
if (ret < 0) {
|
|
codec = jzcodec_socdev->codec;
|
|
err("failed to initialise jzcodec\n");
|
|
kfree(codec);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* power down chip */
|
|
static int jzcodec_remove(struct platform_device *pdev)
|
|
{
|
|
struct snd_soc_device *socdev = platform_get_drvdata(pdev);
|
|
struct snd_soc_codec *codec = socdev->codec;
|
|
|
|
if (codec->control_data)
|
|
jzcodec_dapm_event(codec, SNDRV_CTL_POWER_D3cold);
|
|
|
|
snd_soc_free_pcms(socdev);
|
|
snd_soc_dapm_free(socdev);
|
|
kfree(codec->private_data);
|
|
kfree(codec);
|
|
|
|
return 0;
|
|
}
|
|
|
|
struct snd_soc_codec_device soc_codec_dev_jzcodec = {
|
|
.probe = jzcodec_probe,
|
|
.remove = jzcodec_remove,
|
|
.suspend = jzcodec_suspend,
|
|
.resume = jzcodec_resume,
|
|
};
|
|
|
|
EXPORT_SYMBOL_GPL(soc_codec_dev_jzcodec);
|
|
|
|
MODULE_DESCRIPTION("ASoC JZCODEC driver");
|
|
MODULE_AUTHOR("Richard");
|
|
MODULE_LICENSE("GPL");
|