mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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c92885c466
- Includes large parts of the patch from #1021 by dpalffy - Includes RB532 NAND driver changes by n0-1 git-svn-id: svn://svn.openwrt.org/openwrt/trunk@5789 3c298f89-4303-0410-b956-a3cf2f4a3e73
370 lines
12 KiB
Diff
370 lines
12 KiB
Diff
diff -urN linux-2.6.19.ref/arch/mips/kernel/genex.S linux-2.6.19/arch/mips/kernel/genex.S
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--- linux-2.6.19.ref/arch/mips/kernel/genex.S 2006-11-29 22:57:37.000000000 +0100
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+++ linux-2.6.19/arch/mips/kernel/genex.S 2006-12-04 21:34:09.000000000 +0100
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@@ -73,6 +73,10 @@
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.set push
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.set mips3
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.set noat
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+#ifdef CONFIG_BCM947XX
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+ nop
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+ nop
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+#endif
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mfc0 k1, CP0_CAUSE
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li k0, 31<<2
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andi k1, k1, 0x7c
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diff -urN linux-2.6.19.ref/arch/mips/mm/c-r4k.c linux-2.6.19/arch/mips/mm/c-r4k.c
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--- linux-2.6.19.ref/arch/mips/mm/c-r4k.c 2006-12-04 21:34:04.000000000 +0100
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+++ linux-2.6.19/arch/mips/mm/c-r4k.c 2006-12-04 21:34:09.000000000 +0100
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@@ -13,6 +13,15 @@
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#include <linux/mm.h>
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#include <linux/bitops.h>
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+#ifdef CONFIG_BCM947XX
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+#include "../bcm947xx/include/typedefs.h"
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+#include "../bcm947xx/include/sbconfig.h"
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+#include "../bcm947xx/include/mipsinc.h"
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+#undef MTC0
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+#undef MFC0
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+#undef cache_op
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+#include <asm/paccess.h>
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+#endif
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#include <asm/bcache.h>
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#include <asm/bootinfo.h>
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#include <asm/cache.h>
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@@ -29,6 +38,9 @@
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#include <asm/cacheflush.h> /* for run_uncached() */
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+/* For enabling BCM4710 cache workarounds */
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+int bcm4710 = 0;
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+
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/*
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* Special Variant of smp_call_function for use by cache functions:
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*
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@@ -93,6 +105,9 @@
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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+ if (bcm4710)
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+ r4k_blast_dcache_page = blast_dcache_page;
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+ else
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if (dc_lsize == 0)
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r4k_blast_dcache_page = (void *)cache_noop;
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else if (dc_lsize == 16)
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@@ -107,6 +122,9 @@
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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+ if (bcm4710)
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+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
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+ else
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if (dc_lsize == 0)
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r4k_blast_dcache_page_indexed = (void *)cache_noop;
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else if (dc_lsize == 16)
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@@ -121,6 +139,9 @@
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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+ if (bcm4710)
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+ r4k_blast_dcache = blast_dcache;
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+ else
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if (dc_lsize == 0)
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r4k_blast_dcache = (void *)cache_noop;
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else if (dc_lsize == 16)
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@@ -538,6 +559,9 @@
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r4k_blast_icache();
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else
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protected_blast_icache_range(start, end);
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+
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+ if (bcm4710)
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+ r4k_flush_cache_all();
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}
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static void r4k_flush_icache_range(unsigned long start, unsigned long end)
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@@ -618,6 +642,8 @@
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unsigned long addr = (unsigned long) arg;
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R4600_HIT_CACHEOP_WAR_IMPL;
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+ BCM4710_PROTECTED_FILL_TLB(addr);
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+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
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if (dc_lsize)
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protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
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if (!cpu_icache_snoops_remote_store && scache_size)
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@@ -1135,6 +1161,16 @@
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static void __init coherency_setup(void)
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{
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change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
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+#ifdef CONFIG_BCM947XX
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+ if (BCM330X(current_cpu_data.processor_id)) {
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+ __u32 cm = read_c0_diag();
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+ /* Enable icache */
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+ cm |= (1 << 31);
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+ /* Enable dcache */
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+ cm |= (1 << 30);
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+ write_c0_diag(cm);
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+ }
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+#endif
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/*
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* c0_status.cu=0 specifies that updates by the sc instruction use
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@@ -1173,6 +1209,15 @@
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/* Default cache error handler for R4000 and R5000 family */
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set_uncached_handler (0x100, &except_vec2_generic, 0x80);
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+
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+ /* Check if special workarounds are required */
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+#ifdef CONFIG_BCM947XX
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+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
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+ printk("Enabling BCM4710A0 cache workarounds.\n");
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+ bcm4710 = 1;
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+ } else
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+#endif
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+ bcm4710 = 0;
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probe_pcache();
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setup_scache();
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diff -urN linux-2.6.19.ref/arch/mips/mm/tlbex.c linux-2.6.19/arch/mips/mm/tlbex.c
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--- linux-2.6.19.ref/arch/mips/mm/tlbex.c 2006-12-04 21:33:48.000000000 +0100
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+++ linux-2.6.19/arch/mips/mm/tlbex.c 2006-12-04 21:34:09.000000000 +0100
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@@ -1174,6 +1174,10 @@
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#endif
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}
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+#ifdef CONFIG_BCM947XX
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+extern int bcm4710;
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+#endif
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+
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static void __init build_r4000_tlb_refill_handler(void)
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{
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u32 *p = tlb_handler;
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@@ -1188,6 +1192,12 @@
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memset(relocs, 0, sizeof(relocs));
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memset(final_handler, 0, sizeof(final_handler));
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+#ifdef CONFIG_BCM947XX
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+ if (bcm4710) {
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+ i_nop(&p);
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+ }
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+#endif
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+
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/*
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* create the plain linear handler
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*/
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diff -urN linux-2.6.19.ref/include/asm-mips/r4kcache.h linux-2.6.19/include/asm-mips/r4kcache.h
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--- linux-2.6.19.ref/include/asm-mips/r4kcache.h 2006-11-29 22:57:37.000000000 +0100
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+++ linux-2.6.19/include/asm-mips/r4kcache.h 2006-12-04 21:34:09.000000000 +0100
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@@ -17,6 +17,18 @@
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#include <asm/cpu-features.h>
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#include <asm/mipsmtregs.h>
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+#ifdef CONFIG_BCM947XX
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+#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
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+
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+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
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+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
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+#else
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+#define BCM4710_DUMMY_RREG()
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+
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+#define BCM4710_FILL_TLB(addr)
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+#define BCM4710_PROTECTED_FILL_TLB(addr)
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+#endif
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+
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/*
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* This macro return a properly sign-extended address suitable as base address
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* for indexed cache operations. Two issues here:
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@@ -150,6 +162,7 @@
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static inline void flush_dcache_line_indexed(unsigned long addr)
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{
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__dflush_prologue
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+ BCM4710_DUMMY_RREG();
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cache_op(Index_Writeback_Inv_D, addr);
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__dflush_epilogue
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}
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@@ -169,6 +182,7 @@
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static inline void flush_dcache_line(unsigned long addr)
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{
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__dflush_prologue
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+ BCM4710_DUMMY_RREG();
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cache_op(Hit_Writeback_Inv_D, addr);
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__dflush_epilogue
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}
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@@ -176,6 +190,7 @@
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static inline void invalidate_dcache_line(unsigned long addr)
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{
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__dflush_prologue
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+ BCM4710_DUMMY_RREG();
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cache_op(Hit_Invalidate_D, addr);
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__dflush_epilogue
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}
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@@ -208,6 +223,7 @@
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*/
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static inline void protected_flush_icache_line(unsigned long addr)
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{
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+ BCM4710_DUMMY_RREG();
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protected_cache_op(Hit_Invalidate_I, addr);
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}
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@@ -219,6 +235,7 @@
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*/
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static inline void protected_writeback_dcache_line(unsigned long addr)
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{
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+ BCM4710_DUMMY_RREG();
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protected_cache_op(Hit_Writeback_Inv_D, addr);
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}
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@@ -339,8 +356,52 @@
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: "r" (base), \
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"i" (op));
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+static inline void blast_dcache(void)
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+{
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+ unsigned long start = KSEG0;
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+ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
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+ unsigned long end = (start + dcache_size);
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+
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+ do {
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+ BCM4710_DUMMY_RREG();
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+ cache_op(Index_Writeback_Inv_D, start);
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+ start += current_cpu_data.dcache.linesz;
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+ } while(start < end);
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+}
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+
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+static inline void blast_dcache_page(unsigned long page)
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+{
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+ unsigned long start = page;
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+ unsigned long end = start + PAGE_SIZE;
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+
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+ BCM4710_FILL_TLB(start);
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+ do {
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+ BCM4710_DUMMY_RREG();
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+ cache_op(Hit_Writeback_Inv_D, start);
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+ start += current_cpu_data.dcache.linesz;
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+ } while(start < end);
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+}
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+
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+static inline void blast_dcache_page_indexed(unsigned long page)
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+{
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+ unsigned long start = page;
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+ unsigned long end = start + PAGE_SIZE;
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+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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+ unsigned long ws_end = current_cpu_data.dcache.ways <<
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+ current_cpu_data.dcache.waybit;
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+ unsigned long ws, addr;
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+ for (ws = 0; ws < ws_end; ws += ws_inc) {
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+ start = page + ws;
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+ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
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+ BCM4710_DUMMY_RREG();
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+ cache_op(Index_Writeback_Inv_D, addr);
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+ }
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+ }
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+}
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+
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+
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/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
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-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
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+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
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static inline void blast_##pfx##cache##lsize(void) \
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{ \
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unsigned long start = INDEX_BASE; \
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@@ -352,6 +413,7 @@
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\
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__##pfx##flush_prologue \
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\
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+ war \
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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for (addr = start; addr < end; addr += lsize * 32) \
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cache##lsize##_unroll32(addr|ws,indexop); \
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@@ -366,6 +428,7 @@
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\
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__##pfx##flush_prologue \
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\
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+ war \
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do { \
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cache##lsize##_unroll32(start,hitop); \
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start += lsize * 32; \
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@@ -384,6 +447,8 @@
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current_cpu_data.desc.waybit; \
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unsigned long ws, addr; \
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\
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+ war \
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+ \
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__##pfx##flush_prologue \
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\
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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@@ -393,28 +458,30 @@
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__##pfx##flush_epilogue \
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}
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-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
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-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
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-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
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-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
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-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
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-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
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-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
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-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
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-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
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+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
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+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
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+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
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+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
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+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
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+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
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+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
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+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
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+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
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/* build blast_xxx_range, protected_blast_xxx_range */
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-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
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+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
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static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
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unsigned long end) \
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{ \
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unsigned long lsize = cpu_##desc##_line_size(); \
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unsigned long addr = start & ~(lsize - 1); \
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unsigned long aend = (end - 1) & ~(lsize - 1); \
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+ war \
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\
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__##pfx##flush_prologue \
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\
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while (1) { \
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+ war2 \
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prot##cache_op(hitop, addr); \
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if (addr == aend) \
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break; \
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@@ -424,13 +491,13 @@
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__##pfx##flush_epilogue \
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}
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-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
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-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
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-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
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-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
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-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
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+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
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+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
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+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
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+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
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+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
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/* blast_inv_dcache_range */
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-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
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-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
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+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
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+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
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#endif /* _ASM_R4KCACHE_H */
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diff -urN linux-2.6.19.ref/include/asm-mips/stackframe.h linux-2.6.19/include/asm-mips/stackframe.h
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--- linux-2.6.19.ref/include/asm-mips/stackframe.h 2006-11-29 22:57:37.000000000 +0100
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+++ linux-2.6.19/include/asm-mips/stackframe.h 2006-12-04 21:34:09.000000000 +0100
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@@ -334,6 +334,10 @@
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.macro RESTORE_SP_AND_RET
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LONG_L sp, PT_R29(sp)
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.set mips3
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+#ifdef CONFIG_BCM947XX
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+ nop
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+ nop
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+#endif
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eret
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.set mips0
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.endm
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