mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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ad91de86f5
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@11523 3c298f89-4303-0410-b956-a3cf2f4a3e73
171 lines
5.0 KiB
Diff
171 lines
5.0 KiB
Diff
From 2b2b8e163d28646cbbfde81c900fbb57d6572a11 Mon Sep 17 00:00:00 2001
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From: Axel Gembe <ago@bastart.eu.org>
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Date: Thu, 15 May 2008 11:00:43 +0200
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Subject: [PATCH] bcm963xx: board support
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Signed-off-by: Axel Gembe <ago@bastart.eu.org>
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---
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arch/mips/Kconfig | 11 +++++++++++
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arch/mips/Makefile | 4 ++++
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arch/mips/kernel/cpu-probe.c | 16 ++++++++++++++++
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arch/mips/mm/c-r4k.c | 7 +++++++
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arch/mips/mm/tlbex.c | 4 ++++
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arch/mips/pci/Makefile | 1 +
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include/asm-mips/bootinfo.h | 12 ++++++++++++
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include/asm-mips/cpu.h | 7 ++++++-
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8 files changed, 61 insertions(+), 1 deletions(-)
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--- a/arch/mips/Kconfig
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+++ b/arch/mips/Kconfig
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@@ -59,6 +59,17 @@
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help
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Support for BCM47XX based boards
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+config BCM963XX
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+ bool "Support for Broadcom BCM963xx SoC"
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+ select SYS_SUPPORTS_32BIT_KERNEL
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+ select SYS_SUPPORTS_BIG_ENDIAN
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+ select SYS_HAS_CPU_MIPS32_R1
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+ select HW_HAS_PCI
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+ select DMA_NONCOHERENT
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+ select IRQ_CPU
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+ help
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+ This is a fmaily of boards based on the Broadcom MIPS32
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+
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config MIPS_COBALT
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bool "Cobalt Server"
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select CEVT_R4K
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--- a/arch/mips/Makefile
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+++ b/arch/mips/Makefile
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@@ -560,6 +560,10 @@
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cflags-$(CONFIG_BCM47XX) += -Iinclude/asm-mips/mach-bcm47xx
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load-$(CONFIG_BCM47XX) := 0xffffffff80001000
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+core-$(CONFIG_BCM963XX) += arch/mips/bcm963xx/
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+cflags-$(CONFIG_BCM963XX) += -Iinclude/asm-mips/mach-bcm963xx
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+load-$(CONFIG_BCM963XX) := 0xffffffff8001000
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+
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#
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# SNI RM
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#
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--- a/arch/mips/kernel/cpu-probe.c
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+++ b/arch/mips/kernel/cpu-probe.c
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@@ -803,6 +803,21 @@
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case PRID_IMP_BCM4710:
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c->cputype = CPU_BCM4710;
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break;
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+// case PRID_IMP_BCM6338:
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+// c->cputype = CPU_BCM6338;
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+// break;
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+ case PRID_IMP_BCM6345:
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+ c->cputype = CPU_BCM6345;
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+ break;
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+ case PRID_IMP_BCM6348:
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+ c->cputype = CPU_BCM6348;
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+ break;
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+ case PRID_IMP_BCM6358:
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+ c->cputype = CPU_BCM6358;
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+ break;
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+ case PRID_IMP_BCM3350:
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+ c->cputype = CPU_BCM3350;
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+ break;
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default:
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c->cputype = CPU_UNKNOWN;
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break;
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@@ -887,6 +902,11 @@
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case CPU_SR71000: name = "Sandcraft SR71000"; break;
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case CPU_BCM3302: name = "Broadcom BCM3302"; break;
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case CPU_BCM4710: name = "Broadcom BCM4710"; break;
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+ case CPU_BCM6338: name = "Broadcom BCM6338"; break;
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+ case CPU_BCM6345: name = "Broadcom BCM6345"; break;
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+ case CPU_BCM6348: name = "Broadcom BCM6348"; break;
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+ case CPU_BCM6358: name = "Broadcom BCM6358"; break;
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+ case CPU_BCM3350: name = "Broadcom BCM3350"; break;
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case CPU_PR4450: name = "Philips PR4450"; break;
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case CPU_LOONGSON2: name = "ICT Loongson-2"; break;
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default:
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--- a/arch/mips/mm/c-r4k.c
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+++ b/arch/mips/mm/c-r4k.c
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@@ -882,6 +882,13 @@
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if (!(config & MIPS_CONF_M))
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panic("Don't know how to probe P-caches on this cpu.");
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+ if (c->cputype == CPU_BCM6338 || c->cputype == CPU_BCM6345 || c->cputype == CPU_BCM6348 || c->cputype == CPU_BCM6358 || c->cputype == CPU_BCM3350)
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+ {
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+ printk("bcm963xx: enabling icache and dcache...\n");
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+ /* Enable caches */
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+ write_c0_diag(read_c0_diag() | 0xC0000000);
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+ }
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+
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/*
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* So we seem to be a MIPS32 or MIPS64 CPU
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* So let's probe the I-cache ...
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--- a/arch/mips/mm/tlbex.c
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+++ b/arch/mips/mm/tlbex.c
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@@ -315,6 +315,11 @@
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case CPU_25KF:
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case CPU_BCM3302:
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case CPU_BCM4710:
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+// case CPU_BCM6338:
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+ case CPU_BCM6345:
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+ case CPU_BCM6348:
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+ case CPU_BCM6358:
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+ case CPU_BCM3350:
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case CPU_LOONGSON2:
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if (m4kc_tlbp_war())
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uasm_i_nop(p);
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--- a/arch/mips/pci/Makefile
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+++ b/arch/mips/pci/Makefile
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@@ -48,3 +48,4 @@
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obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
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obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
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obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
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+obj-$(CONFIG_BCM963XX) += fixup-bcm96348.o pci-bcm96348.o ops-bcm96348.o
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--- a/include/asm-mips/bootinfo.h
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+++ b/include/asm-mips/bootinfo.h
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@@ -94,6 +94,19 @@
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#define MACH_MSP7120_FPGA 5 /* PMC-Sierra MSP7120 Emulation */
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#define MACH_MSP_OTHER 255 /* PMC-Sierra unknown board type */
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+#define MACH_WRPPMC 1
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+
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+/*
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+ * Valid machtype for group Broadcom
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+ */
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+#define MACH_GROUP_BRCM 23 /* Broadcom */
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+#define MACH_BCM47XX 1 /* Broadcom BCM47XX */
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+#define MACH_BCM96338 2
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+#define MACH_BCM96345 3
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+#define MACH_BCM96348 4
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+#define MACH_BCM96358 5
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+#define MACH_BCM3350 6
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+
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#define CL_SIZE COMMAND_LINE_SIZE
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extern char *system_type;
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--- a/include/asm-mips/cpu.h
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+++ b/include/asm-mips/cpu.h
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@@ -111,6 +111,11 @@
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#define PRID_IMP_BCM4710 0x4000
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#define PRID_IMP_BCM3302 0x9000
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+//#define PRID_IMP_BCM6338 0x9000
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+#define PRID_IMP_BCM6345 0x8000
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+#define PRID_IMP_BCM6348 0x9100
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+#define PRID_IMP_BCM6358 0xA000
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+#define PRID_IMP_BCM3350 0x28000
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/*
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* Definitions for 7:0 on legacy processors
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@@ -196,7 +201,8 @@
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*/
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CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_74K, CPU_AU1000,
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CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, CPU_AU1550,
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- CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
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+ CPU_PR4450, CPU_BCM3302, CPU_BCM4710, CPU_BCM6338, CPU_BCM6345, CPU_BCM6348,
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+ CPU_BCM6358, CPU_BCM3350,
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/*
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* MIPS64 class processors
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