mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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e0b80e41eb
Tested on the following boards: ALFA AP96 TL-MR3220 v1 TL-WR1043ND v1 TL-WR2543ND v1 TL-WR703N v1 TL-WR741ND v1 TL-WR741ND v4 WNDR3700 v1 WZR-HP-G300NH git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29868 3c298f89-4303-0410-b956-a3cf2f4a3e73
220 lines
9.5 KiB
Diff
220 lines
9.5 KiB
Diff
From 2e535c334018d58b0bf6df583486abda5bfb2003 Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Fri, 18 Nov 2011 22:25:30 +0100
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Subject: [PATCH 10/35] MIPS: ath79: fix broken ar724x_pci_{read,write} functions
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The current ar724x_pci_{read,write} functions are
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broken. Due to that, pci_read_config_byte returns
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with bogus values, and pci_write_config_{byte,word}
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unconditionally clears the accessed PCI configuration
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registers instead of changing the value of them.
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The patch fixes the broken functions, thus the PCI
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configuration space can be accessed correctly.
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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v2: - no changes
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Output of 'lspci -vv' without the patch:
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00:00.0 Network controller: Atheros Communications Inc. AR9285 Wireless
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Network Adapter (PCI-Express) (rev 01)
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Subsystem: Atheros Communications Inc. Device a091
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Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
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Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
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Latency: 0
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Interrupt: pin A routed to IRQ 0
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Region 0: Memory at 10000000 (64-bit, non-prefetchable) [size=64K]
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Capabilities: [40] Power Management version 3
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Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold-)
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Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
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Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit-
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Address: 00000000 Data: 0000
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Capabilities: [60] Express (v2) Legacy Endpoint, MSI 00
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DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
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ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
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DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
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RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
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MaxPayload 128 bytes, MaxReadReq 512 bytes
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DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
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LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM unknown, Latency L0 <512ns, L1 <64us
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ClockPM- Surprise- LLActRep- BwNot-
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LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
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ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
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LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
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DevCap2: Completion Timeout: Not Supported, TimeoutDis+
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DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
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LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
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Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
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Compliance De-emphasis: -6dB
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LnkSta2: Current De-emphasis Level: -6dB
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Output of 'lspci -vv' with the patch:
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00:00.0 Network controller: Atheros Communications Inc. AR9285 Wireless
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Network Adapter (PCI-Express) (rev 01)
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Subsystem: Atheros Communications Inc. Device a091
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Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
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Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
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Latency: 0
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Interrupt: pin A routed to IRQ 48
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Region 0: Memory at 10000000 (64-bit, non-prefetchable) [size=64K]
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Capabilities: [40] Power Management version 3
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Flags: PMEClk- DSI- D1+ D2- AuxCurrent=375mA PME(D0+,D1+,D2-,D3hot+,D3cold-)
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Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
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Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit-
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Address: 00000000 Data: 0000
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Capabilities: [60] Express (v2) Legacy Endpoint, MSI 00
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DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <512ns, L1 <64us
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ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
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DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
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RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
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MaxPayload 128 bytes, MaxReadReq 512 bytes
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DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
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LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM unknown, Latency L0 <512ns, L1 <64us
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ClockPM- Surprise- LLActRep- BwNot-
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LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk-
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ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
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LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
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DevCap2: Completion Timeout: Not Supported, TimeoutDis+
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DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-
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LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
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Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
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Compliance De-emphasis: -6dB
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LnkSta2: Current De-emphasis Level: -6dB
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Capabilities: [100 v1] Advanced Error Reporting
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UESta: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
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UEMsk: DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
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UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
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CESta: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
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CEMsk: RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
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AERCap: First Error Pointer: 00, GenCap+ CGenEn- ChkCap+ ChkEn-
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Capabilities: [140 v1] Virtual Channel
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Caps: LPEVC=0 RefClk=100ns PATEntryBits=1
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Arb: Fixed- WRR32- WRR64- WRR128-
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Ctrl: ArbSelect=Fixed
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Status: InProgress-
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VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
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Arb: Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
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Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
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Status: NegoPending- InProgress-
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Capabilities: [160 v1] Device Serial Number 00-15-17-ff-ff-24-14-12
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Capabilities: [170 v1] Power Budgeting <?>
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---
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arch/mips/pci/pci-ar724x.c | 52 ++++++++++++++++++++++----------------------
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1 files changed, 26 insertions(+), 26 deletions(-)
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--- a/arch/mips/pci/pci-ar724x.c
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+++ b/arch/mips/pci/pci-ar724x.c
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@@ -22,8 +22,9 @@ static void __iomem *ar724x_pci_devcfg_b
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static int ar724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t *value)
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{
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- unsigned long flags, addr, tval, mask;
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+ unsigned long flags;
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void __iomem *base;
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+ u32 data;
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if (devfn)
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return PCIBIOS_DEVICE_NOT_FOUND;
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@@ -31,24 +32,22 @@ static int ar724x_pci_read(struct pci_bu
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base = ar724x_pci_devcfg_base;
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spin_lock_irqsave(&ar724x_pci_lock, flags);
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+ data = __raw_readl(base + (where & ~3));
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switch (size) {
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case 1:
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- addr = where & ~3;
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- mask = 0xff000000 >> ((where % 4) * 8);
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- tval = __raw_readl(base + addr);
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- tval = tval & ~mask;
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- *value = (tval >> ((4 - (where % 4))*8));
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+ if (where & 1)
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+ data >>= 8;
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+ if (where & 2)
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+ data >>= 16;
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+ data &= 0xff;
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break;
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case 2:
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- addr = where & ~3;
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- mask = 0xffff0000 >> ((where % 4)*8);
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- tval = __raw_readl(base + addr);
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- tval = tval & ~mask;
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- *value = (tval >> ((4 - (where % 4))*8));
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+ if (where & 2)
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+ data >>= 16;
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+ data &= 0xffff;
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break;
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case 4:
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- *value = __raw_readl(base + where);
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break;
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default:
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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@@ -57,6 +56,7 @@ static int ar724x_pci_read(struct pci_bu
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}
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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+ *value = data;
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return PCIBIOS_SUCCESSFUL;
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}
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@@ -64,8 +64,10 @@ static int ar724x_pci_read(struct pci_bu
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static int ar724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
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int size, uint32_t value)
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{
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- unsigned long flags, tval, addr, mask;
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+ unsigned long flags;
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void __iomem *base;
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+ u32 data;
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+ int s;
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if (devfn)
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return PCIBIOS_DEVICE_NOT_FOUND;
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@@ -73,26 +75,21 @@ static int ar724x_pci_write(struct pci_b
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base = ar724x_pci_devcfg_base;
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spin_lock_irqsave(&ar724x_pci_lock, flags);
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+ data = __raw_readl(base + (where & ~3));
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switch (size) {
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case 1:
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- addr = where & ~3;
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- mask = 0xff000000 >> ((where % 4)*8);
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- tval = __raw_readl(base + addr);
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- tval = tval & ~mask;
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- tval |= (value << ((4 - (where % 4))*8)) & mask;
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- __raw_writel(tval, base + addr);
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+ s = ((where & 3) * 8);
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+ data &= ~(0xff << s);
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+ data |= ((value & 0xff) << s);
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break;
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case 2:
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- addr = where & ~3;
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- mask = 0xffff0000 >> ((where % 4)*8);
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- tval = __raw_readl(base + addr);
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- tval = tval & ~mask;
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- tval |= (value << ((4 - (where % 4))*8)) & mask;
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- __raw_writel(tval, base + addr);
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+ s = ((where & 2) * 8);
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+ data &= ~(0xffff << s);
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+ data |= ((value & 0xffff) << s);
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break;
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case 4:
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- __raw_writel(value, (base + where));
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+ data = value;
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break;
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default:
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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@@ -100,6 +97,9 @@ static int ar724x_pci_write(struct pci_b
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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+ __raw_writel(data, base + (where & ~3));
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+ /* flush write */
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+ __raw_readl(base + (where & ~3));
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spin_unlock_irqrestore(&ar724x_pci_lock, flags);
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return PCIBIOS_SUCCESSFUL;
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