mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-10 00:45:21 +02:00
e056550af0
patch from Peter Wagner git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27104 3c298f89-4303-0410-b956-a3cf2f4a3e73
373 lines
11 KiB
Diff
373 lines
11 KiB
Diff
From bd620ec1ca053bab8ce2562968700e6f80e4ff83 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 6 May 2011 00:10:00 +0200
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Subject: [PATCH 10/13] MIPS: Lantiq: Add DMA support
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This patch adds support for the DMA engine found inside the XWAY family of
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SoCs. The engine has 5 ports and 20 channels.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com>
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Cc: linux-mips@linux-mips.org
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Patchwork: https://patchwork.linux-mips.org/patch/2355/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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---
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.../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +-
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arch/mips/include/asm/mach-lantiq/xway/xway_dma.h | 60 +++++
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arch/mips/lantiq/xway/Makefile | 2 +-
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arch/mips/lantiq/xway/devices.h | 1 +
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arch/mips/lantiq/xway/dma.c | 253 ++++++++++++++++++++
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5 files changed, 317 insertions(+), 2 deletions(-)
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create mode 100644 arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
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create mode 100644 arch/mips/lantiq/xway/dma.c
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--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
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@@ -86,7 +86,8 @@
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#define LTQ_PPE32_SIZE 0x40000
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/* DMA */
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-#define LTQ_DMA_BASE_ADDR 0xBE104100
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+#define LTQ_DMA_BASE_ADDR 0x1E104100
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+#define LTQ_DMA_SIZE 0x800
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/* PCI */
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#define PCI_CR_BASE_ADDR 0x1E105400
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
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@@ -0,0 +1,60 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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+ *
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+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#ifndef LTQ_DMA_H__
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+#define LTQ_DMA_H__
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+
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+#define LTQ_DESC_SIZE 0x08 /* each descriptor is 64bit */
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+#define LTQ_DESC_NUM 0x40 /* 64 descriptors / channel */
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+
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+#define LTQ_DMA_OWN BIT(31) /* owner bit */
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+#define LTQ_DMA_C BIT(30) /* complete bit */
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+#define LTQ_DMA_SOP BIT(29) /* start of packet */
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+#define LTQ_DMA_EOP BIT(28) /* end of packet */
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+#define LTQ_DMA_TX_OFFSET(x) ((x & 0x1f) << 23) /* data bytes offset */
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+#define LTQ_DMA_RX_OFFSET(x) ((x & 0x7) << 23) /* data bytes offset */
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+#define LTQ_DMA_SIZE_MASK (0xffff) /* the size field is 16 bit */
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+
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+struct ltq_dma_desc {
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+ u32 ctl;
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+ u32 addr;
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+};
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+
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+struct ltq_dma_channel {
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+ int nr; /* the channel number */
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+ int irq; /* the mapped irq */
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+ int desc; /* the current descriptor */
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+ struct ltq_dma_desc *desc_base; /* the descriptor base */
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+ int phys; /* physical addr */
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+};
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+
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+enum {
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+ DMA_PORT_ETOP = 0,
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+ DMA_PORT_DEU,
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+};
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+
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+extern void ltq_dma_enable_irq(struct ltq_dma_channel *ch);
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+extern void ltq_dma_disable_irq(struct ltq_dma_channel *ch);
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+extern void ltq_dma_ack_irq(struct ltq_dma_channel *ch);
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+extern void ltq_dma_open(struct ltq_dma_channel *ch);
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+extern void ltq_dma_close(struct ltq_dma_channel *ch);
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+extern void ltq_dma_alloc_tx(struct ltq_dma_channel *ch);
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+extern void ltq_dma_alloc_rx(struct ltq_dma_channel *ch);
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+extern void ltq_dma_free(struct ltq_dma_channel *ch);
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+extern void ltq_dma_init_port(int p);
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+
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+#endif
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--- a/arch/mips/lantiq/xway/Makefile
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+++ b/arch/mips/lantiq/xway/Makefile
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@@ -1,4 +1,4 @@
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-obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o
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+obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
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obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o
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obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o
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--- a/arch/mips/lantiq/xway/devices.h
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+++ b/arch/mips/lantiq/xway/devices.h
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@@ -10,6 +10,7 @@
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#define _LTQ_DEVICES_XWAY_H__
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#include "../devices.h"
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+#include <linux/phy.h>
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extern void ltq_register_gpio(void);
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extern void ltq_register_gpio_stp(void);
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--- /dev/null
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+++ b/arch/mips/lantiq/xway/dma.c
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@@ -0,0 +1,253 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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+ *
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+ * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
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+ */
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+
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+#include <linux/init.h>
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+#include <linux/platform_device.h>
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+#include <linux/io.h>
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+#include <linux/dma-mapping.h>
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+
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+#include <lantiq_soc.h>
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+#include <xway_dma.h>
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+
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+#define LTQ_DMA_CTRL 0x10
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+#define LTQ_DMA_CPOLL 0x14
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+#define LTQ_DMA_CS 0x18
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+#define LTQ_DMA_CCTRL 0x1C
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+#define LTQ_DMA_CDBA 0x20
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+#define LTQ_DMA_CDLEN 0x24
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+#define LTQ_DMA_CIS 0x28
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+#define LTQ_DMA_CIE 0x2C
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+#define LTQ_DMA_PS 0x40
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+#define LTQ_DMA_PCTRL 0x44
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+#define LTQ_DMA_IRNEN 0xf4
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+
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+#define DMA_DESCPT BIT(3) /* descriptor complete irq */
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+#define DMA_TX BIT(8) /* TX channel direction */
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+#define DMA_CHAN_ON BIT(0) /* channel on / off bit */
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+#define DMA_PDEN BIT(6) /* enable packet drop */
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+#define DMA_CHAN_RST BIT(1) /* channel on / off bit */
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+#define DMA_RESET BIT(0) /* channel on / off bit */
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+#define DMA_IRQ_ACK 0x7e /* IRQ status register */
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+#define DMA_POLL BIT(31) /* turn on channel polling */
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+#define DMA_CLK_DIV4 BIT(6) /* polling clock divider */
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+#define DMA_2W_BURST BIT(1) /* 2 word burst length */
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+#define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */
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+#define DMA_ETOP_ENDIANESS (0xf << 8) /* endianess swap etop channels */
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+#define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */
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+
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+#define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x))
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+#define ltq_dma_w32(x, y) ltq_w32(x, ltq_dma_membase + (y))
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+#define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \
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+ ltq_dma_membase + (z))
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+
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+static struct resource ltq_dma_resource = {
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+ .name = "dma",
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+ .start = LTQ_DMA_BASE_ADDR,
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+ .end = LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1,
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+ .flags = IORESOURCE_MEM,
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+};
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+
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+static void __iomem *ltq_dma_membase;
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+
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+void
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+ltq_dma_enable_irq(struct ltq_dma_channel *ch)
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+{
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+ unsigned long flags;
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+
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+ local_irq_save(flags);
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+ ltq_dma_w32(ch->nr, LTQ_DMA_CS);
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+ ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
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+ local_irq_restore(flags);
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+}
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+EXPORT_SYMBOL_GPL(ltq_dma_enable_irq);
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+
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+void
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+ltq_dma_disable_irq(struct ltq_dma_channel *ch)
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+{
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+ unsigned long flags;
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+
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+ local_irq_save(flags);
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+ ltq_dma_w32(ch->nr, LTQ_DMA_CS);
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+ ltq_dma_w32_mask(1 << ch->nr, 0, LTQ_DMA_IRNEN);
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+ local_irq_restore(flags);
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+}
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+EXPORT_SYMBOL_GPL(ltq_dma_disable_irq);
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+
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+void
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+ltq_dma_ack_irq(struct ltq_dma_channel *ch)
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+{
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+ unsigned long flags;
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+
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+ local_irq_save(flags);
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+ ltq_dma_w32(ch->nr, LTQ_DMA_CS);
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+ ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS);
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+ local_irq_restore(flags);
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+}
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+EXPORT_SYMBOL_GPL(ltq_dma_ack_irq);
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+
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+void
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+ltq_dma_open(struct ltq_dma_channel *ch)
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+{
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+ unsigned long flag;
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+
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+ local_irq_save(flag);
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+ ltq_dma_w32(ch->nr, LTQ_DMA_CS);
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+ ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL);
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+ ltq_dma_enable_irq(ch);
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+ local_irq_restore(flag);
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+}
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+EXPORT_SYMBOL_GPL(ltq_dma_open);
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+
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+void
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+ltq_dma_close(struct ltq_dma_channel *ch)
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+{
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+ unsigned long flag;
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+
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+ local_irq_save(flag);
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+ ltq_dma_w32(ch->nr, LTQ_DMA_CS);
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+ ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
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+ ltq_dma_disable_irq(ch);
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+ local_irq_restore(flag);
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+}
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+EXPORT_SYMBOL_GPL(ltq_dma_close);
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+
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+static void
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+ltq_dma_alloc(struct ltq_dma_channel *ch)
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+{
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+ unsigned long flags;
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+
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+ ch->desc = 0;
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+ ch->desc_base = dma_alloc_coherent(NULL,
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+ LTQ_DESC_NUM * LTQ_DESC_SIZE,
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+ &ch->phys, GFP_ATOMIC);
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+ memset(ch->desc_base, 0, LTQ_DESC_NUM * LTQ_DESC_SIZE);
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+
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+ local_irq_save(flags);
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+ ltq_dma_w32(ch->nr, LTQ_DMA_CS);
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+ ltq_dma_w32(ch->phys, LTQ_DMA_CDBA);
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+ ltq_dma_w32(LTQ_DESC_NUM, LTQ_DMA_CDLEN);
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+ ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
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+ wmb();
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+ ltq_dma_w32_mask(0, DMA_CHAN_RST, LTQ_DMA_CCTRL);
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+ while (ltq_dma_r32(LTQ_DMA_CCTRL) & DMA_CHAN_RST)
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+ ;
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+ local_irq_restore(flags);
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+}
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+
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+void
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+ltq_dma_alloc_tx(struct ltq_dma_channel *ch)
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+{
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+ unsigned long flags;
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+
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+ ltq_dma_alloc(ch);
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+
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+ local_irq_save(flags);
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+ ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
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+ ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
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+ ltq_dma_w32(DMA_WEIGHT | DMA_TX, LTQ_DMA_CCTRL);
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+ local_irq_restore(flags);
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+}
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+EXPORT_SYMBOL_GPL(ltq_dma_alloc_tx);
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+
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+void
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+ltq_dma_alloc_rx(struct ltq_dma_channel *ch)
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+{
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+ unsigned long flags;
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+
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+ ltq_dma_alloc(ch);
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+
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+ local_irq_save(flags);
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+ ltq_dma_w32(DMA_DESCPT, LTQ_DMA_CIE);
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+ ltq_dma_w32_mask(0, 1 << ch->nr, LTQ_DMA_IRNEN);
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+ ltq_dma_w32(DMA_WEIGHT, LTQ_DMA_CCTRL);
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+ local_irq_restore(flags);
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+}
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+EXPORT_SYMBOL_GPL(ltq_dma_alloc_rx);
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+
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+void
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+ltq_dma_free(struct ltq_dma_channel *ch)
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+{
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+ if (!ch->desc_base)
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+ return;
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+ ltq_dma_close(ch);
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+ dma_free_coherent(NULL, LTQ_DESC_NUM * LTQ_DESC_SIZE,
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+ ch->desc_base, ch->phys);
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+}
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+EXPORT_SYMBOL_GPL(ltq_dma_free);
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+
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+void
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+ltq_dma_init_port(int p)
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+{
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+ ltq_dma_w32(p, LTQ_DMA_PS);
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+ switch (p) {
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+ case DMA_PORT_ETOP:
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+ /*
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+ * Tell the DMA engine to swap the endianess of data frames and
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+ * drop packets if the channel arbitration fails.
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+ */
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+ ltq_dma_w32_mask(0, DMA_ETOP_ENDIANESS | DMA_PDEN,
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+ LTQ_DMA_PCTRL);
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+ break;
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+
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+ case DMA_PORT_DEU:
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+ ltq_dma_w32((DMA_2W_BURST << 4) | (DMA_2W_BURST << 2),
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+ LTQ_DMA_PCTRL);
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+ break;
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+
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+ default:
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+ break;
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+ }
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+}
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+EXPORT_SYMBOL_GPL(ltq_dma_init_port);
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+
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+int __init
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+ltq_dma_init(void)
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+{
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+ int i;
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+
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+ /* insert and request the memory region */
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+ if (insert_resource(&iomem_resource, <q_dma_resource) < 0)
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+ panic("Failed to insert dma memory\n");
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+
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+ if (request_mem_region(ltq_dma_resource.start,
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+ resource_size(<q_dma_resource), "dma") < 0)
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+ panic("Failed to request dma memory\n");
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+
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+ /* remap dma register range */
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+ ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start,
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+ resource_size(<q_dma_resource));
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+ if (!ltq_dma_membase)
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+ panic("Failed to remap dma memory\n");
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+
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+ /* power up and reset the dma engine */
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+ ltq_pmu_enable(PMU_DMA);
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+ ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);
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+
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+ /* disable all interrupts */
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+ ltq_dma_w32(0, LTQ_DMA_IRNEN);
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+
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+ /* reset/configure each channel */
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+ for (i = 0; i < DMA_MAX_CHANNEL; i++) {
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+ ltq_dma_w32(i, LTQ_DMA_CS);
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+ ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);
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+ ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
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+ ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
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+ }
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+ return 0;
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+}
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+
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+postcore_initcall(ltq_dma_init);
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