mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-12 12:06:49 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@8653 3c298f89-4303-0410-b956-a3cf2f4a3e73
644 lines
18 KiB
Diff
644 lines
18 KiB
Diff
Index: linux-2.6.22/arch/mips/kernel/genex.S
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===================================================================
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--- linux-2.6.22.orig/arch/mips/kernel/genex.S 2007-07-26 06:29:25.057170943 +0200
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+++ linux-2.6.22/arch/mips/kernel/genex.S 2007-07-26 06:29:40.890073208 +0200
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@@ -51,6 +51,10 @@
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NESTED(except_vec3_generic, 0, sp)
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.set push
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.set noat
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+#ifdef CONFIG_BCM947XX
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+ nop
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+ nop
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+#endif
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#if R5432_CP0_INTERRUPT_WAR
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mfc0 k0, CP0_INDEX
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#endif
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Index: linux-2.6.22/arch/mips/mm/c-r4k.c
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===================================================================
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--- linux-2.6.22.orig/arch/mips/mm/c-r4k.c 2007-07-26 06:29:40.826069560 +0200
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+++ linux-2.6.22/arch/mips/mm/c-r4k.c 2007-07-26 06:32:45.956619550 +0200
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@@ -29,6 +29,9 @@
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#include <asm/cacheflush.h> /* for run_uncached() */
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+/* For enabling BCM4710 cache workarounds */
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+int bcm4710 = 0;
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+
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/*
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* Special Variant of smp_call_function for use by cache functions:
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*
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@@ -85,14 +88,21 @@
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static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
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{
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+ unsigned long flags;
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+
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+ local_irq_save(flags);
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R4600_HIT_CACHEOP_WAR_IMPL;
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blast_dcache32_page(addr);
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+ local_irq_restore(flags);
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}
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static void __init r4k_blast_dcache_page_setup(void)
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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+ if (bcm4710)
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+ r4k_blast_dcache_page = blast_dcache_page;
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+ else
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if (dc_lsize == 0)
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r4k_blast_dcache_page = (void *)cache_noop;
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else if (dc_lsize == 16)
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@@ -107,6 +117,9 @@
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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+ if (bcm4710)
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+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
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+ else
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if (dc_lsize == 0)
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r4k_blast_dcache_page_indexed = (void *)cache_noop;
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else if (dc_lsize == 16)
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@@ -121,6 +134,9 @@
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{
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unsigned long dc_lsize = cpu_dcache_line_size();
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+ if (bcm4710)
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+ r4k_blast_dcache = blast_dcache;
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+ else
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if (dc_lsize == 0)
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r4k_blast_dcache = (void *)cache_noop;
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else if (dc_lsize == 16)
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@@ -202,8 +218,12 @@
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static void (* r4k_blast_icache_page)(unsigned long addr);
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+static void r4k_flush_cache_all(void);
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static void __init r4k_blast_icache_page_setup(void)
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{
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+#ifdef CONFIG_BCM947XX
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+ r4k_blast_icache_page = (void *)r4k_flush_cache_all;
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+#else
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unsigned long ic_lsize = cpu_icache_line_size();
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if (ic_lsize == 0)
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@@ -214,6 +234,7 @@
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r4k_blast_icache_page = blast_icache32_page;
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else if (ic_lsize == 64)
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r4k_blast_icache_page = blast_icache64_page;
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+#endif
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}
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@@ -221,6 +242,9 @@
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static void __init r4k_blast_icache_page_indexed_setup(void)
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{
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+#ifdef CONFIG_BCM947XX
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+ r4k_blast_icache_page_indexed = (void *)r4k_flush_cache_all;
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+#else
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unsigned long ic_lsize = cpu_icache_line_size();
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if (ic_lsize == 0)
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@@ -239,6 +263,7 @@
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blast_icache32_page_indexed;
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} else if (ic_lsize == 64)
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r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
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+#endif
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}
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static void (* r4k_blast_icache)(void);
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@@ -322,12 +347,17 @@
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*/
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static inline void local_r4k_flush_cache_all(void * args)
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{
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+ unsigned long flags;
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+
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+ local_irq_save(flags);
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r4k_blast_dcache();
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+ r4k_blast_icache();
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+ local_irq_restore(flags);
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}
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static void r4k_flush_cache_all(void)
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{
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- if (!cpu_has_dc_aliases)
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+ if (!cpu_has_dc_aliases && cpu_use_kmap_coherent)
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return;
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r4k_on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
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@@ -335,6 +365,9 @@
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static inline void local_r4k___flush_cache_all(void * args)
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{
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+ unsigned long flags;
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+
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+ local_irq_save(flags);
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r4k_blast_dcache();
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r4k_blast_icache();
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@@ -348,6 +381,7 @@
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case CPU_R14000:
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r4k_blast_scache();
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}
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+ local_irq_restore(flags);
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}
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static void r4k___flush_cache_all(void)
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@@ -358,17 +392,21 @@
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static inline void local_r4k_flush_cache_range(void * args)
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{
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struct vm_area_struct *vma = args;
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+ unsigned long flags;
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if (!(cpu_context(smp_processor_id(), vma->vm_mm)))
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return;
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+ local_irq_save(flags);
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r4k_blast_dcache();
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+ r4k_blast_icache();
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+ local_irq_restore(flags);
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}
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static void r4k_flush_cache_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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- if (!cpu_has_dc_aliases)
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+ if (!cpu_has_dc_aliases && cpu_use_kmap_coherent)
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return;
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r4k_on_each_cpu(local_r4k_flush_cache_range, vma, 1, 1);
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@@ -377,6 +415,7 @@
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static inline void local_r4k_flush_cache_mm(void * args)
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{
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struct mm_struct *mm = args;
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+ unsigned long flags;
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if (!cpu_context(smp_processor_id(), mm))
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return;
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@@ -395,12 +434,15 @@
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return;
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}
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+ local_irq_save(flags);
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r4k_blast_dcache();
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+ r4k_blast_icache();
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+ local_irq_restore(flags);
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}
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static void r4k_flush_cache_mm(struct mm_struct *mm)
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{
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- if (!cpu_has_dc_aliases)
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+ if (!cpu_has_dc_aliases && cpu_use_kmap_coherent)
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return;
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r4k_on_each_cpu(local_r4k_flush_cache_mm, mm, 1, 1);
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@@ -420,6 +462,7 @@
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unsigned long paddr = fcp_args->pfn << PAGE_SHIFT;
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int exec = vma->vm_flags & VM_EXEC;
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struct mm_struct *mm = vma->vm_mm;
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+ unsigned long flags;
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pgd_t *pgdp;
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pud_t *pudp;
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pmd_t *pmdp;
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@@ -451,8 +494,9 @@
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* for every cache flush operation. So we do indexed flushes
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* in that case, which doesn't overly flush the cache too much.
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*/
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+ local_irq_save(flags);
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if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) {
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- if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
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+ if (!cpu_use_kmap_coherent || cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
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r4k_blast_dcache_page(addr);
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if (exec && !cpu_icache_snoops_remote_store)
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r4k_blast_scache_page(addr);
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@@ -460,14 +504,14 @@
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if (exec)
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r4k_blast_icache_page(addr);
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- return;
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+ goto done;
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}
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/*
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* Do indexed flush, too much work to get the (possible) TLB refills
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* to work correctly.
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*/
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- if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
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+ if (!cpu_use_kmap_coherent || cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
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r4k_blast_dcache_page_indexed(cpu_has_pindexed_dcache ?
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paddr : addr);
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if (exec && !cpu_icache_snoops_remote_store) {
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@@ -483,6 +527,8 @@
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} else
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r4k_blast_icache_page_indexed(addr);
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}
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+done:
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+ local_irq_restore(flags);
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}
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static void r4k_flush_cache_page(struct vm_area_struct *vma,
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@@ -499,7 +545,11 @@
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static inline void local_r4k_flush_data_cache_page(void * addr)
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{
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+ unsigned long flags;
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+
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+ local_irq_save(flags);
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r4k_blast_dcache_page((unsigned long) addr);
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+ local_irq_restore(flags);
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}
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static void r4k_flush_data_cache_page(unsigned long addr)
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@@ -542,6 +592,9 @@
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static void r4k_flush_icache_range(unsigned long start, unsigned long end)
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{
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+#ifdef CONFIG_BCM947XX
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+ r4k_flush_cache_all();
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+#else
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struct flush_icache_range_args args;
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args.start = start;
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@@ -549,12 +602,15 @@
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r4k_on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
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instruction_hazard();
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+#endif
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}
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#ifdef CONFIG_DMA_NONCOHERENT
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static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
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{
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+ unsigned long flags;
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+
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/* Catch bad driver code */
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BUG_ON(size == 0);
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@@ -571,18 +627,21 @@
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* subset property so we have to flush the primary caches
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* explicitly
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*/
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+ local_irq_save(flags);
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if (size >= dcache_size) {
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r4k_blast_dcache();
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} else {
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R4600_HIT_CACHEOP_WAR_IMPL;
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blast_dcache_range(addr, addr + size);
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}
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-
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bc_wback_inv(addr, size);
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+ local_irq_restore(flags);
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}
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static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
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{
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+ unsigned long flags;
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+
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/* Catch bad driver code */
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BUG_ON(size == 0);
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@@ -594,6 +653,7 @@
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return;
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}
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+ local_irq_save(flags);
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if (size >= dcache_size) {
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r4k_blast_dcache();
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} else {
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@@ -602,6 +662,7 @@
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}
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bc_inv(addr, size);
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+ local_irq_restore(flags);
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}
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#endif /* CONFIG_DMA_NONCOHERENT */
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@@ -616,8 +677,12 @@
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unsigned long dc_lsize = cpu_dcache_line_size();
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unsigned long sc_lsize = cpu_scache_line_size();
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unsigned long addr = (unsigned long) arg;
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+ unsigned long flags;
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+ local_irq_save(flags);
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R4600_HIT_CACHEOP_WAR_IMPL;
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+ BCM4710_PROTECTED_FILL_TLB(addr);
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+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
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if (dc_lsize)
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protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
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if (!cpu_icache_snoops_remote_store && scache_size)
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@@ -644,6 +709,7 @@
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}
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if (MIPS_CACHE_SYNC_WAR)
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__asm__ __volatile__ ("sync");
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+ local_irq_restore(flags);
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}
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static void r4k_flush_cache_sigtramp(unsigned long addr)
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@@ -1144,6 +1210,17 @@
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* silly idea of putting something else there ...
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*/
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switch (current_cpu_data.cputype) {
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+ case CPU_BCM3302:
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+ {
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+ u32 cm;
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+ cm = read_c0_diag();
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+ /* Enable icache */
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+ cm |= (1 << 31);
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+ /* Enable dcache */
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+ cm |= (1 << 30);
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+ write_c0_diag(cm);
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+ }
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+ break;
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case CPU_R4000PC:
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case CPU_R4000SC:
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case CPU_R4000MC:
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@@ -1174,6 +1251,15 @@
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/* Default cache error handler for R4000 and R5000 family */
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set_uncached_handler (0x100, &except_vec2_generic, 0x80);
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+ /* Check if special workarounds are required */
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+#ifdef CONFIG_BCM947XX
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+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & 0xff) == 0) {
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+ printk("Enabling BCM4710A0 cache workarounds.\n");
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+ bcm4710 = 1;
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+ } else
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+#endif
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+ bcm4710 = 0;
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+
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probe_pcache();
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setup_scache();
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@@ -1219,5 +1305,13 @@
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build_clear_page();
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build_copy_page();
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local_r4k___flush_cache_all(NULL);
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+#ifdef CONFIG_BCM947XX
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+ {
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+ static void (*_coherency_setup)(void);
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+ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
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+ _coherency_setup();
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+ }
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+#else
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coherency_setup();
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+#endif
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}
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Index: linux-2.6.22/arch/mips/mm/tlbex.c
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===================================================================
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--- linux-2.6.22.orig/arch/mips/mm/tlbex.c 2007-07-26 06:29:40.582055658 +0200
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+++ linux-2.6.22/arch/mips/mm/tlbex.c 2007-07-26 06:32:45.964620005 +0200
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@@ -1229,6 +1229,10 @@
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#endif
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}
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+#ifdef CONFIG_BCM947XX
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+extern int bcm4710;
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+#endif
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+
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static void __init build_r4000_tlb_refill_handler(void)
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{
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u32 *p = tlb_handler;
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@@ -1243,6 +1247,10 @@
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memset(relocs, 0, sizeof(relocs));
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memset(final_handler, 0, sizeof(final_handler));
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+#ifdef CONFIG_BCM947XX
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+ i_nop(&p);
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+#endif
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+
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/*
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* create the plain linear handler
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*/
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@@ -1736,6 +1744,9 @@
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memset(labels, 0, sizeof(labels));
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memset(relocs, 0, sizeof(relocs));
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+#ifdef CONFIG_BCM947XX
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+ i_nop(&p);
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+#endif
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if (bcm1250_m3_war()) {
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i_MFC0(&p, K0, C0_BADVADDR);
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i_MFC0(&p, K1, C0_ENTRYHI);
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Index: linux-2.6.22/include/asm-mips/r4kcache.h
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===================================================================
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--- linux-2.6.22.orig/include/asm-mips/r4kcache.h 2007-07-26 06:29:25.085172538 +0200
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+++ linux-2.6.22/include/asm-mips/r4kcache.h 2007-07-26 06:29:40.938075943 +0200
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@@ -17,6 +17,20 @@
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#include <asm/cpu-features.h>
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#include <asm/mipsmtregs.h>
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+#ifdef CONFIG_BCM947XX
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+#include <asm/paccess.h>
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+#include <linux/ssb/ssb.h>
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+#define BCM4710_DUMMY_RREG() ((void) *((u8 *) KSEG1ADDR(SSB_ENUM_BASE + SSB_IMSTATE)))
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+
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+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
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+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
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+#else
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+#define BCM4710_DUMMY_RREG()
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+
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+#define BCM4710_FILL_TLB(addr)
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+#define BCM4710_PROTECTED_FILL_TLB(addr)
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+#endif
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+
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/*
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* This macro return a properly sign-extended address suitable as base address
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* for indexed cache operations. Two issues here:
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@@ -150,6 +164,7 @@
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static inline void flush_dcache_line_indexed(unsigned long addr)
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{
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__dflush_prologue
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+ BCM4710_DUMMY_RREG();
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cache_op(Index_Writeback_Inv_D, addr);
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__dflush_epilogue
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}
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@@ -169,6 +184,7 @@
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static inline void flush_dcache_line(unsigned long addr)
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{
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__dflush_prologue
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+ BCM4710_DUMMY_RREG();
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cache_op(Hit_Writeback_Inv_D, addr);
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__dflush_epilogue
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}
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@@ -176,6 +192,7 @@
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static inline void invalidate_dcache_line(unsigned long addr)
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{
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__dflush_prologue
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+ BCM4710_DUMMY_RREG();
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cache_op(Hit_Invalidate_D, addr);
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__dflush_epilogue
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}
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@@ -208,6 +225,7 @@
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*/
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static inline void protected_flush_icache_line(unsigned long addr)
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{
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+ BCM4710_DUMMY_RREG();
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protected_cache_op(Hit_Invalidate_I, addr);
|
|
}
|
|
|
|
@@ -219,6 +237,7 @@
|
|
*/
|
|
static inline void protected_writeback_dcache_line(unsigned long addr)
|
|
{
|
|
+ BCM4710_DUMMY_RREG();
|
|
protected_cache_op(Hit_Writeback_Inv_D, addr);
|
|
}
|
|
|
|
@@ -339,8 +358,52 @@
|
|
: "r" (base), \
|
|
"i" (op));
|
|
|
|
+static inline void blast_dcache(void)
|
|
+{
|
|
+ unsigned long start = KSEG0;
|
|
+ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
|
|
+ unsigned long end = (start + dcache_size);
|
|
+
|
|
+ do {
|
|
+ BCM4710_DUMMY_RREG();
|
|
+ cache_op(Index_Writeback_Inv_D, start);
|
|
+ start += current_cpu_data.dcache.linesz;
|
|
+ } while(start < end);
|
|
+}
|
|
+
|
|
+static inline void blast_dcache_page(unsigned long page)
|
|
+{
|
|
+ unsigned long start = page;
|
|
+ unsigned long end = start + PAGE_SIZE;
|
|
+
|
|
+ BCM4710_FILL_TLB(start);
|
|
+ do {
|
|
+ BCM4710_DUMMY_RREG();
|
|
+ cache_op(Hit_Writeback_Inv_D, start);
|
|
+ start += current_cpu_data.dcache.linesz;
|
|
+ } while(start < end);
|
|
+}
|
|
+
|
|
+static inline void blast_dcache_page_indexed(unsigned long page)
|
|
+{
|
|
+ unsigned long start = page;
|
|
+ unsigned long end = start + PAGE_SIZE;
|
|
+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
|
|
+ unsigned long ws_end = current_cpu_data.dcache.ways <<
|
|
+ current_cpu_data.dcache.waybit;
|
|
+ unsigned long ws, addr;
|
|
+ for (ws = 0; ws < ws_end; ws += ws_inc) {
|
|
+ start = page + ws;
|
|
+ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
|
|
+ BCM4710_DUMMY_RREG();
|
|
+ cache_op(Index_Writeback_Inv_D, addr);
|
|
+ }
|
|
+ }
|
|
+}
|
|
+
|
|
+
|
|
/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
|
|
-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
|
|
+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, war) \
|
|
static inline void blast_##pfx##cache##lsize(void) \
|
|
{ \
|
|
unsigned long start = INDEX_BASE; \
|
|
@@ -352,6 +415,7 @@
|
|
\
|
|
__##pfx##flush_prologue \
|
|
\
|
|
+ war \
|
|
for (ws = 0; ws < ws_end; ws += ws_inc) \
|
|
for (addr = start; addr < end; addr += lsize * 32) \
|
|
cache##lsize##_unroll32(addr|ws,indexop); \
|
|
@@ -366,6 +430,7 @@
|
|
\
|
|
__##pfx##flush_prologue \
|
|
\
|
|
+ war \
|
|
do { \
|
|
cache##lsize##_unroll32(start,hitop); \
|
|
start += lsize * 32; \
|
|
@@ -384,6 +449,8 @@
|
|
current_cpu_data.desc.waybit; \
|
|
unsigned long ws, addr; \
|
|
\
|
|
+ war \
|
|
+ \
|
|
__##pfx##flush_prologue \
|
|
\
|
|
for (ws = 0; ws < ws_end; ws += ws_inc) \
|
|
@@ -393,28 +460,30 @@
|
|
__##pfx##flush_epilogue \
|
|
}
|
|
|
|
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
|
|
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
|
|
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
|
|
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
|
|
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
|
|
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
|
|
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
|
|
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
|
|
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
|
|
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
|
|
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, BCM4710_FILL_TLB(start);)
|
|
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
|
|
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
|
|
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, BCM4710_FILL_TLB(start);)
|
|
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
|
|
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, BCM4710_FILL_TLB(start);)
|
|
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
|
|
+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
|
|
|
|
/* build blast_xxx_range, protected_blast_xxx_range */
|
|
-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
|
|
+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, war, war2) \
|
|
static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
|
|
unsigned long end) \
|
|
{ \
|
|
unsigned long lsize = cpu_##desc##_line_size(); \
|
|
unsigned long addr = start & ~(lsize - 1); \
|
|
unsigned long aend = (end - 1) & ~(lsize - 1); \
|
|
+ war \
|
|
\
|
|
__##pfx##flush_prologue \
|
|
\
|
|
while (1) { \
|
|
+ war2 \
|
|
prot##cache_op(hitop, addr); \
|
|
if (addr == aend) \
|
|
break; \
|
|
@@ -424,13 +493,13 @@
|
|
__##pfx##flush_epilogue \
|
|
}
|
|
|
|
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
|
|
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
|
|
-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
|
|
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
|
|
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
|
|
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
|
|
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_,, )
|
|
+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_,, )
|
|
+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D,, BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
|
|
+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD,,, )
|
|
/* blast_inv_dcache_range */
|
|
-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
|
|
-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
|
|
+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D,,,BCM4710_DUMMY_RREG();)
|
|
+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD,,, )
|
|
|
|
#endif /* _ASM_R4KCACHE_H */
|
|
Index: linux-2.6.22/include/asm-mips/stackframe.h
|
|
===================================================================
|
|
--- linux-2.6.22.orig/include/asm-mips/stackframe.h 2007-07-26 06:29:25.093172994 +0200
|
|
+++ linux-2.6.22/include/asm-mips/stackframe.h 2007-07-26 06:29:40.962077312 +0200
|
|
@@ -350,6 +350,10 @@
|
|
.macro RESTORE_SP_AND_RET
|
|
LONG_L sp, PT_R29(sp)
|
|
.set mips3
|
|
+#ifdef CONFIG_BCM947XX
|
|
+ nop
|
|
+ nop
|
|
+#endif
|
|
eret
|
|
.set mips0
|
|
.endm
|