mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-01 22:44:39 +02:00
b132f921be
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17997 3c298f89-4303-0410-b956-a3cf2f4a3e73
165 lines
4.7 KiB
Diff
165 lines
4.7 KiB
Diff
--- a/arch/arm/Kconfig
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+++ b/arch/arm/Kconfig
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@@ -384,7 +384,6 @@ config ARCH_IXP4XX
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select GENERIC_GPIO
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select GENERIC_TIME
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select GENERIC_CLOCKEVENTS
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- select DMABOUNCE if PCI
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help
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Support for Intel's IXP4XX (XScale) family of processors.
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--- a/arch/arm/mach-ixp4xx/Kconfig
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+++ b/arch/arm/mach-ixp4xx/Kconfig
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@@ -199,6 +199,45 @@ config IXP4XX_INDIRECT_PCI
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need to use the indirect method instead. If you don't know
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what you need, leave this option unselected.
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+config IXP4XX_LEGACY_DMABOUNCE
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+ bool "legacy PCI DMA bounce support"
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+ depends on PCI
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+ default n
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+ select DMABOUNCE
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+ help
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+ The IXP4xx is limited to a 64MB window for PCI DMA, which
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+ requires that PCI accesses above 64MB are bounced via buffers
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+ below 64MB. Furthermore the IXP4xx has an erratum where PCI
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+ read prefetches just below the 64MB limit can trigger lockups.
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+
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+ The kernel has traditionally handled these two issue by using
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+ ARM specific DMA bounce support code for all accesses >= 64MB.
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+ That code causes problems of its own, so it is desirable to
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+ disable it. As the kernel now has a workaround for the PCI read
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+ prefetch erratum, it no longer requires the ARM bounce code.
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+
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+ Enabling this option makes IXP4xx continue to use the problematic
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+ ARM DMA bounce code. Disabling this option makes IXP4xx use the
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+ kernel's generic bounce code.
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+
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+ Say 'N'.
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+
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+config IXP4XX_ZONE_DMA
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+ bool "Support > 64MB RAM"
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+ depends on !IXP4XX_LEGACY_DMABOUNCE
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+ default y
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+ select ZONE_DMA
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+ help
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+ The IXP4xx is limited to a 64MB window for PCI DMA, which
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+ requires that PCI accesses above 64MB are bounced via buffers
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+ below 64MB.
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+
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+ Disabling this option allows you to omit the support code for
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+ DMA-able memory allocations and DMA bouncing, but the kernel
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+ will then not work properly if more than 64MB of RAM is present.
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+
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+ Say 'Y' unless your platform is limited to <= 64MB of RAM.
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+
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config IXP4XX_QMGR
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tristate "IXP4xx Queue Manager support"
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help
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--- a/arch/arm/mach-ixp4xx/common-pci.c
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+++ b/arch/arm/mach-ixp4xx/common-pci.c
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@@ -321,27 +321,38 @@ static int abort_handler(unsigned long a
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*/
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static int ixp4xx_pci_platform_notify(struct device *dev)
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{
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- if(dev->bus == &pci_bus_type) {
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- *dev->dma_mask = SZ_64M - 1;
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+ if (dev->bus == &pci_bus_type) {
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+ *dev->dma_mask = SZ_64M - 1;
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dev->coherent_dma_mask = SZ_64M - 1;
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+#ifdef CONFIG_DMABOUNCE
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dmabounce_register_dev(dev, 2048, 4096);
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+#endif
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}
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return 0;
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}
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static int ixp4xx_pci_platform_notify_remove(struct device *dev)
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{
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- if(dev->bus == &pci_bus_type) {
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+#ifdef CONFIG_DMABOUNCE
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+ if (dev->bus == &pci_bus_type)
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dmabounce_unregister_dev(dev);
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- }
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+#endif
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return 0;
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}
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+#ifdef CONFIG_DMABOUNCE
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int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
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{
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+ /* Note that this returns true for the last page below 64M due to
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+ * IXP4xx erratum 15 (SCR 1289), which states that PCI prefetches
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+ * can cross the boundary between valid memory and a reserved region
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+ * causing AHB bus errors and a lock-up.
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+ */
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return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M);
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}
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+#endif
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+#ifdef CONFIG_ZONE_DMA
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/*
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* Only first 64MB of memory can be accessed via PCI.
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* We use GFP_DMA to allocate safe buffers to do map/unmap.
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@@ -364,6 +375,7 @@ void __init ixp4xx_adjust_zones(int node
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zhole_size[1] = zhole_size[0];
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zhole_size[0] = 0;
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}
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+#endif
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void __init ixp4xx_pci_preinit(void)
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{
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@@ -517,19 +529,35 @@ struct pci_bus * __devinit ixp4xx_scan_b
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int
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pci_set_dma_mask(struct pci_dev *dev, u64 mask)
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{
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- if (mask >= SZ_64M - 1 )
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+#ifdef CONFIG_DMABOUNCE
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+ if (mask >= SZ_64M - 1)
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return 0;
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return -EIO;
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+#else
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+ /* Only honour masks < SZ_64M. Silently ignore masks >= SZ_64M
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+ as generic drivers do not know about IXP4xx PCI DMA quirks. */
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+ if (mask < SZ_64M)
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+ dev->dma_mask = mask;
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+ return 0;
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+#endif
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}
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int
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pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
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{
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- if (mask >= SZ_64M - 1 )
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+#ifdef CONFIG_DMABOUNCE
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+ if (mask >= SZ_64M - 1)
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return 0;
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return -EIO;
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+#else
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+ /* Only honour masks < SZ_64M. Silently ignore masks >= SZ_64M
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+ as generic drivers do not know about IXP4xx PCI DMA quirks. */
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+ if (mask < SZ_64M)
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+ dev->dev.coherent_dma_mask = mask;
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+ return 0;
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+#endif
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}
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EXPORT_SYMBOL(ixp4xx_pci_read);
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--- a/arch/arm/mach-ixp4xx/include/mach/memory.h
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+++ b/arch/arm/mach-ixp4xx/include/mach/memory.h
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@@ -16,10 +16,12 @@
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#if !defined(__ASSEMBLY__) && defined(CONFIG_PCI)
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+#ifdef CONFIG_ZONE_DMA
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void ixp4xx_adjust_zones(int node, unsigned long *size, unsigned long *holes);
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#define arch_adjust_zones(node, size, holes) \
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ixp4xx_adjust_zones(node, size, holes)
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+#endif
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#define ISA_DMA_THRESHOLD (SZ_64M - 1)
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#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
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