mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-18 14:59:42 +02:00
fb2c10f9dc
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@21896 3c298f89-4303-0410-b956-a3cf2f4a3e73
436 lines
12 KiB
Diff
436 lines
12 KiB
Diff
--- /dev/null
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+++ b/arch/powerpc/boot/dts/rb333.dts
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@@ -0,0 +1,432 @@
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+
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+/*
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+ * RouterBOARD 333 series Device Tree Source
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+ *
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+ * Copyright 2010 Alexandros C. Couloumbis <alex@ozo.com>
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+ * Copyright 2009 Michael Guntsche <mike@it-loops.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ * Warning (reg_format): "reg" property in /qe@e0100000/muram@10000/data-only@0 has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1)
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+ * Warning (ranges_format): "ranges" property in /qe@e0100000/muram@10000 has invalid length (12 bytes) (parent #address-cells == 1, child #address-cells == 2, #size-cells == 1)
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+ * Warning (avoid_default_addr_size): Relying on default #address-cells value for /qe@e0100000/muram@10000/data-only@0
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+ * Warning (avoid_default_addr_size): Relying on default #size-cells value for /qe@e0100000/muram@10000/data-only@0
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+ * Warning (obsolete_chosen_interrupt_controller): /chosen has obsolete "interrupt-controller" property
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+ *
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+ */
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+
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+
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+/dts-v1/;
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+
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+/ {
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+ model = "RB333";
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+ compatible = "MPC83xx";
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+ #size-cells = <1>;
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+ #address-cells = <1>;
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+
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+
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+ aliases {
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+ ethernet0 = &enet0;
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+ ethernet1 = &enet1;
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+ ethernet2 = &enet2;
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+ pci0 = &pci0;
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+ };
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+
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+
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+ chosen {
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+ bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1";
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+ // linux,platform = <0x8062>;
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+ // linux,initrd = <0x488000 0x0>;
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+ linux,stdout-path = "/soc8323@e0000000/serial@4500";
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+ // interrupt-controller = <&ipic>;
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+ };
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+
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+ cpus {
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+ #cpus = <1>;
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+ #size-cells = <0>;
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+ #address-cells = <1>;
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+
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+ PowerPC,8323E@0 {
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+ device_type = "cpu";
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+ reg = <0x0>;
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+ i-cache-size = <0x4000>;
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+ d-cache-size = <0x4000>;
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+ i-cache-line-size = <0x20>;
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+ d-cache-line-size = <0x20>;
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+ // clock-frequency = <0x13de3650>;
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+ // timebase-frequency = <0x1fc9f08>;
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+ timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob
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+ clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob
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+ 32-bit;
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+ };
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+ };
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+
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+ memory {
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+ device_type = "memory";
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+ reg = <0x0 0x4000000>;
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+ // reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob
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+ };
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+
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+ flash {
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+ reg = <0xfe000000 0x20000>;
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+ };
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+
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+ nand {
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+ ale = <&gpio2 0x3>;
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+ cle = <&gpio2 0x2>;
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+ nce = <&gpio2 0x1>;
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+ rdy = <&gpio2 0x0>;
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+ reg = <0xf8000000 0x1000>;
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+ device_type = "rb,nand";
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+ };
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+
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+ nnand {
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+ reg = <0xf0000000 0x1000>;
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+ };
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+
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+ voltage {
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+ voltage_gpio = <&gpio3 0x11>;
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+ };
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+
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+ fancon {
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+ interrupt-parent = <&ipic>;
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+ interrupts = <0x14 0x8>;
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+ fan_on = <&gpio0 0x10>;
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+ };
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+
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+ pci0: pci@e0008500 {
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+ device_type = "pci";
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+ // compatible = "83xx";
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+ compatible = "fsl,mpc8349-pci";
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+ reg = <0xe0008500 0x100 0xe0008300 0x8>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ // clock-frequency = <0>;
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+ ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>;
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+ bus-range = <0x0 0x0>;
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+ interrupt-map = <
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+ /* IDSEL 0x10 AD16 miniPCI slot 0 */
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+ 0x8000 0x0 0x0 0x1 &ipic 0x11 0x8
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+ 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8
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+
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+ /* IDSEL 0x11 AD17 miniPCI slot 1 */
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+ 0x8800 0x0 0x0 0x1 &ipic 0x12 0x8
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+ 0x8800 0x0 0x0 0x2 &ipic 0x13 0x8
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+
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+ /* IDSEL 0x12 AD18 miniPCI slot 2 */
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+ 0x9000 0x0 0x0 0x1 &ipic 0x13 0x8
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+ 0x9000 0x0 0x0 0x2 &ipic 0x11 0x8>;
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+
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+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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+ interrupt-parent = <&ipic>;
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+ // interrupts = <66 0x8>;
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+ };
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+
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+
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+ qe@e0100000 {
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+ reg = <0xe0100000 0x480>;
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+ ranges = <0x0 0xe0100000 0x100000>;
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+ model = "QE";
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+ device_type = "qe";
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+ compatible = "fsl,qe";
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+ #size-cells = <1>;
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+ #address-cells = <1>;
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+ brg-frequency = <0>;
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+ bus-frequency = <0>;
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+ // bus-frequency = <198000000>;
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+ fsl,qe-num-riscs = <1>;
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+ fsl,qe-num-snums = <28>;
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+
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+ qeic: qeic@80 {
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+ interrupt-controller;
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+ compatible = "fsl,qe-ic";
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+ big-endian;
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+ built-in;
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+ reg = <0x80 0x80>;
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+ #interrupt-cells = <1>;
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+ #address-cells = <0>;
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+ device_type = "qeic";
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+ interrupts = <0x20 0x8 0x21 0x8>;
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+ interrupt-parent = <&ipic>;
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+ };
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+
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+ mdio@2120 {
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+ compatible = "ucc_geth_phy";
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+ device_type = "mdio";
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+ reg = <0x3120 0x18>;
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+ #size-cells = <0>;
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+ #address-cells = <1>;
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+
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+ phy3: ethernet-phy@03 {
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+ // interface = <0x3>;
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+ device_type = "ethernet-phy";
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+ reg = <0x3>;
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+ };
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+
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+ phy2: ethernet-phy@02 {
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+ // interface = <0x3>;
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+ device_type = "ethernet-phy";
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+ reg = <0x2>;
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+ };
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+
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+ phy1: ethernet-phy@01 {
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+ // interface = <0x3>;
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+ device_type = "ethernet-phy";
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+ reg = <0x1>;
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+ };
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+ };
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+
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+ enet0: ucc@2200 {
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+ tx-clock = <0x1a>;
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+ rx-clock = <0x1f>;
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+ mac-address = [00 0c 42 1c 29 d2];
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+ interrupt-parent = <&qeic>;
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+ interrupts = <0x22>;
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+ reg = <0x2200 0x200>;
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+ device-id = <0x3>;
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+ model = "UCC";
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+ compatible = "ucc_geth";
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+ device_type = "network";
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+ phy-handle = <&phy2>;
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+ pio-handle = <&pio3>;
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+ };
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+
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+ enet1: ucc@3200 {
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+ tx-clock = <0x22>;
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+ rx-clock = <0x20>;
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+ mac-address = [00 0c 42 1c 29 d1];
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+ interrupt-parent = <&qeic>;
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+ interrupts = <0x23>;
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+ reg = <0x3200 0x200>;
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+ device-id = <0x4>;
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+ model = "UCC";
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+ compatible = "ucc_geth";
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+ device_type = "network";
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+ phy-handle = <&phy3>;
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+ pio-handle = <&pio4>;
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+ };
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+
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+ enet2: ucc@3000 {
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+ tx-clock = <0x18>;
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+ rx-clock = <0x17>;
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+ mac-address = [00 0c 42 1c 29 d0];
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+ interrupt-parent = <&qeic>;
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+ interrupts = <0x21>;
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+ reg = <0x3000 0x200>;
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+ device-id = <0x2>;
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+ model = "UCC";
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+ compatible = "ucc_geth";
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+ device_type = "network";
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+ phy-handle = <&phy1>;
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+ pio-handle = <&pio2>;
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+ };
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+
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+ spi@500 {
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+ mode = "cpu";
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+ interrupt-parent = <&qeic>;
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+ interrupts = <0x1>;
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+ reg = <0x500 0x40>;
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+ compatible = "fsl,spi";
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+ device_type = "spi";
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+ };
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+
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+ spi@4c0 {
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+ mode = "cpu";
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+ interrupt-parent = <&qeic>;
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+ interrupts = <0x2>;
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+ reg = <0x4c0 0x40>;
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+ compatible = "fsl,spi";
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+ device_type = "spi";
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+ };
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+
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+ muram@10000 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "fsl,qe-muram", "fsl,cpm-muram";
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+ ranges = <0x0 0x10000 0x4000>;
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+ device_type = "muram";
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+
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+ data-only@0 {
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+ compatible = "fsl,qe-muram-data",
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+ "fsl,cpm-muram-data";
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+ reg = <0x0 0x4000>;
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+ };
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+ };
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+ };
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+
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+
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+ soc8323@e0000000 {
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+ bus-frequency = <0x1>;
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+ reg = <0xe0000000 0x200>;
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+ ranges = <0x0 0xe0000000 0x100000>;
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+ device_type = "soc";
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+ compatible = "simple-bus";
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+ #interrupt-cells = <0x2>;
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+ #size-cells = <1>;
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+ #address-cells = <1>;
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+
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+ beeper {
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+ gpio = <&gpio3 0x12>;
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+ reg = <0x500 0x100>;
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+ interrupt-parent = <&ipic>;
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+ interrupts = <0x48 0x8>;
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+ };
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+
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+ gpio3: gpio@3 {
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+ reg = <0x144c 0x4>;
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+ device-id = <0x3>;
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+ compatible = "qe_gpio";
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+ device_type = "gpio";
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+ };
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+
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+ gpio2: gpio@2 {
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+ reg = <0x1434 0x4>;
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+ device-id = <0x2>;
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+ compatible = "qe_gpio";
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+ device_type = "gpio";
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+ };
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+
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+ gpio0: gpio@0 {
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+ reg = <0x1404 0x4>;
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+ device-id = <0x0>;
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+ compatible = "qe_gpio";
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+ device_type = "gpio";
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+ };
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+
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+ par_io@1400 {
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+ num-ports = <4>;
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+ device_type = "par_io";
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+ reg = <0x1400 0x100>;
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+
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+ pio4: ucc_pin@04 {
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+ pio-map = <
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+ /* port pin dir open_drain assignment has_irq */
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+ 1 18 1 0 1 0
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+ 1 19 1 0 1 0
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+ 1 20 1 0 1 0
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+ 1 21 1 0 1 0
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+ 1 30 1 0 1 0
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+ 3 20 2 0 1 0
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+ 1 30 2 0 1 0
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+ 1 31 2 0 1 0
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+ 1 22 2 0 1 0
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+ 1 23 2 0 1 0
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+ 1 24 2 0 1 0
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+ 1 25 2 0 1 0
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+ 1 28 2 0 1 0
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+ 1 26 2 0 1 0
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+ 3 21 2 0 1 0>;
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+ };
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+
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+ pio3: ucc_pin@03 {
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+ pio-map = <
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+ /* port pin dir open_drain assignment has_irq */
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+ 1 0 1 0 1 0
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+ 1 1 1 0 1 0
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+ 1 2 1 0 1 0
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+ 1 3 1 0 1 0
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+ 1 12 1 0 1 0
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+ 3 24 2 0 1 0
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+ 1 11 2 0 1 0
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+ 1 13 2 0 1 0
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+ 1 4 2 0 1 0
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+ 1 5 2 0 1 0
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+ 1 6 2 0 1 0
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+ 1 7 2 0 1 0
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+ 1 10 2 0 1 0
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+ 1 8 2 0 1 0
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+ 3 29 2 0 1 0>;
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+ };
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+
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+ pio2: ucc_pin@02 {
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+ pio-map = <
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+ /* port pin dir open_drain assignment has_irq */
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+ 3 4 3 0 2 0
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+ 3 5 1 0 2 0
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+ 0 18 1 0 1 0
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+ 0 19 1 0 1 0
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+ 0 20 1 0 1 0
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+ 0 21 1 0 1 0
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+ 0 30 1 0 1 0
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+ 3 6 2 0 1 0
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+ 0 29 2 0 1 0
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+ 0 31 2 0 1 0
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+ 0 22 2 0 1 0
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+ 0 23 2 0 1 0
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+ 0 24 2 0 1 0
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+ 0 25 2 0 1 0
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+ 0 28 2 0 1 0
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+ 0 26 2 0 1 0
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+ 3 31 2 0 1 0>;
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+ };
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+ };
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+
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+ ipic: pic@700 {
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+ device_type = "ipic";
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+ built-in;
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+ reg = <0x700 0x100>;
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+ #interrupt-cells = <0x2>;
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+ #address-cells = <0x0>;
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+ interrupt-controller;
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+ };
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+
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+
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+ serial@4500 {
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+ interrupt-parent = <&ipic>;
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+ interrupts = <0x9 0x8>;
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+ clock-frequency = <0x7f27c20>;
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+ reg = <0x4500 0x100>;
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+ compatible = "ns16550";
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+ device_type = "serial";
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+ };
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+
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+ dma@82a8 {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
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+ reg = <0x82a8 4>;
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+ ranges = <0 0x8100 0x1a8>;
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+ interrupt-parent = <&ipic>;
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+ interrupts = <71 8>;
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+ cell-index = <0>;
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+ dma-channel@0 {
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+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
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+ reg = <0 0x80>;
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+ cell-index = <0>;
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+ interrupt-parent = <&ipic>;
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+ interrupts = <71 8>;
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+ };
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+ dma-channel@80 {
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+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
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+ reg = <0x80 0x80>;
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+ cell-index = <1>;
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+ interrupt-parent = <&ipic>;
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+ interrupts = <71 8>;
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+ };
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+ dma-channel@100 {
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+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
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+ reg = <0x100 0x80>;
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+ cell-index = <2>;
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+ interrupt-parent = <&ipic>;
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+ interrupts = <71 8>;
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+ };
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+ dma-channel@180 {
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+ compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
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+ reg = <0x180 0x28>;
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+ cell-index = <3>;
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+ interrupt-parent = <&ipic>;
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+ interrupts = <71 8>;
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+ };
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+ };
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+
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+ wdt@200 {
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+ reg = <0x200 0x100>;
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+ compatible = "mpc83xx_wdt";
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+ device_type = "watchdog";
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+ };
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+ };
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+};
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