mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-25 23:05:31 +02:00
bf183aeff8
* this adds sflash support for ssb devices * the flash is now a platform device * minor updates git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27902 3c298f89-4303-0410-b956-a3cf2f4a3e73
411 lines
10 KiB
Diff
411 lines
10 KiB
Diff
From d3fb63a710e1f04fed2c2703c6dce3531490c451 Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Mon, 6 Jun 2011 00:07:37 +0200
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Subject: [PATCH 10/26] bcm47xx: add support for bcma bus
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This patch add support for the bcma bus. Broadcom uses only Mips 74K
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CPUs on the new SoC and on the old ons using ssb bus there are no Mips
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74K CPUs.
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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---
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arch/mips/bcm47xx/Kconfig | 13 ++++++
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arch/mips/bcm47xx/gpio.c | 22 +++++++++++
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arch/mips/bcm47xx/nvram.c | 10 +++++
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arch/mips/bcm47xx/serial.c | 29 ++++++++++++++
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arch/mips/bcm47xx/setup.c | 53 +++++++++++++++++++++++++-
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arch/mips/bcm47xx/time.c | 5 ++
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arch/mips/include/asm/mach-bcm47xx/bcm47xx.h | 8 ++++
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arch/mips/include/asm/mach-bcm47xx/gpio.h | 41 ++++++++++++++++++++
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drivers/watchdog/bcm47xx_wdt.c | 11 +++++
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9 files changed, 190 insertions(+), 2 deletions(-)
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--- a/arch/mips/bcm47xx/Kconfig
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+++ b/arch/mips/bcm47xx/Kconfig
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@@ -15,4 +15,17 @@ config BCM47XX_SSB
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This will generate an image with support for SSB and MIPS32 R1 instruction set.
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+config BCM47XX_BCMA
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+ bool "BCMA Support for Broadcom BCM47XX"
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+ select SYS_HAS_CPU_MIPS32_R2
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+ select BCMA
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+ select BCMA_HOST_SOC
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+ select BCMA_DRIVER_MIPS
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+ select BCMA_DRIVER_PCI_HOSTMODE if PCI
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+ default y
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+ help
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+ Add support for new Broadcom BCM47xx boards with Broadcom specific Advanced Microcontroller Bus.
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+
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+ This will generate an image with support for BCMA and MIPS32 R2 instruction set.
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+
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endif
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--- a/arch/mips/bcm47xx/gpio.c
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+++ b/arch/mips/bcm47xx/gpio.c
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@@ -36,6 +36,16 @@ int gpio_request(unsigned gpio, const ch
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return 0;
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ if (gpio >= BCM47XX_CHIPCO_GPIO_LINES)
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+ return -EINVAL;
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+
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+ if (test_and_set_bit(gpio, gpio_in_use))
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+ return -EBUSY;
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+
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+ return 0;
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+#endif
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}
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return -EINVAL;
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}
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@@ -57,6 +67,14 @@ void gpio_free(unsigned gpio)
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clear_bit(gpio, gpio_in_use);
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return;
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ if (gpio >= BCM47XX_CHIPCO_GPIO_LINES)
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+ return;
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+
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+ clear_bit(gpio, gpio_in_use);
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+ return;
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+#endif
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}
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}
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EXPORT_SYMBOL(gpio_free);
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@@ -73,6 +91,10 @@ int gpio_to_irq(unsigned gpio)
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else
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return -EINVAL;
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ return bcma_core_mips_irq(bcm47xx_bus.bcma.bus.drv_cc.core) + 2;
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+#endif
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}
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return -EINVAL;
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}
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--- a/arch/mips/bcm47xx/nvram.c
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+++ b/arch/mips/bcm47xx/nvram.c
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@@ -29,6 +29,9 @@ static void early_nvram_init(void)
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#ifdef CONFIG_BCM47XX_SSB
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struct ssb_mipscore *mcore_ssb;
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ struct bcma_drv_cc *bcma_cc;
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+#endif
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struct nvram_header *header;
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int i;
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u32 base = 0;
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@@ -44,6 +47,13 @@ static void early_nvram_init(void)
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lim = mcore_ssb->flash_window_size;
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break;
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ bcma_cc = &bcm47xx_bus.bcma.bus.drv_cc;
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+ base = bcma_cc->pflash.window;
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+ lim = bcma_cc->pflash.window_size;
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+ break;
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+#endif
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}
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off = FLASH_MIN;
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--- a/arch/mips/bcm47xx/serial.c
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+++ b/arch/mips/bcm47xx/serial.c
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@@ -47,6 +47,31 @@ static int __init uart8250_init_ssb(void
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}
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+static int __init uart8250_init_bcma(void)
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+{
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+ int i;
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+ struct bcma_drv_cc *cc = &(bcm47xx_bus.bcma.bus.drv_cc);
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+
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+ memset(&uart8250_data, 0, sizeof(uart8250_data));
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+
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+ for (i = 0; i < cc->nr_serial_ports; i++) {
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+ struct plat_serial8250_port *p = &(uart8250_data[i]);
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+ struct bcma_serial_port *bcma_port;
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+ bcma_port = &(cc->serial_ports[i]);
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+
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+ p->mapbase = (unsigned int) bcma_port->regs;
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+ p->membase = (void *) bcma_port->regs;
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+ p->irq = bcma_port->irq + 2;
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+ p->uartclk = bcma_port->baud_base;
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+ p->regshift = bcma_port->reg_shift;
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+ p->iotype = UPIO_MEM;
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+ p->flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
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+ }
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+ return platform_device_register(&uart8250_device);
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+}
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+#endif
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+
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static int __init uart8250_init(void)
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{
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switch (bcm47xx_bus_type) {
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@@ -54,6 +79,10 @@ static int __init uart8250_init(void)
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case BCM47XX_BUS_TYPE_SSB:
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return uart8250_init_ssb();
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ return uart8250_init_bcma();
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+#endif
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}
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return -EINVAL;
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}
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--- a/arch/mips/bcm47xx/setup.c
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+++ b/arch/mips/bcm47xx/setup.c
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@@ -29,6 +29,7 @@
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#include <linux/types.h>
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#include <linux/ssb/ssb.h>
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#include <linux/ssb/ssb_embedded.h>
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+#include <linux/bcma/bcma_soc.h>
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#include <asm/bootinfo.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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@@ -52,6 +53,11 @@ static void bcm47xx_machine_restart(char
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ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 1);
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break;
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 1);
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+ break;
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+#endif
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}
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while (1)
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cpu_relax();
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@@ -67,6 +73,11 @@ static void bcm47xx_machine_halt(void)
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ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0);
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break;
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 0);
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+ break;
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+#endif
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}
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while (1)
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cpu_relax();
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@@ -295,16 +306,54 @@ static void __init bcm47xx_register_ssb(
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}
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+static void __init bcm47xx_register_bcma(void)
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+{
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+ int err;
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+
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+ err = bcma_host_soc_register(&bcm47xx_bus.bcma);
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+ if (err)
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+ panic("Failed to initialize BCMA bus (err %d)\n", err);
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+}
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+#endif
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+
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void __init plat_mem_setup(void)
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{
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struct cpuinfo_mips *c = ¤t_cpu_data;
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+ if (c->cputype == CPU_74K) {
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+ printk(KERN_INFO "bcm47xx: using bcma bus\n");
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+#ifdef CONFIG_BCM47XX_BCMA
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+ bcm47xx_bus_type = BCM47XX_BUS_TYPE_BCMA;
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+ bcm47xx_register_bcma();
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+#endif
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+ } else {
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+ printk(KERN_INFO "bcm47xx: using ssb bus\n");
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#ifdef CONFIG_BCM47XX_SSB
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- bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB;
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- bcm47xx_register_ssb();
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+ bcm47xx_bus_type = BCM47XX_BUS_TYPE_SSB;
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+ bcm47xx_register_ssb();
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#endif
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+ }
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_machine_restart = bcm47xx_machine_restart;
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_machine_halt = bcm47xx_machine_halt;
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pm_power_off = bcm47xx_machine_halt;
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}
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+
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+static int __init bcm47xx_register_bus_complete(void)
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+{
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+ switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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+ case BCM47XX_BUS_TYPE_SSB:
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+ /* Nothing to do */
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+ break;
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+#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ bcma_bus_register(&bcm47xx_bus.bcma.bus);
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+ break;
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+#endif
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+ }
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+ return 0;
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+}
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+device_initcall(bcm47xx_register_bus_complete);
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--- a/arch/mips/bcm47xx/time.c
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+++ b/arch/mips/bcm47xx/time.c
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@@ -45,6 +45,11 @@ void __init plat_time_init(void)
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hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2;
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break;
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2;
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+ break;
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+#endif
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}
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if (!hz)
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--- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
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+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx.h
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@@ -20,17 +20,25 @@
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#define __ASM_BCM47XX_H
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#include <linux/ssb/ssb.h>
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+#include <linux/bcma/bcma.h>
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+#include <linux/bcma/bcma_soc.h>
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enum bcm47xx_bus_type {
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#ifdef CONFIG_BCM47XX_SSB
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BCM47XX_BUS_TYPE_SSB,
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ BCM47XX_BUS_TYPE_BCMA,
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+#endif
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};
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union bcm47xx_bus {
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#ifdef CONFIG_BCM47XX_SSB
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struct ssb_bus ssb;
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ struct bcma_soc bcma;
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+#endif
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};
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extern union bcm47xx_bus bcm47xx_bus;
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--- a/arch/mips/include/asm/mach-bcm47xx/gpio.h
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+++ b/arch/mips/include/asm/mach-bcm47xx/gpio.h
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@@ -10,6 +10,7 @@
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#define __BCM47XX_GPIO_H
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#include <linux/ssb/ssb_embedded.h>
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+#include <linux/bcma/bcma.h>
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#include <asm/mach-bcm47xx/bcm47xx.h>
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#define BCM47XX_EXTIF_GPIO_LINES 5
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@@ -26,6 +27,11 @@ static inline int gpio_get_value(unsigne
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case BCM47XX_BUS_TYPE_SSB:
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return ssb_gpio_in(&bcm47xx_bus.ssb, 1 << gpio);
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ return bcma_chipco_gpio_in(&bcm47xx_bus.bcma.bus.drv_cc,
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+ 1 << gpio);
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+#endif
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}
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return -EINVAL;
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}
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@@ -37,6 +43,13 @@ static inline void gpio_set_value(unsign
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case BCM47XX_BUS_TYPE_SSB:
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ssb_gpio_out(&bcm47xx_bus.ssb, 1 << gpio,
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value ? 1 << gpio : 0);
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+ return;
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+#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio,
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+ value ? 1 << gpio : 0);
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+ return;
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#endif
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}
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}
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@@ -49,6 +62,12 @@ static inline int gpio_direction_input(u
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ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 0);
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return 0;
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio,
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+ 0);
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+ return 0;
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+#endif
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}
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return -EINVAL;
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}
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@@ -65,6 +84,16 @@ static inline int gpio_direction_output(
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ssb_gpio_outen(&bcm47xx_bus.ssb, 1 << gpio, 1 << gpio);
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return 0;
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ /* first set the gpio out value */
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+ bcma_chipco_gpio_out(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio,
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+ value ? 1 << gpio : 0);
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+ /* then set the gpio mode */
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+ bcma_chipco_gpio_outen(&bcm47xx_bus.bcma.bus.drv_cc, 1 << gpio,
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+ 1 << gpio);
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+ return 0;
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+#endif
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}
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return -EINVAL;
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}
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@@ -78,6 +107,12 @@ static inline int gpio_intmask(unsigned
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value ? 1 << gpio : 0);
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return 0;
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ bcma_chipco_gpio_intmask(&bcm47xx_bus.bcma.bus.drv_cc,
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+ 1 << gpio, value ? 1 << gpio : 0);
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+ return 0;
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+#endif
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}
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return -EINVAL;
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}
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@@ -91,6 +126,12 @@ static inline int gpio_polarity(unsigned
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value ? 1 << gpio : 0);
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return 0;
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ bcma_chipco_gpio_polarity(&bcm47xx_bus.bcma.bus.drv_cc,
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+ 1 << gpio, value ? 1 << gpio : 0);
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+ return 0;
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+#endif
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}
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return -EINVAL;
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}
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--- a/drivers/watchdog/bcm47xx_wdt.c
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+++ b/drivers/watchdog/bcm47xx_wdt.c
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@@ -60,6 +60,12 @@ static inline void bcm47xx_wdt_hw_start(
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ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0xfffffff);
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break;
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc,
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+ 0xfffffff);
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+ break;
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+#endif
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}
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}
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@@ -70,6 +76,11 @@ static inline int bcm47xx_wdt_hw_stop(vo
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case BCM47XX_BUS_TYPE_SSB:
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return ssb_watchdog_timer_set(&bcm47xx_bus.ssb, 0);
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#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ bcma_chipco_watchdog_timer_set(&bcm47xx_bus.bcma.bus.drv_cc, 0);
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+ return 0;
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+#endif
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}
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return -EINVAL;
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}
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