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git://projects.qi-hardware.com/openwrt-xburst.git
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b06573b702
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@12863 3c298f89-4303-0410-b956-a3cf2f4a3e73
956 lines
25 KiB
C
956 lines
25 KiB
C
/*
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* ADM5120 HCD (Host Controller Driver) for USB
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*
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* Copyright (C) 2007-2008 Gabor Juhos <juhosg@openwrt.org>
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*
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* This file was derived from: drivers/usb/host/ohci-q.c
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* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
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* (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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*/
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#include <linux/irq.h>
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/*-------------------------------------------------------------------------*/
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/*
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* URB goes back to driver, and isn't reissued.
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* It's completely gone from HC data structures.
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* PRECONDITION: ahcd lock held, irqs blocked.
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*/
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static void
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finish_urb(struct admhcd *ahcd, struct urb *urb, int status)
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__releases(ahcd->lock)
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__acquires(ahcd->lock)
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{
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urb_priv_free(ahcd, urb->hcpriv);
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if (likely(status == -EINPROGRESS))
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status = 0;
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switch (usb_pipetype(urb->pipe)) {
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case PIPE_ISOCHRONOUS:
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admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs--;
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break;
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case PIPE_INTERRUPT:
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admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs--;
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break;
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}
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#ifdef ADMHC_VERBOSE_DEBUG
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urb_print(ahcd, urb, "RET", usb_pipeout (urb->pipe), status);
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#endif
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/* urb->complete() can reenter this HCD */
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usb_hcd_unlink_urb_from_ep(admhcd_to_hcd(ahcd), urb);
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spin_unlock(&ahcd->lock);
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usb_hcd_giveback_urb(admhcd_to_hcd(ahcd), urb, status);
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spin_lock(&ahcd->lock);
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}
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/*-------------------------------------------------------------------------*
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* ED handling functions
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*-------------------------------------------------------------------------*/
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#if 0 /* FIXME */
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/* search for the right schedule branch to use for a periodic ed.
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* does some load balancing; returns the branch, or negative errno.
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*/
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static int balance(struct admhcd *ahcd, int interval, int load)
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{
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int i, branch = -ENOSPC;
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/* iso periods can be huge; iso tds specify frame numbers */
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if (interval > NUM_INTS)
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interval = NUM_INTS;
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/* search for the least loaded schedule branch of that period
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* that has enough bandwidth left unreserved.
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*/
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for (i = 0; i < interval ; i++) {
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if (branch < 0 || ahcd->load [branch] > ahcd->load [i]) {
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int j;
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/* usb 1.1 says 90% of one frame */
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for (j = i; j < NUM_INTS; j += interval) {
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if ((ahcd->load [j] + load) > 900)
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break;
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}
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if (j < NUM_INTS)
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continue;
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branch = i;
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}
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}
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return branch;
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}
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#endif
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/*-------------------------------------------------------------------------*/
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#if 0 /* FIXME */
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/* both iso and interrupt requests have periods; this routine puts them
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* into the schedule tree in the apppropriate place. most iso devices use
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* 1msec periods, but that's not required.
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*/
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static void periodic_link (struct admhcd *ahcd, struct ed *ed)
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{
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unsigned i;
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admhc_vdbg (ahcd, "link %sed %p branch %d [%dus.], interval %d\n",
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(ed->hwINFO & cpu_to_hc32(ahcd, ED_ISO)) ? "iso " : "",
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ed, ed->branch, ed->load, ed->interval);
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for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
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struct ed **prev = &ahcd->periodic [i];
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__hc32 *prev_p = &ahcd->hcca->int_table [i];
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struct ed *here = *prev;
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/* sorting each branch by period (slow before fast)
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* lets us share the faster parts of the tree.
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* (plus maybe: put interrupt eds before iso)
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*/
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while (here && ed != here) {
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if (ed->interval > here->interval)
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break;
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prev = &here->ed_next;
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prev_p = &here->hwNextED;
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here = *prev;
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}
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if (ed != here) {
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ed->ed_next = here;
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if (here)
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ed->hwNextED = *prev_p;
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wmb ();
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*prev = ed;
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*prev_p = cpu_to_hc32(ahcd, ed->dma);
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wmb();
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}
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ahcd->load [i] += ed->load;
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}
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admhcd_to_hcd(ahcd)->self.bandwidth_allocated += ed->load / ed->interval;
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}
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#endif
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/* link an ed into the HC chain */
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static int ed_schedule(struct admhcd *ahcd, struct ed *ed)
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{
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struct ed *old_tail;
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if (admhcd_to_hcd(ahcd)->state == HC_STATE_QUIESCING)
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return -EAGAIN;
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ed->state = ED_OPER;
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old_tail = ahcd->ed_tails[ed->type];
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ed->ed_next = old_tail->ed_next;
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if (ed->ed_next) {
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ed->ed_next->ed_prev = ed;
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ed->hwNextED = cpu_to_hc32(ahcd, ed->ed_next->dma);
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}
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ed->ed_prev = old_tail;
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old_tail->ed_next = ed;
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old_tail->hwNextED = cpu_to_hc32(ahcd, ed->dma);
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ahcd->ed_tails[ed->type] = ed;
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admhc_dma_enable(ahcd);
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return 0;
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}
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/*-------------------------------------------------------------------------*/
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#if 0 /* FIXME */
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/* scan the periodic table to find and unlink this ED */
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static void periodic_unlink (struct admhcd *ahcd, struct ed *ed)
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{
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int i;
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for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
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struct ed *temp;
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struct ed **prev = &ahcd->periodic [i];
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__hc32 *prev_p = &ahcd->hcca->int_table [i];
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while (*prev && (temp = *prev) != ed) {
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prev_p = &temp->hwNextED;
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prev = &temp->ed_next;
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}
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if (*prev) {
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*prev_p = ed->hwNextED;
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*prev = ed->ed_next;
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}
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ahcd->load [i] -= ed->load;
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}
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admhcd_to_hcd(ahcd)->self.bandwidth_allocated -= ed->load / ed->interval;
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admhc_vdbg (ahcd, "unlink %sed %p branch %d [%dus.], interval %d\n",
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(ed->hwINFO & cpu_to_hc32(ahcd, ED_ISO)) ? "iso " : "",
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ed, ed->branch, ed->load, ed->interval);
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}
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#endif
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/* unlink an ed from the HC chain.
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* just the link to the ed is unlinked.
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* the link from the ed still points to another operational ed or 0
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* so the HC can eventually finish the processing of the unlinked ed
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* (assuming it already started that, which needn't be true).
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*
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* ED_UNLINK is a transient state: the HC may still see this ED, but soon
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* it won't. ED_SKIP means the HC will finish its current transaction,
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* but won't start anything new. The TD queue may still grow; device
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* drivers don't know about this HCD-internal state.
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*
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* When the HC can't see the ED, something changes ED_UNLINK to one of:
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*
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* - ED_OPER: when there's any request queued, the ED gets rescheduled
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* immediately. HC should be working on them.
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*
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* - ED_IDLE: when there's no TD queue. there's no reason for the HC
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* to care about this ED; safe to disable the endpoint.
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*
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* When finish_unlinks() runs later, after SOF interrupt, it will often
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* complete one or more URB unlinks before making that state change.
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*/
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static void ed_deschedule(struct admhcd *ahcd, struct ed *ed)
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{
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#ifdef ADMHC_VERBOSE_DEBUG
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admhc_dump_ed(ahcd, "ED-DESCHED", ed, 1);
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#endif
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ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
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wmb();
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ed->state = ED_UNLINK;
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/* remove this ED from the HC list */
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ed->ed_prev->hwNextED = ed->hwNextED;
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/* and remove it from our list also */
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ed->ed_prev->ed_next = ed->ed_next;
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if (ed->ed_next)
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ed->ed_next->ed_prev = ed->ed_prev;
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if (ahcd->ed_tails[ed->type] == ed)
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ahcd->ed_tails[ed->type] = ed->ed_prev;
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}
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/*-------------------------------------------------------------------------*/
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static struct ed *ed_create(struct admhcd *ahcd, unsigned int type, u32 info)
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{
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struct ed *ed;
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struct td *td;
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ed = ed_alloc(ahcd, GFP_ATOMIC);
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if (!ed)
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goto err;
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/* dummy td; end of td list for this ed */
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td = td_alloc(ahcd, GFP_ATOMIC);
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if (!td)
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goto err_free_ed;
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switch (type) {
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case PIPE_INTERRUPT:
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info |= ED_INT;
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break;
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case PIPE_ISOCHRONOUS:
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info |= ED_ISO;
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break;
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}
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ed->dummy = td;
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ed->state = ED_IDLE;
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ed->type = type;
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ed->hwINFO = cpu_to_hc32(ahcd, info);
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ed->hwTailP = cpu_to_hc32(ahcd, td->td_dma);
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ed->hwHeadP = ed->hwTailP; /* ED_C, ED_H zeroed */
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return ed;
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err_free_ed:
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ed_free(ahcd, ed);
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err:
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return NULL;
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}
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/* get and maybe (re)init an endpoint. init _should_ be done only as part
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* of enumeration, usb_set_configuration() or usb_set_interface().
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*/
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static struct ed *ed_get(struct admhcd *ahcd, struct usb_host_endpoint *ep,
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struct usb_device *udev, unsigned int pipe, int interval)
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{
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struct ed *ed;
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unsigned long flags;
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spin_lock_irqsave(&ahcd->lock, flags);
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ed = ep->hcpriv;
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if (!ed) {
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u32 info;
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/* FIXME: usbcore changes dev->devnum before SET_ADDRESS
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* suceeds ... otherwise we wouldn't need "pipe".
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*/
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info = usb_pipedevice(pipe);
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info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << ED_EN_SHIFT;
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info |= le16_to_cpu(ep->desc.wMaxPacketSize) << ED_MPS_SHIFT;
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if (udev->speed == USB_SPEED_FULL)
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info |= ED_SPEED_FULL;
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ed = ed_create(ahcd, usb_pipetype(pipe), info);
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if (ed)
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ep->hcpriv = ed;
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}
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spin_unlock_irqrestore(&ahcd->lock, flags);
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return ed;
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}
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/*-------------------------------------------------------------------------*/
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/* request unlinking of an endpoint from an operational HC.
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* put the ep on the rm_list
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* real work is done at the next start frame (SOFI) hardware interrupt
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* caller guarantees HCD is running, so hardware access is safe,
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* and that ed->state is ED_OPER
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*/
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static void start_ed_unlink(struct admhcd *ahcd, struct ed *ed)
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{
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#ifdef ADMHC_VERBOSE_DEBUG
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admhc_dump_ed(ahcd, "ED-UNLINK", ed, 1);
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#endif
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ed->hwINFO |= cpu_to_hc32(ahcd, ED_DEQUEUE);
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ed_deschedule(ahcd, ed);
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/* add this ED into the remove list */
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ed->ed_rm_next = ahcd->ed_rm_list;
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ahcd->ed_rm_list = ed;
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/* enable SOF interrupt */
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admhc_intr_ack(ahcd, ADMHC_INTR_SOFI);
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admhc_intr_enable(ahcd, ADMHC_INTR_SOFI);
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/* flush those writes */
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admhc_writel_flush(ahcd);
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/* SOF interrupt might get delayed; record the frame counter value that
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* indicates when the HC isn't looking at it, so concurrent unlinks
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* behave. frame_no wraps every 2^16 msec, and changes right before
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* SOF is triggered.
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*/
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ed->tick = admhc_frame_no(ahcd) + 1;
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}
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/*-------------------------------------------------------------------------*
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* TD handling functions
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*-------------------------------------------------------------------------*/
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/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
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static void
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td_fill(struct admhcd *ahcd, u32 info, dma_addr_t data, int len,
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struct urb *urb, int index)
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{
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struct td *td, *td_pt;
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struct urb_priv *urb_priv = urb->hcpriv;
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int hash;
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u32 cbl = 0;
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#if 1
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if (index == (urb_priv->td_cnt - 1) &&
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((urb->transfer_flags & URB_NO_INTERRUPT) == 0))
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cbl |= TD_IE;
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#else
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if (index == (urb_priv->td_cnt - 1))
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cbl |= TD_IE;
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#endif
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/* use this td as the next dummy */
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td_pt = urb_priv->td[index];
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/* fill the old dummy TD */
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td = urb_priv->td[index] = urb_priv->ed->dummy;
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urb_priv->ed->dummy = td_pt;
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td->ed = urb_priv->ed;
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td->next_dl_td = NULL;
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td->index = index;
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td->urb = urb;
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td->data_dma = data;
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if (!len)
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data = 0;
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if (data)
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cbl |= (len & TD_BL_MASK);
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info |= TD_OWN;
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/* setup hardware specific fields */
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td->hwINFO = cpu_to_hc32(ahcd, info);
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td->hwDBP = cpu_to_hc32(ahcd, data);
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td->hwCBL = cpu_to_hc32(ahcd, cbl);
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td->hwNextTD = cpu_to_hc32(ahcd, td_pt->td_dma);
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/* append to queue */
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list_add_tail(&td->td_list, &td->ed->td_list);
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/* hash it for later reverse mapping */
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hash = TD_HASH_FUNC(td->td_dma);
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td->td_hash = ahcd->td_hash[hash];
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ahcd->td_hash[hash] = td;
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/* HC might read the TD (or cachelines) right away ... */
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wmb();
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td->ed->hwTailP = td->hwNextTD;
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}
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/*-------------------------------------------------------------------------*/
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/* Prepare all TDs of a transfer, and queue them onto the ED.
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* Caller guarantees HC is active.
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* Usually the ED is already on the schedule, so TDs might be
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* processed as soon as they're queued.
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*/
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static void td_submit_urb(struct admhcd *ahcd, struct urb *urb)
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{
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struct urb_priv *urb_priv = urb->hcpriv;
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dma_addr_t data;
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int data_len = urb->transfer_buffer_length;
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int cnt = 0;
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u32 info = 0;
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int is_out = usb_pipeout(urb->pipe);
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u32 toggle = 0;
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/* OHCI handles the bulk/interrupt data toggles itself. We just
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* use the device toggle bits for resetting, and rely on the fact
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* that resetting toggle is meaningless if the endpoint is active.
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*/
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if (usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe), is_out)) {
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toggle = TD_T_CARRY;
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} else {
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toggle = TD_T_DATA0;
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usb_settoggle(urb->dev, usb_pipeendpoint (urb->pipe),
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is_out, 1);
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}
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urb_priv->td_idx = 0;
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list_add(&urb_priv->pending, &ahcd->pending);
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if (data_len)
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data = urb->transfer_dma;
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else
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data = 0;
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/* NOTE: TD_CC is set so we can tell which TDs the HC processed by
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* using TD_CC_GET, as well as by seeing them on the done list.
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* (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
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*/
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switch (urb_priv->ed->type) {
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case PIPE_INTERRUPT:
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info = is_out
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? TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_OUT
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: TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_IN;
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/* setup service interval and starting frame number */
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info |= (urb->start_frame & TD_FN_MASK);
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info |= (urb->interval & TD_ISI_MASK) << TD_ISI_SHIFT;
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td_fill(ahcd, info, data, data_len, urb, cnt);
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cnt++;
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admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs++;
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break;
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case PIPE_BULK:
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info = is_out
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? TD_SCC_NOTACCESSED | TD_DP_OUT
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: TD_SCC_NOTACCESSED | TD_DP_IN;
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/* TDs _could_ transfer up to 8K each */
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while (data_len > TD_DATALEN_MAX) {
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td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle),
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data, TD_DATALEN_MAX, urb, cnt);
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data += TD_DATALEN_MAX;
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data_len -= TD_DATALEN_MAX;
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cnt++;
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}
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td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle), data,
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data_len, urb, cnt);
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cnt++;
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if ((urb->transfer_flags & URB_ZERO_PACKET)
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&& (cnt < urb_priv->td_cnt)) {
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td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle),
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0, 0, urb, cnt);
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cnt++;
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}
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break;
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|
|
/* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
|
|
* any DATA phase works normally, and the STATUS ack is special.
|
|
*/
|
|
case PIPE_CONTROL:
|
|
/* fill a TD for the setup */
|
|
info = TD_SCC_NOTACCESSED | TD_DP_SETUP | TD_T_DATA0;
|
|
td_fill(ahcd, info, urb->setup_dma, 8, urb, cnt++);
|
|
|
|
if (data_len > 0) {
|
|
/* fill a TD for the data */
|
|
info = TD_SCC_NOTACCESSED | TD_T_DATA1;
|
|
info |= is_out ? TD_DP_OUT : TD_DP_IN;
|
|
/* NOTE: mishandles transfers >8K, some >4K */
|
|
td_fill(ahcd, info, data, data_len, urb, cnt++);
|
|
}
|
|
|
|
/* fill a TD for the ACK */
|
|
info = (is_out || data_len == 0)
|
|
? TD_SCC_NOTACCESSED | TD_DP_IN | TD_T_DATA1
|
|
: TD_SCC_NOTACCESSED | TD_DP_OUT | TD_T_DATA1;
|
|
td_fill(ahcd, info, data, 0, urb, cnt++);
|
|
|
|
break;
|
|
|
|
/* ISO has no retransmit, so no toggle;
|
|
* Each TD could handle multiple consecutive frames (interval 1);
|
|
* we could often reduce the number of TDs here.
|
|
*/
|
|
case PIPE_ISOCHRONOUS:
|
|
info = is_out
|
|
? TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_OUT
|
|
: TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_IN;
|
|
|
|
for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
|
|
int frame = urb->start_frame;
|
|
|
|
frame += cnt * urb->interval;
|
|
frame &= TD_FN_MASK;
|
|
td_fill(ahcd, info | frame,
|
|
data + urb->iso_frame_desc[cnt].offset,
|
|
urb->iso_frame_desc[cnt].length, urb, cnt);
|
|
}
|
|
admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs++;
|
|
break;
|
|
}
|
|
|
|
if (urb_priv->td_cnt != cnt)
|
|
admhc_err(ahcd, "bad number of tds created for urb %p\n", urb);
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*
|
|
* Done List handling functions
|
|
*-------------------------------------------------------------------------*/
|
|
|
|
/* calculate transfer length/status and update the urb */
|
|
static int td_done(struct admhcd *ahcd, struct urb *urb, struct td *td)
|
|
{
|
|
struct urb_priv *urb_priv = urb->hcpriv;
|
|
u32 info;
|
|
u32 bl;
|
|
u32 tdDBP;
|
|
int type = usb_pipetype(urb->pipe);
|
|
int cc;
|
|
int status = -EINPROGRESS;
|
|
|
|
info = hc32_to_cpup(ahcd, &td->hwINFO);
|
|
tdDBP = hc32_to_cpup(ahcd, &td->hwDBP);
|
|
bl = TD_BL_GET(hc32_to_cpup(ahcd, &td->hwCBL));
|
|
cc = TD_CC_GET(info);
|
|
|
|
/* ISO ... drivers see per-TD length/status */
|
|
if (type == PIPE_ISOCHRONOUS) {
|
|
/* TODO */
|
|
int dlen = 0;
|
|
|
|
/* NOTE: assumes FC in tdINFO == 0, and that
|
|
* only the first of 0..MAXPSW psws is used.
|
|
*/
|
|
if (info & TD_CC) /* hc didn't touch? */
|
|
return status;
|
|
|
|
if (usb_pipeout(urb->pipe))
|
|
dlen = urb->iso_frame_desc[td->index].length;
|
|
else {
|
|
/* short reads are always OK for ISO */
|
|
if (cc == TD_CC_DATAUNDERRUN)
|
|
cc = TD_CC_NOERROR;
|
|
dlen = tdDBP - td->data_dma + bl;
|
|
}
|
|
|
|
urb->actual_length += dlen;
|
|
urb->iso_frame_desc[td->index].actual_length = dlen;
|
|
urb->iso_frame_desc[td->index].status = cc_to_error[cc];
|
|
|
|
if (cc != TD_CC_NOERROR)
|
|
admhc_vdbg (ahcd,
|
|
"urb %p iso td %p (%d) len %d cc %d\n",
|
|
urb, td, 1 + td->index, dlen, cc);
|
|
|
|
/* BULK, INT, CONTROL ... drivers see aggregate length/status,
|
|
* except that "setup" bytes aren't counted and "short" transfers
|
|
* might not be reported as errors.
|
|
*/
|
|
} else {
|
|
/* update packet status if needed (short is normally ok) */
|
|
if (cc == TD_CC_DATAUNDERRUN
|
|
&& !(urb->transfer_flags & URB_SHORT_NOT_OK))
|
|
cc = TD_CC_NOERROR;
|
|
|
|
if (cc != TD_CC_NOERROR && cc < TD_CC_HCD0)
|
|
status = cc_to_error[cc];
|
|
|
|
|
|
/* count all non-empty packets except control SETUP packet */
|
|
if ((type != PIPE_CONTROL || td->index != 0) && tdDBP != 0) {
|
|
urb->actual_length += tdDBP - td->data_dma + bl;
|
|
}
|
|
|
|
if (cc != TD_CC_NOERROR && cc < TD_CC_HCD0)
|
|
admhc_vdbg(ahcd,
|
|
"urb %p td %p (%d) cc %d, len=%d/%d\n",
|
|
urb, td, td->index, cc,
|
|
urb->actual_length,
|
|
urb->transfer_buffer_length);
|
|
}
|
|
|
|
list_del(&td->td_list);
|
|
urb_priv->td_idx++;
|
|
|
|
return status;
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
static inline void
|
|
ed_halted(struct admhcd *ahcd, struct td *td, int cc, struct td *rev)
|
|
{
|
|
struct urb *urb = td->urb;
|
|
struct urb_priv *urb_priv = urb->hcpriv;
|
|
struct ed *ed = td->ed;
|
|
struct list_head *tmp = td->td_list.next;
|
|
__hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C);
|
|
|
|
admhc_dump_ed(ahcd, "ed halted", td->ed, 1);
|
|
/* clear ed halt; this is the td that caused it, but keep it inactive
|
|
* until its urb->complete() has a chance to clean up.
|
|
*/
|
|
ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
|
|
wmb();
|
|
ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
|
|
|
|
/* Get rid of all later tds from this urb. We don't have
|
|
* to be careful: no errors and nothing was transferred.
|
|
* Also patch the ed so it looks as if those tds completed normally.
|
|
*/
|
|
while (tmp != &ed->td_list) {
|
|
struct td *next;
|
|
|
|
next = list_entry(tmp, struct td, td_list);
|
|
tmp = next->td_list.next;
|
|
|
|
if (next->urb != urb)
|
|
break;
|
|
|
|
/* NOTE: if multi-td control DATA segments get supported,
|
|
* this urb had one of them, this td wasn't the last td
|
|
* in that segment (TD_R clear), this ed halted because
|
|
* of a short read, _and_ URB_SHORT_NOT_OK is clear ...
|
|
* then we need to leave the control STATUS packet queued
|
|
* and clear ED_SKIP.
|
|
*/
|
|
list_del(&next->td_list);
|
|
urb_priv->td_cnt++;
|
|
ed->hwHeadP = next->hwNextTD | toggle;
|
|
}
|
|
|
|
/* help for troubleshooting: report anything that
|
|
* looks odd ... that doesn't include protocol stalls
|
|
* (or maybe some other things)
|
|
*/
|
|
switch (cc) {
|
|
case TD_CC_DATAUNDERRUN:
|
|
if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
|
|
break;
|
|
/* fallthrough */
|
|
case TD_CC_STALL:
|
|
if (usb_pipecontrol(urb->pipe))
|
|
break;
|
|
/* fallthrough */
|
|
default:
|
|
admhc_dbg (ahcd,
|
|
"urb %p path %s ep%d%s %08x cc %d --> status %d\n",
|
|
urb, urb->dev->devpath,
|
|
usb_pipeendpoint (urb->pipe),
|
|
usb_pipein (urb->pipe) ? "in" : "out",
|
|
hc32_to_cpu(ahcd, td->hwINFO),
|
|
cc, cc_to_error [cc]);
|
|
}
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
/* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
|
|
static void
|
|
finish_unlinks(struct admhcd *ahcd, u16 tick)
|
|
{
|
|
struct ed *ed, **last;
|
|
|
|
rescan_all:
|
|
for (last = &ahcd->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
|
|
struct list_head *entry, *tmp;
|
|
int completed, modified;
|
|
__hc32 *prev;
|
|
|
|
/* only take off EDs that the HC isn't using, accounting for
|
|
* frame counter wraps and EDs with partially retired TDs
|
|
*/
|
|
if (likely(HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state))) {
|
|
if (tick_before (tick, ed->tick)) {
|
|
skip_ed:
|
|
last = &ed->ed_rm_next;
|
|
continue;
|
|
}
|
|
#if 0
|
|
if (!list_empty(&ed->td_list)) {
|
|
struct td *td;
|
|
u32 head;
|
|
|
|
td = list_entry(ed->td_list.next, struct td,
|
|
td_list);
|
|
head = hc32_to_cpu(ahcd, ed->hwHeadP) &
|
|
TD_MASK;
|
|
|
|
/* INTR_WDH may need to clean up first */
|
|
if (td->td_dma != head)
|
|
goto skip_ed;
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/* reentrancy: if we drop the schedule lock, someone might
|
|
* have modified this list. normally it's just prepending
|
|
* entries (which we'd ignore), but paranoia won't hurt.
|
|
*/
|
|
*last = ed->ed_rm_next;
|
|
ed->ed_rm_next = NULL;
|
|
modified = 0;
|
|
|
|
/* unlink urbs as requested, but rescan the list after
|
|
* we call a completion since it might have unlinked
|
|
* another (earlier) urb
|
|
*
|
|
* When we get here, the HC doesn't see this ed. But it
|
|
* must not be rescheduled until all completed URBs have
|
|
* been given back to the driver.
|
|
*/
|
|
rescan_this:
|
|
completed = 0;
|
|
prev = &ed->hwHeadP;
|
|
list_for_each_safe(entry, tmp, &ed->td_list) {
|
|
struct td *td;
|
|
struct urb *urb;
|
|
struct urb_priv *urb_priv;
|
|
__hc32 savebits;
|
|
int status;
|
|
|
|
td = list_entry(entry, struct td, td_list);
|
|
urb = td->urb;
|
|
urb_priv = td->urb->hcpriv;
|
|
|
|
if (!urb->unlinked) {
|
|
prev = &td->hwNextTD;
|
|
continue;
|
|
}
|
|
|
|
if ((urb_priv) == NULL)
|
|
continue;
|
|
|
|
/* patch pointer hc uses */
|
|
savebits = *prev & ~cpu_to_hc32(ahcd, TD_MASK);
|
|
*prev = td->hwNextTD | savebits;
|
|
|
|
/* HC may have partly processed this TD */
|
|
#ifdef ADMHC_VERBOSE_DEBUG
|
|
urb_print(ahcd, urb, "PARTIAL", 0);
|
|
#endif
|
|
status = td_done(ahcd, urb, td);
|
|
|
|
/* if URB is done, clean up */
|
|
if (urb_priv->td_idx == urb_priv->td_cnt) {
|
|
modified = completed = 1;
|
|
finish_urb(ahcd, urb, status);
|
|
}
|
|
}
|
|
if (completed && !list_empty(&ed->td_list))
|
|
goto rescan_this;
|
|
|
|
/* ED's now officially unlinked, hc doesn't see */
|
|
ed->state = ED_IDLE;
|
|
ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
|
|
ed->hwNextED = 0;
|
|
wmb();
|
|
ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP | ED_DEQUEUE);
|
|
|
|
/* but if there's work queued, reschedule */
|
|
if (!list_empty(&ed->td_list)) {
|
|
if (HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state))
|
|
ed_schedule(ahcd, ed);
|
|
}
|
|
|
|
if (modified)
|
|
goto rescan_all;
|
|
}
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
/*
|
|
* Process normal completions (error or success) and clean the schedules.
|
|
*
|
|
* This is the main path for handing urbs back to drivers. The only other
|
|
* path is finish_unlinks(), which unlinks URBs using ed_rm_list, instead of
|
|
* scanning the (re-reversed) donelist as this does.
|
|
*/
|
|
|
|
static void ed_unhalt(struct admhcd *ahcd, struct ed *ed, struct urb *urb)
|
|
{
|
|
struct list_head *entry,*tmp;
|
|
__hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C);
|
|
|
|
#ifdef ADMHC_VERBOSE_DEBUG
|
|
admhc_dump_ed(ahcd, "UNHALT", ed, 0);
|
|
#endif
|
|
/* clear ed halt; this is the td that caused it, but keep it inactive
|
|
* until its urb->complete() has a chance to clean up.
|
|
*/
|
|
ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
|
|
wmb();
|
|
ed->hwHeadP &= ~cpu_to_hc32(ahcd, ED_H);
|
|
|
|
list_for_each_safe(entry, tmp, &ed->td_list) {
|
|
struct td *td = list_entry(entry, struct td, td_list);
|
|
__hc32 info;
|
|
|
|
if (td->urb != urb)
|
|
break;
|
|
|
|
info = td->hwINFO;
|
|
info &= ~cpu_to_hc32(ahcd, TD_CC | TD_OWN);
|
|
td->hwINFO = info;
|
|
|
|
ed->hwHeadP = td->hwNextTD | toggle;
|
|
wmb();
|
|
}
|
|
|
|
}
|
|
|
|
static void ed_intr_refill(struct admhcd *ahcd, struct ed *ed)
|
|
{
|
|
__hc32 toggle = ed->hwHeadP & cpu_to_hc32(ahcd, ED_C);
|
|
|
|
ed->hwHeadP = ed->hwTailP | toggle;
|
|
}
|
|
|
|
|
|
static inline int is_ed_halted(struct admhcd *ahcd, struct ed *ed)
|
|
{
|
|
return ((hc32_to_cpup(ahcd, &ed->hwHeadP) & ED_H) == ED_H);
|
|
}
|
|
|
|
static inline int is_td_halted(struct admhcd *ahcd, struct ed *ed,
|
|
struct td *td)
|
|
{
|
|
return ((hc32_to_cpup(ahcd, &ed->hwHeadP) & TD_MASK) ==
|
|
(hc32_to_cpup(ahcd, &td->hwNextTD) & TD_MASK));
|
|
}
|
|
|
|
static void ed_update(struct admhcd *ahcd, struct ed *ed)
|
|
{
|
|
struct list_head *entry,*tmp;
|
|
|
|
#ifdef ADMHC_VERBOSE_DEBUG
|
|
admhc_dump_ed(ahcd, "UPDATE", ed, 1);
|
|
#endif
|
|
|
|
list_for_each_safe(entry, tmp, &ed->td_list) {
|
|
struct td *td = list_entry(entry, struct td, td_list);
|
|
struct urb *urb = td->urb;
|
|
struct urb_priv *urb_priv = urb->hcpriv;
|
|
int status;
|
|
|
|
if (hc32_to_cpup(ahcd, &td->hwINFO) & TD_OWN)
|
|
break;
|
|
|
|
/* update URB's length and status from TD */
|
|
status = td_done(ahcd, urb, td);
|
|
if (is_ed_halted(ahcd, ed) && is_td_halted(ahcd, ed, td))
|
|
ed_unhalt(ahcd, ed, urb);
|
|
|
|
if (ed->type == PIPE_INTERRUPT)
|
|
ed_intr_refill(ahcd,ed);
|
|
|
|
/* If all this urb's TDs are done, call complete() */
|
|
if (urb_priv->td_idx == urb_priv->td_cnt)
|
|
finish_urb(ahcd, urb, status);
|
|
|
|
/* clean schedule: unlink EDs that are no longer busy */
|
|
if (list_empty(&ed->td_list)) {
|
|
if (ed->state == ED_OPER)
|
|
start_ed_unlink(ahcd, ed);
|
|
|
|
/* ... reenabling halted EDs only after fault cleanup */
|
|
} else if ((ed->hwINFO & cpu_to_hc32(ahcd,
|
|
ED_SKIP | ED_DEQUEUE))
|
|
== cpu_to_hc32(ahcd, ED_SKIP)) {
|
|
td = list_entry(ed->td_list.next, struct td, td_list);
|
|
#if 0
|
|
if (!(td->hwINFO & cpu_to_hc32(ahcd, TD_DONE))) {
|
|
ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP);
|
|
/* ... hc may need waking-up */
|
|
switch (ed->type) {
|
|
case PIPE_CONTROL:
|
|
admhc_writel (ahcd, OHCI_CLF,
|
|
&ahcd->regs->cmdstatus);
|
|
break;
|
|
case PIPE_BULK:
|
|
admhc_writel (ahcd, OHCI_BLF,
|
|
&ahcd->regs->cmdstatus);
|
|
break;
|
|
}
|
|
}
|
|
#else
|
|
if ((td->hwINFO & cpu_to_hc32(ahcd, TD_OWN)))
|
|
ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP);
|
|
#endif
|
|
}
|
|
|
|
}
|
|
}
|
|
|
|
/* there are some tds completed; called in_irq(), with HCD locked */
|
|
static void admhc_td_complete(struct admhcd *ahcd)
|
|
{
|
|
struct ed *ed;
|
|
|
|
for (ed = ahcd->ed_head; ed; ed = ed->ed_next) {
|
|
if (ed->state != ED_OPER)
|
|
continue;
|
|
|
|
ed_update(ahcd, ed);
|
|
}
|
|
}
|