mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-10-30 13:35:19 +02:00
90fba37c49
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@10137 3c298f89-4303-0410-b956-a3cf2f4a3e73
544 lines
14 KiB
C
544 lines
14 KiB
C
/*
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* HND Run Time Environment for standalone MIPS programs.
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*
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* Copyright 2007, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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* $Id$
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*/
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#ifndef _MISPINC_H
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#define _MISPINC_H
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/* MIPS defines */
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#ifdef _LANGUAGE_ASSEMBLY
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/*
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* Symbolic register names for 32 bit ABI
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*/
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#define zero $0 /* wired zero */
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#define AT $1 /* assembler temp - uppercase because of ".set at" */
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#define v0 $2 /* return value */
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#define v1 $3
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#define a0 $4 /* argument registers */
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#define a1 $5
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#define a2 $6
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#define a3 $7
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#define t0 $8 /* caller saved */
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#define t1 $9
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#define t2 $10
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#define t3 $11
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#define t4 $12
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#define t5 $13
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#define t6 $14
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#define t7 $15
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#define s0 $16 /* callee saved */
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#define s1 $17
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#define s2 $18
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#define s3 $19
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#define s4 $20
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#define s5 $21
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#define s6 $22
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#define s7 $23
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#define t8 $24 /* caller saved */
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#define t9 $25
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#define jp $25 /* PIC jump register */
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#define k0 $26 /* kernel scratch */
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#define k1 $27
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#define gp $28 /* global pointer */
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#define sp $29 /* stack pointer */
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#define fp $30 /* frame pointer */
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#define s8 $30 /* same like fp! */
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#define ra $31 /* return address */
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/* CP0 Registers */
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#define C0_INX $0
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#define C0_RAND $1
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#define C0_TLBLO0 $2
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#define C0_TLBLO C0_TLBLO0
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#define C0_TLBLO1 $3
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#define C0_CTEXT $4
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#define C0_PGMASK $5
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#define C0_WIRED $6
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#define C0_INFO $7
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#define C0_BADVADDR $8
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#define C0_COUNT $9
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#define C0_TLBHI $10
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#define C0_COMPARE $11
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#define C0_SR $12
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#define C0_STATUS C0_SR
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#define C0_CAUSE $13
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#define C0_EPC $14
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#define C0_PRID $15
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#define C0_CONFIG $16
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#define C0_LLADDR $17
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#define C0_WATCHLO $18
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#define C0_WATCHHI $19
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#define C0_XCTEXT $20
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#define C0_DIAGNOSTIC $22
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#define C0_BROADCOM C0_DIAGNOSTIC
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#define C0_PERFORMANCE $25
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#define C0_ECC $26
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#define C0_CACHEERR $27
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#define C0_TAGLO $28
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#define C0_TAGHI $29
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#define C0_ERREPC $30
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#define C0_DESAVE $31
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/*
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* LEAF - declare leaf routine
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*/
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#define LEAF(symbol) \
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.globl symbol; \
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.align 2; \
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.type symbol, @function; \
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.ent symbol, 0; \
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symbol: .frame sp, 0, ra
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/*
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* END - mark end of function
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*/
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#define END(function) \
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.end function; \
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.size function, . - function
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#define _ULCAST_
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#define MFC0_SEL(dst, src, sel) \
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.word\t(0x40000000 | ((dst) << 16) | ((src) << 11) | (sel))
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#define MTC0_SEL(dst, src, sel) \
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.word\t(0x40800000 | ((dst) << 16) | ((src) << 11) | (sel))
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#else
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/*
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* The following macros are especially useful for __asm__
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* inline assembler.
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*/
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#ifndef __STR
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#define __STR(x) #x
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#endif
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#ifndef STR
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#define STR(x) __STR(x)
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#endif
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#define _ULCAST_ (unsigned long)
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/* CP0 Registers */
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#define C0_INX 0 /* CP0: TLB Index */
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#define C0_RAND 1 /* CP0: TLB Random */
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#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
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#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
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#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
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#define C0_CTEXT 4 /* CP0: Context */
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#define C0_PGMASK 5 /* CP0: TLB PageMask */
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#define C0_WIRED 6 /* CP0: TLB Wired */
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#define C0_INFO 7 /* CP0: Info */
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#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
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#define C0_COUNT 9 /* CP0: Count */
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#define C0_TLBHI 10 /* CP0: TLB EntryHi */
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#define C0_COMPARE 11 /* CP0: Compare */
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#define C0_SR 12 /* CP0: Processor Status */
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#define C0_STATUS C0_SR /* CP0: Processor Status */
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#define C0_CAUSE 13 /* CP0: Exception Cause */
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#define C0_EPC 14 /* CP0: Exception PC */
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#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
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#define C0_CONFIG 16 /* CP0: Config */
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#define C0_LLADDR 17 /* CP0: LLAddr */
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#define C0_WATCHLO 18 /* CP0: WatchpointLo */
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#define C0_WATCHHI 19 /* CP0: WatchpointHi */
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#define C0_XCTEXT 20 /* CP0: XContext */
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#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
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#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
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#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
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#define C0_ECC 26 /* CP0: ECC */
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#define C0_CACHEERR 27 /* CP0: CacheErr */
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#define C0_TAGLO 28 /* CP0: TagLo */
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#define C0_TAGHI 29 /* CP0: TagHi */
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#define C0_ERREPC 30 /* CP0: ErrorEPC */
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#define C0_DESAVE 31 /* CP0: DebugSave */
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#endif /* _LANGUAGE_ASSEMBLY */
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/*
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* Memory segments (32bit kernel mode addresses)
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*/
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#undef KUSEG
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#undef KSEG0
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#undef KSEG1
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#undef KSEG2
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#undef KSEG3
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#define KUSEG 0x00000000
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#define KSEG0 0x80000000
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#define KSEG1 0xa0000000
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#define KSEG2 0xc0000000
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#define KSEG3 0xe0000000
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#define PHYSADDR_MASK 0x1fffffff
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/*
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* Map an address to a certain kernel segment
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*/
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#undef PHYSADDR
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#undef KSEG0ADDR
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#undef KSEG1ADDR
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#undef KSEG2ADDR
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#undef KSEG3ADDR
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#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
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#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
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#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
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#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
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#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
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#ifndef Index_Invalidate_I
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/*
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* Cache Operations
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*/
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#define Index_Invalidate_I 0x00
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#define Index_Writeback_Inv_D 0x01
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#define Index_Invalidate_SI 0x02
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#define Index_Writeback_Inv_SD 0x03
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#define Index_Load_Tag_I 0x04
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#define Index_Load_Tag_D 0x05
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#define Index_Load_Tag_SI 0x06
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#define Index_Load_Tag_SD 0x07
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#define Index_Store_Tag_I 0x08
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#define Index_Store_Tag_D 0x09
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#define Index_Store_Tag_SI 0x0A
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#define Index_Store_Tag_SD 0x0B
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#define Create_Dirty_Excl_D 0x0d
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#define Create_Dirty_Excl_SD 0x0f
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#define Hit_Invalidate_I 0x10
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#define Hit_Invalidate_D 0x11
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#define Hit_Invalidate_SI 0x12
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#define Hit_Invalidate_SD 0x13
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#define Fill_I 0x14
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#define Hit_Writeback_Inv_D 0x15
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/* 0x16 is unused */
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#define Hit_Writeback_Inv_SD 0x17
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#define R5K_Page_Invalidate_S 0x17
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#define Hit_Writeback_I 0x18
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#define Hit_Writeback_D 0x19
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/* 0x1a is unused */
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#define Hit_Writeback_SD 0x1b
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/* 0x1c is unused */
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/* 0x1e is unused */
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#define Hit_Set_Virtual_SI 0x1e
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#define Hit_Set_Virtual_SD 0x1f
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#endif /* !Index_Invalidate_I */
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/*
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* R4x00 interrupt enable / cause bits
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*/
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#define IE_SW0 (_ULCAST_(1) << 8)
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#define IE_SW1 (_ULCAST_(1) << 9)
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#define IE_IRQ0 (_ULCAST_(1) << 10)
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#define IE_IRQ1 (_ULCAST_(1) << 11)
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#define IE_IRQ2 (_ULCAST_(1) << 12)
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#define IE_IRQ3 (_ULCAST_(1) << 13)
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#define IE_IRQ4 (_ULCAST_(1) << 14)
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#define IE_IRQ5 (_ULCAST_(1) << 15)
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#ifndef ST0_UM
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/*
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* Bitfields in the mips32 cp0 status register
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*/
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#define ST0_IE 0x00000001
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#define ST0_EXL 0x00000002
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#define ST0_ERL 0x00000004
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#define ST0_UM 0x00000010
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#define ST0_SWINT0 0x00000100
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#define ST0_SWINT1 0x00000200
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#define ST0_HWINT0 0x00000400
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#define ST0_HWINT1 0x00000800
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#define ST0_HWINT2 0x00001000
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#define ST0_HWINT3 0x00002000
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#define ST0_HWINT4 0x00004000
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#define ST0_HWINT5 0x00008000
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#define ST0_IM 0x0000ff00
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#define ST0_NMI 0x00080000
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#define ST0_SR 0x00100000
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#define ST0_TS 0x00200000
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#define ST0_BEV 0x00400000
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#define ST0_RE 0x02000000
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#define ST0_RP 0x08000000
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#define ST0_CU 0xf0000000
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#define ST0_CU0 0x10000000
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#define ST0_CU1 0x20000000
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#define ST0_CU2 0x40000000
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#define ST0_CU3 0x80000000
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#endif /* !ST0_UM */
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/*
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* Bitfields in the mips32 cp0 cause register
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*/
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#define C_EXC 0x0000007c
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#define C_EXC_SHIFT 2
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#define C_INT 0x0000ff00
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#define C_INT_SHIFT 8
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#define C_SW0 (_ULCAST_(1) << 8)
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#define C_SW1 (_ULCAST_(1) << 9)
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#define C_IRQ0 (_ULCAST_(1) << 10)
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#define C_IRQ1 (_ULCAST_(1) << 11)
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#define C_IRQ2 (_ULCAST_(1) << 12)
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#define C_IRQ3 (_ULCAST_(1) << 13)
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#define C_IRQ4 (_ULCAST_(1) << 14)
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#define C_IRQ5 (_ULCAST_(1) << 15)
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#define C_WP 0x00400000
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#define C_IV 0x00800000
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#define C_CE 0x30000000
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#define C_CE_SHIFT 28
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#define C_BD 0x80000000
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/* Values in C_EXC */
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#define EXC_INT 0
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#define EXC_TLBM 1
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#define EXC_TLBL 2
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#define EXC_TLBS 3
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#define EXC_AEL 4
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#define EXC_AES 5
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#define EXC_IBE 6
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#define EXC_DBE 7
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#define EXC_SYS 8
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#define EXC_BPT 9
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#define EXC_RI 10
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#define EXC_CU 11
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#define EXC_OV 12
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#define EXC_TR 13
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#define EXC_WATCH 23
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#define EXC_MCHK 24
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/*
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* Bits in the cp0 config register.
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*/
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#define CONF_CM_CACHABLE_NO_WA 0
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#define CONF_CM_CACHABLE_WA 1
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#define CONF_CM_UNCACHED 2
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#define CONF_CM_CACHABLE_NONCOHERENT 3
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#define CONF_CM_CACHABLE_CE 4
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#define CONF_CM_CACHABLE_COW 5
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#define CONF_CM_CACHABLE_CUW 6
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#define CONF_CM_CACHABLE_ACCELERATED 7
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#define CONF_CM_CMASK 7
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#define CONF_CU (_ULCAST_(1) << 3)
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#define CONF_DB (_ULCAST_(1) << 4)
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#define CONF_IB (_ULCAST_(1) << 5)
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#define CONF_SE (_ULCAST_(1) << 12)
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#ifndef CONF_BE /* duplicate in mipsregs.h */
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#define CONF_BE (_ULCAST_(1) << 15)
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#endif
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#define CONF_SC (_ULCAST_(1) << 17)
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#define CONF_AC (_ULCAST_(1) << 23)
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#define CONF_HALT (_ULCAST_(1) << 25)
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#ifndef CONF_M /* duplicate in mipsregs.h */
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#define CONF_M (_ULCAST_(1) << 31)
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#endif
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/*
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* Bits in the cp0 config register select 1.
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*/
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#define CONF1_FP 0x00000001 /* FPU present */
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#define CONF1_EP 0x00000002 /* EJTAG present */
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#define CONF1_CA 0x00000004 /* mips16 implemented */
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#define CONF1_WR 0x00000008 /* Watch registers present */
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#define CONF1_PC 0x00000010 /* Performance counters present */
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#define CONF1_DA_SHIFT 7 /* D$ associativity */
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#define CONF1_DA_MASK 0x00000380
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#define CONF1_DA_BASE 1
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#define CONF1_DL_SHIFT 10 /* D$ line size */
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#define CONF1_DL_MASK 0x00001c00
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#define CONF1_DL_BASE 2
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#define CONF1_DS_SHIFT 13 /* D$ sets/way */
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#define CONF1_DS_MASK 0x0000e000
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#define CONF1_DS_BASE 64
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#define CONF1_IA_SHIFT 16 /* I$ associativity */
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#define CONF1_IA_MASK 0x00070000
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#define CONF1_IA_BASE 1
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#define CONF1_IL_SHIFT 19 /* I$ line size */
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#define CONF1_IL_MASK 0x00380000
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#define CONF1_IL_BASE 2
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#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
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#define CONF1_IS_MASK 0x01c00000
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#define CONF1_IS_BASE 64
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#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
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#define CONF1_MS_SHIFT 25
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/* PRID register */
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#define PRID_COPT_MASK 0xff000000
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#define PRID_COMP_MASK 0x00ff0000
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#define PRID_IMP_MASK 0x0000ff00
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#define PRID_REV_MASK 0x000000ff
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#define PRID_COMP_LEGACY 0x000000
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#define PRID_COMP_MIPS 0x010000
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#define PRID_COMP_BROADCOM 0x020000
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#define PRID_COMP_ALCHEMY 0x030000
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#define PRID_COMP_SIBYTE 0x040000
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#define PRID_IMP_BCM4710 0x4000
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#define PRID_IMP_BCM3302 0x9000
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#define PRID_IMP_BCM3303 0x9100
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#define PRID_IMP_UNKNOWN 0xff00
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#define BCM330X(id) \
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(((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
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(PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) || \
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((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == \
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(PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
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/* Bits in C0_BROADCOM */
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#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
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#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
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#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
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#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
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#define BRCM_CLF_ENABLE 0x00100000 /* Enable cache line first feature */
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/* PreFetch Cache aka Read Ahead Cache */
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#define PFC_CR0 0xff400000 /* control reg 0 */
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#define PFC_CR1 0xff400004 /* control reg 1 */
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/* PFC operations */
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#define PFC_I 0x00000001 /* Enable PFC use for instructions */
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#define PFC_D 0x00000002 /* Enable PFC use for data */
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#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
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#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
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#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
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#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
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#define PFC_DPF 0x00000040 /* Enable directional prefetching */
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#define PFC_FLUSH 0x00000100 /* Flush the PFC */
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#define PFC_BRR 0x40000000 /* Bus error indication */
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#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
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/* Handy defaults */
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#define PFC_DISABLED 0
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#define PFC_AUTO 0xffffffff /* auto select the default mode */
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#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
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#define PFC_INST_NOPF (PFC_I | PFC_CINV)
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#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
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#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
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#define PFC_I_AND_D (PFC_INST | PFC_DATA)
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#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
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#ifndef _LANGUAGE_ASSEMBLY
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/*
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* Macros to access the system control coprocessor
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*/
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#define MFC0(source, sel) \
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({ \
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int __res; \
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__asm__ __volatile__(" \
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.set\tnoreorder; \
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.set\tnoat; \
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.word\t"STR(0x40010000 | ((source) << 11) | (sel))"; \
|
|
move\t%0, $1; \
|
|
.set\tat; \
|
|
.set\treorder" \
|
|
:"=r" (__res) \
|
|
: \
|
|
:"$1"); \
|
|
__res; \
|
|
})
|
|
|
|
#define MTC0(source, sel, value) \
|
|
do { \
|
|
__asm__ __volatile__(" \
|
|
.set\tnoreorder; \
|
|
.set\tnoat; \
|
|
move\t$1, %z0; \
|
|
.word\t"STR(0x40810000 | ((source) << 11) | (sel))"; \
|
|
.set\tat; \
|
|
.set\treorder" \
|
|
: \
|
|
:"jr" (value) \
|
|
:"$1"); \
|
|
} while (0)
|
|
|
|
#define get_c0_count() \
|
|
({ \
|
|
int __res; \
|
|
__asm__ __volatile__(" \
|
|
.set\tnoreorder; \
|
|
.set\tnoat; \
|
|
mfc0\t%0, $9; \
|
|
.set\tat; \
|
|
.set\treorder" \
|
|
:"=r" (__res)); \
|
|
__res; \
|
|
})
|
|
|
|
static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
|
|
{
|
|
uint lsz, sets, ways;
|
|
|
|
/* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
|
|
if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
|
|
lsz = CONF1_IL_BASE << lsz;
|
|
sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
|
|
ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
|
|
*size = lsz * sets * ways;
|
|
*lsize = lsz;
|
|
}
|
|
|
|
static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
|
|
{
|
|
uint lsz, sets, ways;
|
|
|
|
/* Data Cache Size = Associativity * Line Size * Sets Per Way */
|
|
if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
|
|
lsz = CONF1_DL_BASE << lsz;
|
|
sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
|
|
ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
|
|
*size = lsz * sets * ways;
|
|
*lsize = lsz;
|
|
}
|
|
|
|
#define cache_op(base, op) \
|
|
__asm__ __volatile__(" \
|
|
.set noreorder; \
|
|
.set mips3; \
|
|
cache %1, (%0); \
|
|
.set mips0; \
|
|
.set reorder" \
|
|
: \
|
|
: "r" (base), \
|
|
"i" (op));
|
|
|
|
#define cache_unroll4(base, delta, op) \
|
|
__asm__ __volatile__(" \
|
|
.set noreorder; \
|
|
.set mips3; \
|
|
cache %1, 0(%0); \
|
|
cache %1, delta(%0); \
|
|
cache %1, (2 * delta)(%0); \
|
|
cache %1, (3 * delta)(%0); \
|
|
.set mips0; \
|
|
.set reorder" \
|
|
: \
|
|
: "r" (base), \
|
|
"i" (op));
|
|
|
|
#endif /* !_LANGUAGE_ASSEMBLY */
|
|
|
|
#endif /* _MISPINC_H */
|