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64 lines
1.5 KiB
ArmAsm
64 lines
1.5 KiB
ArmAsm
/*
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* Startup Code for MIPS32 XBURST CPU-core
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*
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* Copyright (c) 2010 Xiangfu Liu <xiangfu@sharism.cc>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 3 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/cacheops.h>
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#include <asm/jz4740.h>
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.set noreorder
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.globl _start
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.text
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_start:
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.word JZ4740_NANDBOOT_CFG /* fetched during NAND Boot */
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reset:
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/*
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* STATUS register
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* CU0=UM=EXL=IE=0, BEV=ERL=1, IP2~7=1
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*/
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li t0, 0x0040FC04
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mtc0 t0, CP0_STATUS
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/* CAUSE register
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* IV=1, use the specical interrupt vector (0x200) */
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li t1, 0x00800000
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mtc0 t1, CP0_CAUSE
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bal 1f
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nop
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.word _GLOBAL_OFFSET_TABLE_
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1:
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move gp, ra
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lw t1, 0(ra)
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move gp, t1
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la sp, 0x80004000
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la t9, nand_boot
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j t9
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nop
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