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cc966472c3
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@8728 3c298f89-4303-0410-b956-a3cf2f4a3e73
101 lines
3.3 KiB
C
101 lines
3.3 KiB
C
/*
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* $Id$
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*
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* ADM5120 MPMC (Multiport Memory Controller) register definitions
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*
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* Copyright (C) 2007 OpenWrt.org
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* Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the
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* Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
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* Boston, MA 02110-1301, USA.
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*
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*/
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#ifndef _ADM5120_MPMC_H_
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#define _ADM5120_MPMC_H_
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#define MPMC_READ_REG(r) __raw_readl( \
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(void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r)
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#define MPMC_WRITE_REG(r, v) __raw_writel((v), \
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(void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r)
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#define MPMC_REG_CTRL 0x0000
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#define MPMC_REG_STATUS 0x0004
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#define MPMC_REG_CONF 0x0008
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#define MPMC_REG_DC 0x0020
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#define MPMC_REG_DR 0x0024
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#define MPMC_REG_DRP 0x0030
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#define MPMC_REG_DC0 0x0100
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#define MPMC_REG_DRC0 0x0104
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#define MPMC_REG_DC1 0x0120
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#define MPMC_REG_DRC1 0x0124
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#define MPMC_REG_DC2 0x0140
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#define MPMC_REG_DRC2 0x0144
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#define MPMC_REG_DC3 0x0160
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#define MPMC_REG_DRC3 0x0164
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#define MPMC_REG_SC0 0x0200 /* for F_CS1_N */
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#define MPMC_REG_SC1 0x0220 /* for F_CS0_N */
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#define MPMC_REG_SC2 0x0240
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#define MPMC_REG_SC3 0x0260
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/* Control register bits */
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#define MPMC_CTRL_AM ( 1 << 1 ) /* Address Mirror */
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#define MPMC_CTRL_LPM ( 1 << 2 ) /* Low Power Mode */
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#define MPMC_CTRL_DWB ( 1 << 3 ) /* Drain Write Buffers */
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/* Status register bits */
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#define MPMC_STATUS_BUSY ( 1 << 0 ) /* Busy */
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#define MPMC_STATUS_WBS ( 1 << 1 ) /* Write Buffer Status */
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#define MPMC_STATUS_SRA ( 1 << 2 ) /* Self-Refresh Acknowledge*/
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/* Dynamic Control register bits */
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#define MPMC_DC_CE ( 1 << 0 )
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#define MPMC_DC_DMC ( 1 << 1 )
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#define MPMC_DC_SRR ( 1 << 2 )
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#define MPMC_DC_SI_SHIFT 7
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#define MPMC_DC_SI_MASK ( 3 << 7 )
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#define MPMC_DC_SI_NORMAL ( 0 << 7 )
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#define MPMC_DC_SI_MODE ( 1 << 7 )
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#define MPMC_DC_SI_PALL ( 2 << 7 )
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#define MPMC_DC_SI_NOP ( 3 << 7 )
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#define SRAM_REG_CONF 0x00
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#define SRAM_REG_WWE 0x04
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#define SRAM_REG_WOE 0x08
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#define SRAM_REG_WRD 0x0C
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#define SRAM_REG_WPG 0x10
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#define SRAM_REG_WWR 0x14
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#define SRAM_REG_WTR 0x18
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/* Dynamic Configuration register bits */
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#define DC_BE (1 << 19) /* buffer enable */
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#define DC_RW_SHIFT 28 /* shift for number of rows */
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#define DC_RW_MASK 0x03
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#define DC_NB_SHIFT 26 /* shift for number of banks */
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#define DC_NB_MASK 0x01
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#define DC_CW_SHIFT 22 /* shift for number of columns */
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#define DC_CW_MASK 0x07
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#define DC_DW_SHIFT 7 /* shift for device width */
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#define DC_DW_MASK 0x03
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/* Static Configuration register bits */
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#define SC_MW_MASK 0x03 /* memory width mask */
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#define SC_MW_8 0x00 /* 8 bit memory width */
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#define SC_MW_16 0x01 /* 16 bit memory width */
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#define SC_MW_32 0x02 /* 32 bit memory width */
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#endif /* _ADM5120_MPMC_H_ */
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