mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-25 13:44:58 +02:00
55877ca580
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16144 3c298f89-4303-0410-b956-a3cf2f4a3e73
492 lines
14 KiB
Diff
492 lines
14 KiB
Diff
--- a/arch/mips/kernel/entry.S
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+++ b/arch/mips/kernel/entry.S
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@@ -100,6 +100,10 @@ END(except_vec1_generic)
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* and R4400 SC and MC versions.
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*/
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NESTED(except_vec3_generic, 0, sp)
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+#ifdef CONFIG_BCM4710
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+ nop
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+ nop
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+#endif
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#if R5432_CP0_INTERRUPT_WAR
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mfc0 k0, CP0_INDEX
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#endif
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--- a/arch/mips/mm/c-r4k.c
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+++ b/arch/mips/mm/c-r4k.c
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@@ -14,6 +14,12 @@
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#include <linux/mm.h>
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#include <linux/bitops.h>
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+#ifdef CONFIG_BCM4710
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+#include "../bcm947xx/include/typedefs.h"
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+#include "../bcm947xx/include/sbconfig.h"
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+#include <asm/paccess.h>
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+#endif
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+
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#include <asm/bcache.h>
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#include <asm/bootinfo.h>
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#include <asm/cacheops.h>
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@@ -40,6 +46,7 @@ static struct bcache_ops no_sc_ops = {
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.bc_inv = (void *)no_sc_noop
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};
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+int bcm4710 = 0;
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struct bcache_ops *bcops = &no_sc_ops;
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#define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010)
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@@ -64,8 +71,10 @@ static inline void r4k_blast_dcache_page
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static inline void r4k_blast_dcache_page_setup(void)
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{
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unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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-
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- if (dc_lsize == 16)
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+
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+ if (bcm4710)
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+ r4k_blast_dcache_page = blast_dcache_page;
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+ else if (dc_lsize == 16)
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r4k_blast_dcache_page = blast_dcache16_page;
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else if (dc_lsize == 32)
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r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
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@@ -77,7 +86,9 @@ static void r4k_blast_dcache_page_indexe
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{
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unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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- if (dc_lsize == 16)
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+ if (bcm4710)
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+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
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+ else if (dc_lsize == 16)
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r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
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else if (dc_lsize == 32)
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r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
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@@ -89,7 +100,9 @@ static inline void r4k_blast_dcache_setu
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{
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unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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- if (dc_lsize == 16)
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+ if (bcm4710)
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+ r4k_blast_dcache = blast_dcache;
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+ else if (dc_lsize == 16)
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r4k_blast_dcache = blast_dcache16;
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else if (dc_lsize == 32)
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r4k_blast_dcache = blast_dcache32;
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@@ -266,6 +279,7 @@ static void r4k___flush_cache_all(void)
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r4k_blast_dcache();
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r4k_blast_icache();
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+ if (!bcm4710)
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switch (current_cpu_data.cputype) {
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case CPU_R4000SC:
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case CPU_R4000MC:
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@@ -304,10 +318,10 @@ static void r4k_flush_cache_mm(struct mm
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* Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
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* only flush the primary caches but R10000 and R12000 behave sane ...
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*/
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- if (current_cpu_data.cputype == CPU_R4000SC ||
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+ if (!bcm4710 && (current_cpu_data.cputype == CPU_R4000SC ||
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current_cpu_data.cputype == CPU_R4000MC ||
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current_cpu_data.cputype == CPU_R4400SC ||
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- current_cpu_data.cputype == CPU_R4400MC)
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+ current_cpu_data.cputype == CPU_R4400MC))
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r4k_blast_scache();
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}
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@@ -383,12 +397,15 @@ static void r4k_flush_icache_range(unsig
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unsigned long ic_lsize = current_cpu_data.icache.linesz;
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unsigned long addr, aend;
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+ addr = start & ~(dc_lsize - 1);
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+ aend = (end - 1) & ~(dc_lsize - 1);
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+
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if (!cpu_has_ic_fills_f_dc) {
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if (end - start > dcache_size)
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r4k_blast_dcache();
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else {
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- addr = start & ~(dc_lsize - 1);
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- aend = (end - 1) & ~(dc_lsize - 1);
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+ BCM4710_PROTECTED_FILL_TLB(addr);
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+ BCM4710_PROTECTED_FILL_TLB(aend);
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while (1) {
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/* Hit_Writeback_Inv_D */
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@@ -403,8 +420,6 @@ static void r4k_flush_icache_range(unsig
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if (end - start > icache_size)
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r4k_blast_icache();
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else {
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- addr = start & ~(ic_lsize - 1);
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- aend = (end - 1) & ~(ic_lsize - 1);
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while (1) {
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/* Hit_Invalidate_I */
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protected_flush_icache_line(addr);
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@@ -413,6 +428,9 @@ static void r4k_flush_icache_range(unsig
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addr += ic_lsize;
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}
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}
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+
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+ if (bcm4710)
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+ flush_cache_all();
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}
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/*
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@@ -443,7 +461,8 @@ static void r4k_flush_icache_page(struct
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if (cpu_has_subset_pcaches) {
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unsigned long addr = (unsigned long) page_address(page);
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- r4k_blast_scache_page(addr);
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+ if (!bcm4710)
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+ r4k_blast_scache_page(addr);
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ClearPageDcacheDirty(page);
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return;
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@@ -451,6 +470,7 @@ static void r4k_flush_icache_page(struct
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if (!cpu_has_ic_fills_f_dc) {
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unsigned long addr = (unsigned long) page_address(page);
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+
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r4k_blast_dcache_page(addr);
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ClearPageDcacheDirty(page);
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}
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@@ -477,7 +497,7 @@ static void r4k_dma_cache_wback_inv(unsi
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/* Catch bad driver code */
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BUG_ON(size == 0);
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- if (cpu_has_subset_pcaches) {
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+ if (!bcm4710 && cpu_has_subset_pcaches) {
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unsigned long sc_lsize = current_cpu_data.scache.linesz;
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if (size >= scache_size) {
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@@ -509,6 +529,8 @@ static void r4k_dma_cache_wback_inv(unsi
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R4600_HIT_CACHEOP_WAR_IMPL;
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a = addr & ~(dc_lsize - 1);
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end = (addr + size - 1) & ~(dc_lsize - 1);
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+ BCM4710_FILL_TLB(a);
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+ BCM4710_FILL_TLB(end);
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while (1) {
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flush_dcache_line(a); /* Hit_Writeback_Inv_D */
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if (a == end)
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@@ -527,7 +549,7 @@ static void r4k_dma_cache_inv(unsigned l
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/* Catch bad driver code */
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BUG_ON(size == 0);
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- if (cpu_has_subset_pcaches) {
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+ if (!bcm4710 && (cpu_has_subset_pcaches)) {
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unsigned long sc_lsize = current_cpu_data.scache.linesz;
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if (size >= scache_size) {
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@@ -554,6 +576,8 @@ static void r4k_dma_cache_inv(unsigned l
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R4600_HIT_CACHEOP_WAR_IMPL;
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a = addr & ~(dc_lsize - 1);
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end = (addr + size - 1) & ~(dc_lsize - 1);
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+ BCM4710_FILL_TLB(a);
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+ BCM4710_FILL_TLB(end);
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while (1) {
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flush_dcache_line(a); /* Hit_Writeback_Inv_D */
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if (a == end)
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@@ -577,6 +601,8 @@ static void r4k_flush_cache_sigtramp(uns
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unsigned long dc_lsize = current_cpu_data.dcache.linesz;
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R4600_HIT_CACHEOP_WAR_IMPL;
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+ BCM4710_PROTECTED_FILL_TLB(addr);
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+ BCM4710_PROTECTED_FILL_TLB(addr + 4);
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protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
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protected_flush_icache_line(addr & ~(ic_lsize - 1));
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if (MIPS4K_ICACHE_REFILL_WAR) {
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@@ -986,10 +1012,12 @@ static void __init setup_scache(void)
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case CPU_R4000MC:
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case CPU_R4400SC:
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case CPU_R4400MC:
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- probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
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- sc_present = probe_scache_kseg1(config);
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- if (sc_present)
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- c->options |= MIPS_CPU_CACHE_CDEX_S;
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+ if (!bcm4710) {
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+ probe_scache_kseg1 = (probe_func_t) (KSEG1ADDR(&probe_scache));
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+ sc_present = probe_scache_kseg1(config);
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+ if (sc_present)
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+ c->options |= MIPS_CPU_CACHE_CDEX_S;
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+ }
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break;
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case CPU_R10000:
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@@ -1041,6 +1069,19 @@ static void __init setup_scache(void)
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static inline void coherency_setup(void)
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{
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change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
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+
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+#if defined(CONFIG_BCM4310) || defined(CONFIG_BCM4704) || defined(CONFIG_BCM5365)
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+ if (BCM330X(current_cpu_data.processor_id)) {
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+ uint32 cm;
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+
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+ cm = read_c0_diag();
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+ /* Enable icache */
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+ cm |= (1 << 31);
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+ /* Enable dcache */
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+ cm |= (1 << 30);
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+ write_c0_diag(cm);
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+ }
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+#endif
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/*
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* c0_status.cu=0 specifies that updates by the sc instruction use
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@@ -1073,6 +1114,12 @@ void __init ld_mmu_r4xx0(void)
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memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
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memcpy((void *)(KSEG1 + 0x100), &except_vec2_generic, 0x80);
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+ if (current_cpu_data.cputype == CPU_BCM4710 && (current_cpu_data.processor_id & PRID_REV_MASK) == 0) {
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+ printk("Enabling BCM4710A0 cache workarounds.\n");
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+ bcm4710 = 1;
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+ } else
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+ bcm4710 = 0;
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+
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probe_pcache();
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setup_scache();
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--- a/arch/mips/mm/tlbex-mips32.S
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+++ b/arch/mips/mm/tlbex-mips32.S
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@@ -90,6 +90,9 @@
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.set noat
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LEAF(except_vec0_r4000)
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.set mips3
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+#ifdef CONFIG_BCM4704
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+ nop
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+#endif
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#ifdef CONFIG_SMP
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mfc0 k1, CP0_CONTEXT
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la k0, pgd_current
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--- a/include/asm-mips/r4kcache.h
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+++ b/include/asm-mips/r4kcache.h
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@@ -15,6 +15,18 @@
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#include <asm/asm.h>
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#include <asm/cacheops.h>
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+#ifdef CONFIG_BCM4710
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+#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
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+
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+#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
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+#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
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+#else
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+#define BCM4710_DUMMY_RREG()
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+
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+#define BCM4710_FILL_TLB(addr)
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+#define BCM4710_PROTECTED_FILL_TLB(addr)
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+#endif
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+
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#define cache_op(op,addr) \
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__asm__ __volatile__( \
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" .set noreorder \n" \
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@@ -27,12 +39,25 @@
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static inline void flush_icache_line_indexed(unsigned long addr)
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{
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- cache_op(Index_Invalidate_I, addr);
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+ unsigned int way;
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+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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+
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+ for (way = 0; way < current_cpu_data.dcache.ways; way++) {
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+ cache_op(Index_Invalidate_I, addr);
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+ addr += ws_inc;
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+ }
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}
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static inline void flush_dcache_line_indexed(unsigned long addr)
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{
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- cache_op(Index_Writeback_Inv_D, addr);
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+ unsigned int way;
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+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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+
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+ for (way = 0; way < current_cpu_data.dcache.ways; way++) {
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+ BCM4710_DUMMY_RREG();
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+ cache_op(Index_Writeback_Inv_D, addr);
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+ addr += ws_inc;
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+ }
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}
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static inline void flush_scache_line_indexed(unsigned long addr)
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@@ -47,6 +72,7 @@ static inline void flush_icache_line(uns
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static inline void flush_dcache_line(unsigned long addr)
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{
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+ BCM4710_DUMMY_RREG();
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cache_op(Hit_Writeback_Inv_D, addr);
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}
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@@ -91,6 +117,7 @@ static inline void protected_flush_icach
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*/
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static inline void protected_writeback_dcache_line(unsigned long addr)
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{
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+ BCM4710_DUMMY_RREG();
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__asm__ __volatile__(
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".set noreorder\n\t"
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".set mips3\n"
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@@ -138,6 +165,62 @@ static inline void invalidate_tcache_pag
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: "r" (base), \
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"i" (op));
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+#define cache_unroll(base,op) \
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+ __asm__ __volatile__(" \
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+ .set noreorder; \
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+ .set mips3; \
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+ cache %1, (%0); \
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+ .set mips0; \
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+ .set reorder" \
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+ : \
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+ : "r" (base), \
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+ "i" (op));
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+
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+
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+static inline void blast_dcache(void)
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+{
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+ unsigned long start = KSEG0;
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+ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
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+ unsigned long end = (start + dcache_size);
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+
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+ while(start < end) {
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+ BCM4710_DUMMY_RREG();
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+ cache_unroll(start,Index_Writeback_Inv_D);
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+ start += current_cpu_data.dcache.linesz;
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+ }
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+}
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+
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+static inline void blast_dcache_page(unsigned long page)
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+{
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+ unsigned long start = page;
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+ unsigned long end = start + PAGE_SIZE;
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+
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+ BCM4710_FILL_TLB(start);
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+ do {
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+ BCM4710_DUMMY_RREG();
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+ cache_unroll(start,Hit_Writeback_Inv_D);
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+ start += current_cpu_data.dcache.linesz;
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+ } while (start < end);
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+}
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+
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+static inline void blast_dcache_page_indexed(unsigned long page)
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+{
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+ unsigned long start = page;
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+ unsigned long end = start + PAGE_SIZE;
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+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
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+ unsigned long ws_end = current_cpu_data.dcache.ways <<
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+ current_cpu_data.dcache.waybit;
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+ unsigned long ws, addr;
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+
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+ for (ws = 0; ws < ws_end; ws += ws_inc) {
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+ start = page + ws;
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+ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
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+ BCM4710_DUMMY_RREG();
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+ cache_unroll(addr,Index_Writeback_Inv_D);
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+ }
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+ }
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+}
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+
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static inline void blast_dcache16(void)
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{
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unsigned long start = KSEG0;
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@@ -148,8 +231,9 @@ static inline void blast_dcache16(void)
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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- for (addr = start; addr < end; addr += 0x200)
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+ for (addr = start; addr < end; addr += 0x200) {
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cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
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+ }
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}
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static inline void blast_dcache16_page(unsigned long page)
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@@ -173,8 +257,9 @@ static inline void blast_dcache16_page_i
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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- for (addr = start; addr < end; addr += 0x200)
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+ for (addr = start; addr < end; addr += 0x200) {
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cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
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+ }
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}
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static inline void blast_icache16(void)
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@@ -196,6 +281,7 @@ static inline void blast_icache16_page(u
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unsigned long start = page;
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unsigned long end = start + PAGE_SIZE;
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+ BCM4710_FILL_TLB(start);
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do {
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cache16_unroll32(start,Hit_Invalidate_I);
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start += 0x200;
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@@ -281,6 +367,7 @@ static inline void blast_scache16_page_i
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: "r" (base), \
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"i" (op));
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+
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static inline void blast_dcache32(void)
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{
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unsigned long start = KSEG0;
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@@ -291,8 +378,9 @@ static inline void blast_dcache32(void)
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
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- for (addr = start; addr < end; addr += 0x400)
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+ for (addr = start; addr < end; addr += 0x400) {
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cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
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+ }
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}
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static inline void blast_dcache32_page(unsigned long page)
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@@ -316,8 +404,9 @@ static inline void blast_dcache32_page_i
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unsigned long ws, addr;
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for (ws = 0; ws < ws_end; ws += ws_inc)
|
|
- for (addr = start; addr < end; addr += 0x400)
|
|
+ for (addr = start; addr < end; addr += 0x400) {
|
|
cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
|
|
+ }
|
|
}
|
|
|
|
static inline void blast_icache32(void)
|
|
@@ -339,6 +428,7 @@ static inline void blast_icache32_page(u
|
|
unsigned long start = page;
|
|
unsigned long end = start + PAGE_SIZE;
|
|
|
|
+ BCM4710_FILL_TLB(start);
|
|
do {
|
|
cache32_unroll32(start,Hit_Invalidate_I);
|
|
start += 0x400;
|
|
@@ -443,6 +533,7 @@ static inline void blast_icache64_page(u
|
|
unsigned long start = page;
|
|
unsigned long end = start + PAGE_SIZE;
|
|
|
|
+ BCM4710_FILL_TLB(start);
|
|
do {
|
|
cache64_unroll32(start,Hit_Invalidate_I);
|
|
start += 0x800;
|
|
--- a/include/asm-mips/stackframe.h
|
|
+++ b/include/asm-mips/stackframe.h
|
|
@@ -209,6 +209,20 @@
|
|
|
|
#endif
|
|
|
|
+#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4704)
|
|
+
|
|
+#undef RESTORE_SP_AND_RET
|
|
+#define RESTORE_SP_AND_RET \
|
|
+ lw sp, PT_R29(sp); \
|
|
+ .set mips3; \
|
|
+ nop; \
|
|
+ nop; \
|
|
+ eret; \
|
|
+ .set mips0
|
|
+
|
|
+#endif
|
|
+
|
|
+
|
|
#define RESTORE_SP \
|
|
lw sp, PT_R29(sp); \
|
|
|
|
--- a/mm/memory.c
|
|
+++ b/mm/memory.c
|
|
@@ -927,6 +927,7 @@ static inline void break_cow(struct vm_a
|
|
flush_page_to_ram(new_page);
|
|
flush_cache_page(vma, address);
|
|
establish_pte(vma, address, page_table, pte_mkwrite(pte_mkdirty(mk_pte(new_page, vma->vm_page_prot))));
|
|
+ flush_icache_page(vma, new_page);
|
|
}
|
|
|
|
/*
|