mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-25 09:38:26 +02:00
acb3c6bb2e
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@17733 3c298f89-4303-0410-b956-a3cf2f4a3e73
64 lines
1.9 KiB
Diff
64 lines
1.9 KiB
Diff
This patch significantly improves the reliability of high speed
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usb writes on the bcm5354. It implements a work around for version 2
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of the usb20 core that was cribbed from the GPL sources for the
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Asus wl500gpv2 and verified against the wl520gu sources.
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Reference:
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GPL/WL-520gu-NewUI/src/linux/linux/arch/mips/brcm-boards/bcm947xx/pcibios.c
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GPL/WL-500gPV2-NewUI/src/linux/linux/arch/mips/brcm-boards/bcm947xx/pcibios.c
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Signed-off-by: Steve Brown <sbrown@cortland.com>
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---
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drivers/usb/host/ohci-ssb.c | 37 +++++++++++++++++++++++--------------
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1 file changed, 23 insertions(+), 14 deletions(-)
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--- a/drivers/usb/host/ohci-ssb.c
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+++ b/drivers/usb/host/ohci-ssb.c
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@@ -141,22 +141,31 @@ static int ssb_ohci_attach(struct ssb_de
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*/
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ssb_device_enable(dev, 0);
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ssb_write32(dev, 0x200, 0x7ff);
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+
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+ /* Change Flush control reg */
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+ tmp = ssb_read32(dev, 0x400);
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+ tmp &= ~8;
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+ ssb_write32(dev, 0x400, tmp);
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+ tmp = ssb_read32(dev, 0x400);
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+
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+ /* Change Shim control reg */
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+ tmp = ssb_read32(dev, 0x304);
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+ tmp &= ~0x100;
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+ ssb_write32(dev, 0x304, tmp);
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+ tmp = ssb_read32(dev, 0x304);
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+
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udelay(1);
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- if (dev->id.revision == 1) { // bug in rev 1
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- /* Change Flush control reg */
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- tmp = ssb_read32(dev, 0x400);
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- tmp &= ~8;
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- ssb_write32(dev, 0x400, tmp);
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- tmp = ssb_read32(dev, 0x400);
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- printk("USB20H fcr: 0x%0x\n", tmp);
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-
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- /* Change Shim control reg */
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- tmp = ssb_read32(dev, 0x304);
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- tmp &= ~0x100;
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- ssb_write32(dev, 0x304, tmp);
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- tmp = ssb_read32(dev, 0x304);
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- printk("USB20H shim: 0x%0x\n", tmp);
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+ /* Work around for 5354 failures */
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+ if ((dev->id.revision == 2) && (dev->bus->chip_id == 0x5354)) {
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+ /* Change syn01 reg */
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+ tmp = 0x00fe00fe;
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+ ssb_write32(dev, 0x894, tmp);
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+
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+ /* Change syn03 reg */
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+ tmp = ssb_read32(dev, 0x89c);
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+ tmp |= 0x1;
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+ ssb_write32(dev, 0x89c, tmp);
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}
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} else
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ssb_device_enable(dev, 0);
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