mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-18 19:36:15 +02:00
e386996557
- runtime detect the amount of memory available - define EBI_BASE as MPI_BASE to get rid of chip-select specific hacks - fix GPIO control git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27880 3c298f89-4303-0410-b956-a3cf2f4a3e73
123 lines
3.6 KiB
Diff
123 lines
3.6 KiB
Diff
--- a/arch/mips/bcm63xx/cpu.c
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+++ b/arch/mips/bcm63xx/cpu.c
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@@ -260,8 +260,10 @@ static unsigned int detect_memory_size(v
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unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
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u32 val;
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- if (BCMCPU_IS_6345())
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- return (8 * 1024 * 1024);
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+ if (BCMCPU_IS_6345()) {
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+ val = bcm_sdram_readl(SDRAM_MBASE_REG);
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+ return (val * 8 * 1024 * 1024);
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+ }
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if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
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val = bcm_sdram_readl(SDRAM_CFG_REG);
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -735,6 +735,8 @@
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#define SDRAM_CFG_BANK_SHIFT 13
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#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
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+#define SDRAM_MBASE_REG 0xc
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+
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#define SDRAM_PRIO_REG 0x2C
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#define SDRAM_PRIO_MIPS_SHIFT 29
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#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
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--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
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+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
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@@ -698,15 +698,9 @@ void __init board_prom_init(void)
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char cfe_version[32];
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u32 val;
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- /* read base address of boot chip select (0)
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- * 6345 does not have MPI but boots from standard
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- * MIPS Flash address */
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- if (BCMCPU_IS_6345())
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- val = 0x1fc00000;
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- else {
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- val = bcm_mpi_readl(MPI_CSBASE_REG(0));
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- val &= MPI_CSBASE_BASE_MASK;
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- }
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+ /* read base address of boot chip select (0) */
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+ val = bcm_mpi_readl(MPI_CSBASE_REG(0));
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+ val &= MPI_CSBASE_BASE_MASK;
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boot_addr = (u8 *)KSEG1ADDR(val);
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/* dump cfe version */
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@@ -881,12 +875,9 @@ int __init board_register_devices(void)
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bcm63xx_dsp_register(&board.dsp);
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/* read base address of boot chip select (0) */
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- if (BCMCPU_IS_6345())
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- val = 0x1fc00000;
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- else {
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- val = bcm_mpi_readl(MPI_CSBASE_REG(0));
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- val &= MPI_CSBASE_BASE_MASK;
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- }
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+ val = bcm_mpi_readl(MPI_CSBASE_REG(0));
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+ val &= MPI_CSBASE_BASE_MASK;
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+
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mtd_resources[0].start = val;
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mtd_resources[0].end = 0x1FFFFFFF;
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
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@@ -163,7 +163,7 @@ enum bcm63xx_regs_set {
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#define BCM_6345_ENET0_BASE (0xfffe1800)
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#define BCM_6345_ENETDMA_BASE (0xfffe2800)
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#define BCM_6345_PCMCIA_BASE (0xfffe2028)
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-#define BCM_6345_MPI_BASE (0xdeadbeef)
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+#define BCM_6345_MPI_BASE (0xfffe2000)
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#define BCM_6345_OHCI0_BASE (0xfffe2100)
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#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
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#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
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--- a/arch/mips/bcm63xx/gpio.c
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+++ b/arch/mips/bcm63xx/gpio.c
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@@ -4,7 +4,7 @@
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* for more details.
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*
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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- * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
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+ * Copyright (C) 2008-2011 Florian Fainelli <florian@openwrt.org>
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*/
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#include <linux/kernel.h>
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@@ -33,7 +33,10 @@ static void bcm63xx_gpio_set(struct gpio
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BUG();
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if (gpio < 32) {
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- reg = GPIO_DATA_LO_REG;
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+ if (!BCMCPU_IS_6345())
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+ reg = GPIO_DATA_LO_REG;
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+ else
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+ reg = GPIO_DATA_HI_REG;
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mask = 1 << gpio;
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v = &gpio_out_low;
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} else {
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@@ -60,7 +63,10 @@ static int bcm63xx_gpio_get(struct gpio_
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BUG();
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if (gpio < 32) {
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- reg = GPIO_DATA_LO_REG;
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+ if (!BCMCPU_IS_6345())
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+ reg = GPIO_DATA_LO_REG;
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+ else
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+ reg = GPIO_DATA_HI_REG;
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mask = 1 << gpio;
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} else {
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reg = GPIO_DATA_HI_REG;
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@@ -125,7 +131,11 @@ static struct gpio_chip bcm63xx_gpio_chi
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int __init bcm63xx_gpio_init(void)
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{
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- gpio_out_low = bcm_gpio_readl(GPIO_DATA_LO_REG);
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+ if (!BCMCPU_IS_6345())
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+ gpio_out_low = bcm_gpio_readl(GPIO_DATA_LO_REG);
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+ else
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+ gpio_out_low = bcm_gpio_readl(GPIO_DATA_HI_REG);
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+
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gpio_out_high = bcm_gpio_readl(GPIO_DATA_HI_REG);
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bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count();
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pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio);
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