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2cea1e6b9a
openwrt. this gives us the ability to better support different hardware models, without changing any external tar-balls. only et.o and wl.o is missing and is fetched from my webserver. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@379 3c298f89-4303-0410-b956-a3cf2f4a3e73
842 lines
20 KiB
C
842 lines
20 KiB
C
/*
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* Generic Broadcom Home Networking Division (HND) DMA module.
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* This supports the following chips: BCM42xx, 44xx, 47xx .
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*
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* Copyright 2004, Broadcom Corporation
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* All Rights Reserved.
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*
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* THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
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* KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
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* SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
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*
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* $Id$
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*/
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#include <typedefs.h>
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#include <osl.h>
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#include <bcmendian.h>
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#include <bcmutils.h>
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struct dma_info; /* forward declaration */
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#define di_t struct dma_info
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#include <hnddma.h>
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/* debug/trace */
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#define DMA_ERROR(args)
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#define DMA_TRACE(args)
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/* default dma message level(if input msg_level pointer is null in dma_attach()) */
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static uint dma_msg_level = 0;
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#define MAXNAMEL 8
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#define MAXDD (DMAMAXRINGSZ / sizeof (dmadd_t))
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/* dma engine software state */
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typedef struct dma_info {
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hnddma_t hnddma; /* exported structure */
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uint *msg_level; /* message level pointer */
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char name[MAXNAMEL]; /* callers name for diag msgs */
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void *drv; /* driver handle */
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void *dev; /* device handle */
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dmaregs_t *regs; /* dma engine registers */
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dmadd_t *txd; /* pointer to chip-specific tx descriptor ring */
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uint txin; /* index of next descriptor to reclaim */
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uint txout; /* index of next descriptor to post */
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uint txavail; /* # free tx descriptors */
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void *txp[MAXDD]; /* parallel array of pointers to packets */
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ulong txdpa; /* physical address of descriptor ring */
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uint txdalign; /* #bytes added to alloc'd mem to align txd */
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dmadd_t *rxd; /* pointer to chip-specific rx descriptor ring */
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uint rxin; /* index of next descriptor to reclaim */
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uint rxout; /* index of next descriptor to post */
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void *rxp[MAXDD]; /* parallel array of pointers to packets */
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ulong rxdpa; /* physical address of descriptor ring */
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uint rxdalign; /* #bytes added to alloc'd mem to align rxd */
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/* tunables */
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uint ntxd; /* # tx descriptors */
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uint nrxd; /* # rx descriptors */
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uint rxbufsize; /* rx buffer size in bytes */
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uint nrxpost; /* # rx buffers to keep posted */
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uint rxoffset; /* rxcontrol offset */
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uint ddoffset; /* add to get dma address of descriptor ring */
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uint dataoffset; /* add to get dma address of data buffer */
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} dma_info_t;
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/* descriptor bumping macros */
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#define TXD(x) ((x) & (di->ntxd - 1))
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#define RXD(x) ((x) & (di->nrxd - 1))
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#define NEXTTXD(i) TXD(i + 1)
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#define PREVTXD(i) TXD(i - 1)
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#define NEXTRXD(i) RXD(i + 1)
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#define NTXDACTIVE(h, t) TXD(t - h)
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#define NRXDACTIVE(h, t) RXD(t - h)
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/* macros to convert between byte offsets and indexes */
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#define B2I(bytes) ((bytes) / sizeof (dmadd_t))
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#define I2B(index) ((index) * sizeof (dmadd_t))
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void*
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dma_attach(void *drv, void *dev, char *name, dmaregs_t *regs, uint ntxd, uint nrxd,
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uint rxbufsize, uint nrxpost, uint rxoffset, uint ddoffset, uint dataoffset, uint *msg_level)
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{
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dma_info_t *di;
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void *va;
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ASSERT(ntxd <= MAXDD);
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ASSERT(nrxd <= MAXDD);
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/* allocate private info structure */
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if ((di = MALLOC(sizeof (dma_info_t))) == NULL)
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return (NULL);
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bzero((char*)di, sizeof (dma_info_t));
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/* set message level */
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di->msg_level = msg_level ? msg_level : &dma_msg_level;
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DMA_TRACE(("%s: dma_attach: drv 0x%x dev 0x%x regs 0x%x ntxd %d nrxd %d rxbufsize %d nrxpost %d rxoffset %d ddoffset 0x%x dataoffset 0x%x\n", name, (uint)drv, (uint)dev, (uint)regs, ntxd, nrxd, rxbufsize, nrxpost, rxoffset, ddoffset, dataoffset));
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/* make a private copy of our callers name */
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strncpy(di->name, name, MAXNAMEL);
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di->name[MAXNAMEL-1] = '\0';
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di->drv = drv;
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di->dev = dev;
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di->regs = regs;
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/* allocate transmit descriptor ring */
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if (ntxd) {
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if ((va = DMA_ALLOC_CONSISTENT(dev, (DMAMAXRINGSZ + DMARINGALIGN), &di->txdpa)) == NULL)
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goto fail;
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di->txd = (dmadd_t*) ROUNDUP(va, DMARINGALIGN);
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di->txdalign = ((uint)di->txd - (uint)va);
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di->txdpa = di->txdpa + di->txdalign;
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ASSERT(ISALIGNED(di->txd, DMARINGALIGN));
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}
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/* allocate receive descriptor ring */
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if (nrxd) {
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if ((va = DMA_ALLOC_CONSISTENT(dev, (DMAMAXRINGSZ + DMARINGALIGN), &di->rxdpa)) == NULL)
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goto fail;
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di->rxd = (dmadd_t*) ROUNDUP(va, DMARINGALIGN);
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di->rxdalign = ((uint)di->rxd - (uint)va);
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di->rxdpa = di->rxdpa + di->rxdalign;
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ASSERT(ISALIGNED(di->rxd, DMARINGALIGN));
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}
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/* save tunables */
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di->ntxd = ntxd;
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di->nrxd = nrxd;
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di->rxbufsize = rxbufsize;
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di->nrxpost = nrxpost;
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di->rxoffset = rxoffset;
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di->ddoffset = ddoffset;
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di->dataoffset = dataoffset;
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return ((void*)di);
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fail:
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dma_detach((void*)di);
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return (NULL);
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}
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/* may be called with core in reset */
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void
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dma_detach(dma_info_t *di)
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{
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if (di == NULL)
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return;
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DMA_TRACE(("%s: dma_detach\n", di->name));
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/* shouldn't be here if descriptors are unreclaimed */
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ASSERT(di->txin == di->txout);
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ASSERT(di->rxin == di->rxout);
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/* free dma descriptor rings */
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if (di->txd)
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DMA_FREE_CONSISTENT(di->dev, (void *)((uint)di->txd - di->txdalign), (DMAMAXRINGSZ + DMARINGALIGN), di->txdpa);
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if (di->rxd)
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DMA_FREE_CONSISTENT(di->dev, (void *)((uint)di->rxd - di->rxdalign), (DMAMAXRINGSZ + DMARINGALIGN), di->rxdpa);
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/* free our private info structure */
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MFREE((void*)di, sizeof (dma_info_t));
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}
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void
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dma_txreset(dma_info_t *di)
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{
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uint32 status;
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DMA_TRACE(("%s: dma_txreset\n", di->name));
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/* suspend tx DMA first */
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W_REG(&di->regs->xmtcontrol, XC_SE);
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SPINWAIT((status = (R_REG(&di->regs->xmtstatus) & XS_XS_MASK)) != XS_XS_DISABLED &&
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status != XS_XS_IDLE &&
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status != XS_XS_STOPPED,
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10000);
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W_REG(&di->regs->xmtcontrol, 0);
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SPINWAIT((status = (R_REG(&di->regs->xmtstatus) & XS_XS_MASK)) != XS_XS_DISABLED,
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10000);
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if (status != XS_XS_DISABLED) {
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DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
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}
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/* wait for the last transaction to complete */
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OSL_DELAY(300);
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}
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void
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dma_rxreset(dma_info_t *di)
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{
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uint32 status;
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DMA_TRACE(("%s: dma_rxreset\n", di->name));
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W_REG(&di->regs->rcvcontrol, 0);
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SPINWAIT((status = (R_REG(&di->regs->rcvstatus) & RS_RS_MASK)) != RS_RS_DISABLED,
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10000);
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if (status != RS_RS_DISABLED) {
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DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
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}
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}
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void
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dma_txinit(dma_info_t *di)
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{
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DMA_TRACE(("%s: dma_txinit\n", di->name));
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di->txin = di->txout = 0;
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di->txavail = di->ntxd - 1;
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/* clear tx descriptor ring */
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BZERO_SM((void*)di->txd, (di->ntxd * sizeof (dmadd_t)));
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W_REG(&di->regs->xmtcontrol, XC_XE);
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W_REG(&di->regs->xmtaddr, (di->txdpa + di->ddoffset));
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}
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bool
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dma_txenabled(dma_info_t *di)
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{
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uint32 xc;
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/* If the chip is dead, it is not enabled :-) */
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xc = R_REG(&di->regs->xmtcontrol);
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return ((xc != 0xffffffff) && (xc & XC_XE));
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}
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void
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dma_txsuspend(dma_info_t *di)
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{
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DMA_TRACE(("%s: dma_txsuspend\n", di->name));
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OR_REG(&di->regs->xmtcontrol, XC_SE);
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}
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void
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dma_txresume(dma_info_t *di)
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{
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DMA_TRACE(("%s: dma_txresume\n", di->name));
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AND_REG(&di->regs->xmtcontrol, ~XC_SE);
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}
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bool
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dma_txsuspended(dma_info_t *di)
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{
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if (!(R_REG(&di->regs->xmtcontrol) & XC_SE))
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return 0;
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if ((R_REG(&di->regs->xmtstatus) & XS_XS_MASK) != XS_XS_IDLE)
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return 0;
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OSL_DELAY(2);
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return ((R_REG(&di->regs->xmtstatus) & XS_XS_MASK) == XS_XS_IDLE);
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}
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bool
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dma_txstopped(dma_info_t *di)
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{
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return ((R_REG(&di->regs->xmtstatus) & XS_XS_MASK) == XS_XS_STOPPED);
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}
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bool
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dma_rxstopped(dma_info_t *di)
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{
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return ((R_REG(&di->regs->rcvstatus) & RS_RS_MASK) == RS_RS_STOPPED);
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}
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void
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dma_fifoloopbackenable(dma_info_t *di)
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{
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DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
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OR_REG(&di->regs->xmtcontrol, XC_LE);
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}
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void
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dma_rxinit(dma_info_t *di)
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{
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DMA_TRACE(("%s: dma_rxinit\n", di->name));
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di->rxin = di->rxout = 0;
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/* clear rx descriptor ring */
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BZERO_SM((void*)di->rxd, (di->nrxd * sizeof (dmadd_t)));
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dma_rxenable(di);
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W_REG(&di->regs->rcvaddr, (di->rxdpa + di->ddoffset));
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}
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void
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dma_rxenable(dma_info_t *di)
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{
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DMA_TRACE(("%s: dma_rxenable\n", di->name));
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W_REG(&di->regs->rcvcontrol, ((di->rxoffset << RC_RO_SHIFT) | RC_RE));
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}
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bool
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dma_rxenabled(dma_info_t *di)
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{
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uint32 rc;
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rc = R_REG(&di->regs->rcvcontrol);
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return ((rc != 0xffffffff) && (rc & RC_RE));
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}
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/*
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* The BCM47XX family supports full 32bit dma engine buffer addressing so
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* dma buffers can cross 4 Kbyte page boundaries.
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*/
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int
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dma_txfast(dma_info_t *di, void *p0, uint32 coreflags)
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{
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void *p, *next;
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uchar *data;
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uint len;
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uint txout;
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uint32 ctrl;
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uint32 pa;
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DMA_TRACE(("%s: dma_txfast\n", di->name));
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txout = di->txout;
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ctrl = 0;
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/*
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* Walk the chain of packet buffers
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* allocating and initializing transmit descriptor entries.
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*/
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for (p = p0; p; p = next) {
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data = PKTDATA(di->drv, p);
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len = PKTLEN(di->drv, p);
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next = PKTNEXT(di->drv, p);
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/* return nonzero if out of tx descriptors */
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if (NEXTTXD(txout) == di->txin)
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goto outoftxd;
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if (len == 0)
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continue;
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/* get physical address of buffer start */
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pa = (uint32) DMA_MAP(di->dev, data, len, DMA_TX, p);
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/* build the descriptor control value */
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ctrl = len & CTRL_BC_MASK;
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ctrl |= coreflags;
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if (p == p0)
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ctrl |= CTRL_SOF;
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if (next == NULL)
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ctrl |= (CTRL_IOC | CTRL_EOF);
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if (txout == (di->ntxd - 1))
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ctrl |= CTRL_EOT;
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/* init the tx descriptor */
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W_SM(&di->txd[txout].ctrl, BUS_SWAP32(ctrl));
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W_SM(&di->txd[txout].addr, BUS_SWAP32(pa + di->dataoffset));
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ASSERT(di->txp[txout] == NULL);
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txout = NEXTTXD(txout);
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}
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/* if last txd eof not set, fix it */
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if (!(ctrl & CTRL_EOF))
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W_SM(&di->txd[PREVTXD(txout)].ctrl, BUS_SWAP32(ctrl | CTRL_IOC | CTRL_EOF));
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/* save the packet */
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di->txp[PREVTXD(txout)] = p0;
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/* bump the tx descriptor index */
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di->txout = txout;
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/* kick the chip */
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W_REG(&di->regs->xmtptr, I2B(txout));
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/* tx flow control */
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di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
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return (0);
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outoftxd:
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DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
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PKTFREE(di->drv, p0, TRUE);
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di->txavail = 0;
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di->hnddma.txnobuf++;
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return (-1);
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}
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#define PAGESZ 4096
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#define PAGEBASE(x) ((uint)(x) & ~4095)
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/*
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* Just like above except go through the extra effort of splitting
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* buffers that cross 4Kbyte boundaries into multiple tx descriptors.
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*/
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int
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dma_tx(dma_info_t *di, void *p0, uint32 coreflags)
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{
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void *p, *next;
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uchar *data;
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uint plen, len;
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uchar *page, *start, *end;
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uint txout;
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uint32 ctrl;
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uint32 pa;
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DMA_TRACE(("%s: dma_tx\n", di->name));
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txout = di->txout;
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ctrl = 0;
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/*
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* Walk the chain of packet buffers
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* splitting those that cross 4 Kbyte boundaries
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* allocating and initializing transmit descriptor entries.
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*/
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for (p = p0; p; p = next) {
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data = PKTDATA(di->drv, p);
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plen = PKTLEN(di->drv, p);
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next = PKTNEXT(di->drv, p);
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if (plen == 0)
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continue;
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for (page = (uchar*)PAGEBASE(data);
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page <= (uchar*)PAGEBASE(data + plen - 1);
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page += PAGESZ) {
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/* return nonzero if out of tx descriptors */
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if (NEXTTXD(txout) == di->txin)
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goto outoftxd;
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start = (page == (uchar*)PAGEBASE(data))? data: page;
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end = (page == (uchar*)PAGEBASE(data + plen))?
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(data + plen): (page + PAGESZ);
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len = end - start;
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/* build the descriptor control value */
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ctrl = len & CTRL_BC_MASK;
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ctrl |= coreflags;
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if ((p == p0) && (start == data))
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ctrl |= CTRL_SOF;
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if ((next == NULL) && (end == (data + plen)))
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ctrl |= (CTRL_IOC | CTRL_EOF);
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if (txout == (di->ntxd - 1))
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ctrl |= CTRL_EOT;
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/* get physical address of buffer start */
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pa = (uint32) DMA_MAP(di->dev, start, len, DMA_TX, p);
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/* init the tx descriptor */
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W_SM(&di->txd[txout].ctrl, BUS_SWAP32(ctrl));
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W_SM(&di->txd[txout].addr, BUS_SWAP32(pa + di->dataoffset));
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ASSERT(di->txp[txout] == NULL);
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txout = NEXTTXD(txout);
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}
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}
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/* if last txd eof not set, fix it */
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if (!(ctrl & CTRL_EOF))
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W_SM(&di->txd[PREVTXD(txout)].ctrl, BUS_SWAP32(ctrl | CTRL_IOC | CTRL_EOF));
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/* save the packet */
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di->txp[PREVTXD(txout)] = p0;
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/* bump the tx descriptor index */
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di->txout = txout;
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/* kick the chip */
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W_REG(&di->regs->xmtptr, I2B(txout));
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/* tx flow control */
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di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
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return (0);
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outoftxd:
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DMA_ERROR(("%s: dma_tx: out of txds\n", di->name));
|
|
PKTFREE(di->drv, p0, TRUE);
|
|
di->txavail = 0;
|
|
di->hnddma.txnobuf++;
|
|
return (-1);
|
|
}
|
|
|
|
/* returns a pointer to the next frame received, or NULL if there are no more */
|
|
void*
|
|
dma_rx(dma_info_t *di)
|
|
{
|
|
void *p;
|
|
uint len;
|
|
int skiplen = 0;
|
|
|
|
while ((p = dma_getnextrxp(di, FALSE))) {
|
|
/* skip giant packets which span multiple rx descriptors */
|
|
if (skiplen > 0) {
|
|
skiplen -= di->rxbufsize;
|
|
if (skiplen < 0)
|
|
skiplen = 0;
|
|
PKTFREE(di->drv, p, FALSE);
|
|
continue;
|
|
}
|
|
|
|
len = ltoh16(*(uint16*)(PKTDATA(di->drv, p)));
|
|
DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
|
|
|
|
/* bad frame length check */
|
|
if (len > (di->rxbufsize - di->rxoffset)) {
|
|
DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n", di->name, len));
|
|
if (len > 0)
|
|
skiplen = len - (di->rxbufsize - di->rxoffset);
|
|
PKTFREE(di->drv, p, FALSE);
|
|
di->hnddma.rxgiants++;
|
|
continue;
|
|
}
|
|
|
|
/* set actual length */
|
|
PKTSETLEN(di->drv, p, (di->rxoffset + len));
|
|
|
|
break;
|
|
}
|
|
|
|
return (p);
|
|
}
|
|
|
|
/* post receive buffers */
|
|
void
|
|
dma_rxfill(dma_info_t *di)
|
|
{
|
|
void *p;
|
|
uint rxin, rxout;
|
|
uint ctrl;
|
|
uint n;
|
|
uint i;
|
|
uint32 pa;
|
|
uint rxbufsize;
|
|
|
|
/*
|
|
* Determine how many receive buffers we're lacking
|
|
* from the full complement, allocate, initialize,
|
|
* and post them, then update the chip rx lastdscr.
|
|
*/
|
|
|
|
rxin = di->rxin;
|
|
rxout = di->rxout;
|
|
rxbufsize = di->rxbufsize;
|
|
|
|
n = di->nrxpost - NRXDACTIVE(rxin, rxout);
|
|
|
|
DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n));
|
|
|
|
for (i = 0; i < n; i++) {
|
|
if ((p = PKTGET(di->drv, rxbufsize, FALSE)) == NULL) {
|
|
DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n", di->name));
|
|
di->hnddma.rxnobuf++;
|
|
break;
|
|
}
|
|
|
|
*(uint32*)(OSL_UNCACHED(PKTDATA(di->drv, p))) = 0;
|
|
|
|
pa = (uint32) DMA_MAP(di->dev, PKTDATA(di->drv, p), rxbufsize, DMA_RX, p);
|
|
ASSERT(ISALIGNED(pa, 4));
|
|
|
|
/* save the free packet pointer */
|
|
ASSERT(di->rxp[rxout] == NULL);
|
|
di->rxp[rxout] = p;
|
|
|
|
/* prep the descriptor control value */
|
|
ctrl = rxbufsize;
|
|
if (rxout == (di->nrxd - 1))
|
|
ctrl |= CTRL_EOT;
|
|
|
|
/* init the rx descriptor */
|
|
W_SM(&di->rxd[rxout].ctrl, BUS_SWAP32(ctrl));
|
|
W_SM(&di->rxd[rxout].addr, BUS_SWAP32(pa + di->dataoffset));
|
|
|
|
rxout = NEXTRXD(rxout);
|
|
}
|
|
|
|
di->rxout = rxout;
|
|
|
|
/* update the chip lastdscr pointer */
|
|
W_REG(&di->regs->rcvptr, I2B(rxout));
|
|
}
|
|
|
|
void
|
|
dma_txreclaim(dma_info_t *di, bool forceall)
|
|
{
|
|
void *p;
|
|
|
|
DMA_TRACE(("%s: dma_txreclaim %s\n", di->name, forceall ? "all" : ""));
|
|
|
|
while ((p = dma_getnexttxp(di, forceall)))
|
|
PKTFREE(di->drv, p, TRUE);
|
|
}
|
|
|
|
/*
|
|
* Reclaim next completed txd (txds if using chained buffers) and
|
|
* return associated packet.
|
|
* If 'force' is true, reclaim txd(s) and return associated packet
|
|
* regardless of the value of the hardware "curr" pointer.
|
|
*/
|
|
void*
|
|
dma_getnexttxp(dma_info_t *di, bool forceall)
|
|
{
|
|
uint start, end, i;
|
|
void *txp;
|
|
|
|
DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
|
|
|
|
txp = NULL;
|
|
|
|
start = di->txin;
|
|
if (forceall)
|
|
end = di->txout;
|
|
else
|
|
end = B2I(R_REG(&di->regs->xmtstatus) & XS_CD_MASK);
|
|
|
|
if ((start == 0) && (end > di->txout))
|
|
goto bogus;
|
|
|
|
for (i = start; i != end && !txp; i = NEXTTXD(i)) {
|
|
DMA_UNMAP(di->dev, (BUS_SWAP32(R_SM(&di->txd[i].addr)) - di->dataoffset),
|
|
(BUS_SWAP32(R_SM(&di->txd[i].ctrl)) & CTRL_BC_MASK), DMA_TX, di->txp[i]);
|
|
W_SM(&di->txd[i].addr, 0xdeadbeef);
|
|
txp = di->txp[i];
|
|
di->txp[i] = NULL;
|
|
}
|
|
|
|
di->txin = i;
|
|
|
|
/* tx flow control */
|
|
di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
|
|
|
|
return (txp);
|
|
|
|
bogus:
|
|
/*
|
|
DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
|
|
start, end, di->txout, forceall));
|
|
*/
|
|
return (NULL);
|
|
}
|
|
|
|
/* like getnexttxp but no reclaim */
|
|
void*
|
|
dma_peeknexttxp(dma_info_t *di)
|
|
{
|
|
uint end, i;
|
|
|
|
end = B2I(R_REG(&di->regs->xmtstatus) & XS_CD_MASK);
|
|
|
|
for (i = di->txin; i != end; i = NEXTTXD(i))
|
|
if (di->txp[i])
|
|
return (di->txp[i]);
|
|
|
|
return (NULL);
|
|
}
|
|
|
|
void
|
|
dma_rxreclaim(dma_info_t *di)
|
|
{
|
|
void *p;
|
|
|
|
DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
|
|
|
|
while ((p = dma_getnextrxp(di, TRUE)))
|
|
PKTFREE(di->drv, p, FALSE);
|
|
}
|
|
|
|
void *
|
|
dma_getnextrxp(dma_info_t *di, bool forceall)
|
|
{
|
|
uint i;
|
|
void *rxp;
|
|
|
|
/* if forcing, dma engine must be disabled */
|
|
ASSERT(!forceall || !dma_rxenabled(di));
|
|
|
|
i = di->rxin;
|
|
|
|
/* return if no packets posted */
|
|
if (i == di->rxout)
|
|
return (NULL);
|
|
|
|
/* ignore curr if forceall */
|
|
if (!forceall && (i == B2I(R_REG(&di->regs->rcvstatus) & RS_CD_MASK)))
|
|
return (NULL);
|
|
|
|
/* get the packet pointer that corresponds to the rx descriptor */
|
|
rxp = di->rxp[i];
|
|
ASSERT(rxp);
|
|
di->rxp[i] = NULL;
|
|
|
|
/* clear this packet from the descriptor ring */
|
|
DMA_UNMAP(di->dev, (BUS_SWAP32(R_SM(&di->rxd[i].addr)) - di->dataoffset),
|
|
di->rxbufsize, DMA_RX, rxp);
|
|
W_SM(&di->rxd[i].addr, 0xdeadbeef);
|
|
|
|
di->rxin = NEXTRXD(i);
|
|
|
|
return (rxp);
|
|
}
|
|
|
|
char*
|
|
dma_dumptx(dma_info_t *di, char *buf)
|
|
{
|
|
buf += sprintf(buf, "txd 0x%lx txdpa 0x%lx txp 0x%lx txin %d txout %d txavail %d\n",
|
|
(ulong)di->txd, di->txdpa, (ulong)di->txp, di->txin, di->txout, di->txavail);
|
|
buf += sprintf(buf, "xmtcontrol 0x%x xmtaddr 0x%x xmtptr 0x%x xmtstatus 0x%x\n",
|
|
R_REG(&di->regs->xmtcontrol),
|
|
R_REG(&di->regs->xmtaddr),
|
|
R_REG(&di->regs->xmtptr),
|
|
R_REG(&di->regs->xmtstatus));
|
|
return (buf);
|
|
}
|
|
|
|
char*
|
|
dma_dumprx(dma_info_t *di, char *buf)
|
|
{
|
|
buf += sprintf(buf, "rxd 0x%lx rxdpa 0x%lx rxp 0x%lx rxin %d rxout %d\n",
|
|
(ulong)di->rxd, di->rxdpa, (ulong)di->rxp, di->rxin, di->rxout);
|
|
buf += sprintf(buf, "rcvcontrol 0x%x rcvaddr 0x%x rcvptr 0x%x rcvstatus 0x%x\n",
|
|
R_REG(&di->regs->rcvcontrol),
|
|
R_REG(&di->regs->rcvaddr),
|
|
R_REG(&di->regs->rcvptr),
|
|
R_REG(&di->regs->rcvstatus));
|
|
return (buf);
|
|
}
|
|
|
|
char*
|
|
dma_dump(dma_info_t *di, char *buf)
|
|
{
|
|
buf = dma_dumptx(di, buf);
|
|
buf = dma_dumprx(di, buf);
|
|
return (buf);
|
|
}
|
|
|
|
uint
|
|
dma_getvar(dma_info_t *di, char *name)
|
|
{
|
|
if (!strcmp(name, "&txavail"))
|
|
return ((uint) &di->txavail);
|
|
else {
|
|
ASSERT(0);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
void
|
|
dma_txblock(dma_info_t *di)
|
|
{
|
|
di->txavail = 0;
|
|
}
|
|
|
|
void
|
|
dma_txunblock(dma_info_t *di)
|
|
{
|
|
di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
|
|
}
|
|
|
|
uint
|
|
dma_txactive(dma_info_t *di)
|
|
{
|
|
return (NTXDACTIVE(di->txin, di->txout));
|
|
}
|
|
|
|
/*
|
|
* Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
|
|
*/
|
|
void
|
|
dma_txrotate(di_t *di)
|
|
{
|
|
uint ad;
|
|
uint nactive;
|
|
uint rot;
|
|
uint old, new;
|
|
uint32 w;
|
|
uint first, last;
|
|
|
|
ASSERT(dma_txsuspended(di));
|
|
|
|
nactive = dma_txactive(di);
|
|
ad = B2I((R_REG(&di->regs->xmtstatus) & XS_AD_MASK) >> XS_AD_SHIFT);
|
|
rot = TXD(ad - di->txin);
|
|
|
|
ASSERT(rot < di->ntxd);
|
|
|
|
/* full-ring case is a lot harder - don't worry about this */
|
|
if (rot >= (di->ntxd - nactive)) {
|
|
DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
|
|
return;
|
|
}
|
|
|
|
first = di->txin;
|
|
last = PREVTXD(di->txout);
|
|
|
|
/* move entries starting at last and moving backwards to first */
|
|
for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
|
|
new = TXD(old + rot);
|
|
|
|
/*
|
|
* Move the tx dma descriptor.
|
|
* EOT is set only in the last entry in the ring.
|
|
*/
|
|
w = R_SM(&di->txd[old].ctrl) & ~CTRL_EOT;
|
|
if (new == (di->ntxd - 1))
|
|
w |= CTRL_EOT;
|
|
W_SM(&di->txd[new].ctrl, w);
|
|
W_SM(&di->txd[new].addr, R_SM(&di->txd[old].addr));
|
|
|
|
/* zap the old tx dma descriptor address field */
|
|
W_SM(&di->txd[old].addr, 0xdeadbeef);
|
|
|
|
/* move the corresponding txp[] entry */
|
|
ASSERT(di->txp[new] == NULL);
|
|
di->txp[new] = di->txp[old];
|
|
di->txp[old] = NULL;
|
|
}
|
|
|
|
/* update txin and txout */
|
|
di->txin = ad;
|
|
di->txout = TXD(di->txout + rot);
|
|
di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
|
|
|
|
/* kick the chip */
|
|
W_REG(&di->regs->xmtptr, I2B(di->txout));
|
|
}
|