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git://projects.qi-hardware.com/openwrt-xburst.git
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35f8e31243
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31878 3c298f89-4303-0410-b956-a3cf2f4a3e73
241 lines
6.2 KiB
Diff
241 lines
6.2 KiB
Diff
From e170282d7d12f4a26f10d4b666b158d24810d2f6 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Sun, 3 Jul 2011 03:41:02 +0200
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Subject: [PATCH 47/79] MIPS: BCM63XX: Add PCIe Support for BCM6328
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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---
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arch/mips/pci/ops-bcm63xx.c | 61 +++++++++++++++++++++++
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arch/mips/pci/pci-bcm63xx.c | 112 +++++++++++++++++++++++++++++++++++++++++++
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arch/mips/pci/pci-bcm63xx.h | 5 ++
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3 files changed, 178 insertions(+)
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--- a/arch/mips/pci/ops-bcm63xx.c
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+++ b/arch/mips/pci/ops-bcm63xx.c
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@@ -465,3 +465,64 @@ static void bcm63xx_fixup(struct pci_dev
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DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup);
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#endif
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+
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+static int bcm63xx_pcie_can_access(struct pci_bus *bus, int devfn)
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+{
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+ switch (bus->number) {
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+ case PCIE_BUS_BRIDGE:
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+ return (PCI_SLOT(devfn) == 0);
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+ case PCIE_BUS_DEVICE:
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+ if (PCI_SLOT(devfn) == 0)
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+ return bcm_pcie_readl(PCIE_DLSTATUS_REG)
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+ & DLSTATUS_PHYLINKUP;
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+ default:
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+ return false;
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+ }
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+}
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+
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+static int bcm63xx_pcie_read(struct pci_bus *bus, unsigned int devfn,
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+ int where, int size, u32 *val)
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+{
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+ u32 data;
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+ u32 reg = where & ~3;
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+
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+ if (!bcm63xx_pcie_can_access(bus, devfn))
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ if (bus->number == PCIE_BUS_DEVICE)
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+ reg += PCIE_DEVICE_OFFSET;
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+
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+ data = bcm_pcie_readl(reg);
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+
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+ *val = postprocess_read(data, where, size);
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+
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+ return PCIBIOS_SUCCESSFUL;
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+
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+}
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+
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+static int bcm63xx_pcie_write(struct pci_bus *bus, unsigned int devfn,
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+ int where, int size, u32 val)
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+{
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+ u32 data;
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+ u32 reg = where & ~3;
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+
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+ if (!bcm63xx_pcie_can_access(bus, devfn))
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+ return PCIBIOS_DEVICE_NOT_FOUND;
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+
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+ if (bus->number == PCIE_BUS_DEVICE)
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+ reg += PCIE_DEVICE_OFFSET;
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+
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+
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+ data = bcm_pcie_readl(reg);
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+
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+ data = preprocess_write(data, val, where, size);
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+ bcm_pcie_writel(data, reg);
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+
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+ return PCIBIOS_SUCCESSFUL;
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+}
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+
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+
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+struct pci_ops bcm63xx_pcie_ops = {
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+ .read = bcm63xx_pcie_read,
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+ .write = bcm63xx_pcie_write
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+};
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--- a/arch/mips/pci/pci-bcm63xx.c
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+++ b/arch/mips/pci/pci-bcm63xx.c
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@@ -10,6 +10,7 @@
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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+#include <linux/delay.h>
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#include <asm/bootinfo.h>
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#include "pci-bcm63xx.h"
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@@ -65,6 +66,26 @@ struct pci_controller bcm63xx_cb_control
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};
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#endif
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+static struct resource bcm_pcie_mem_resource = {
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+ .name = "bcm63xx PCIe memory space",
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+ .start = BCM_PCIE_MEM_BASE_PA,
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+ .end = BCM_PCIE_MEM_END_PA,
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+ .flags = IORESOURCE_MEM,
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+};
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+
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+static struct resource bcm_pcie_io_resource = {
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+ .name = "bcm63xx PCIe IO space",
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+ .start = 0,
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+ .end = 0,
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+ .flags = 0,
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+};
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+
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+struct pci_controller bcm63xx_pcie_controller = {
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+ .pci_ops = &bcm63xx_pcie_ops,
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+ .io_resource = &bcm_pcie_io_resource,
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+ .mem_resource = &bcm_pcie_mem_resource,
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+};
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+
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static u32 bcm63xx_int_cfg_readl(u32 reg)
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{
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u32 tmp;
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@@ -88,6 +109,95 @@ static void bcm63xx_int_cfg_writel(u32 v
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void __iomem *pci_iospace_start;
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+static void __init bcm63xx_reset_pcie(void)
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+{
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+ u32 val;
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+
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+ /* enable clock */
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+ val = bcm_perf_readl(PERF_CKCTL_REG);
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+ val |= CKCTL_6328_PCIE_EN;
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+ bcm_perf_writel(val, PERF_CKCTL_REG);
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+
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+ /* enable SERDES */
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+ val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
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+ val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
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+ bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
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+
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+ /* reset the PCIe core */
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+ val = bcm_perf_readl(PERF_SOFTRESET_6328_REG);
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+
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+ val &= ~SOFTRESET_6328_PCIE_MASK;
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+ val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
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+ val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
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+ val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
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+ bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
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+ mdelay(10);
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+
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+ val |= SOFTRESET_6328_PCIE_MASK;
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+ val |= SOFTRESET_6328_PCIE_CORE_MASK;
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+ val |= SOFTRESET_6328_PCIE_HARD_MASK;
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+ bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
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+ mdelay(10);
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+
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+ val |= SOFTRESET_6328_PCIE_EXT_MASK;
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+ bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
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+ mdelay(200);
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+}
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+
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+static int __init bcm63xx_register_pcie(void)
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+{
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+ u32 val;
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+
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+ bcm63xx_reset_pcie();
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+
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+ /* configure the PCIe bridge */
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+ val = bcm_pcie_readl(PCIE_BRIDGE_OPT1_REG);
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+ val |= OPT1_RD_BE_OPT_EN;
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+ val |= OPT1_RD_REPLY_BE_FIX_EN;
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+ val |= OPT1_PCIE_BRIDGE_HOLE_DET_EN;
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+ val |= OPT1_L1_INT_STATUS_MASK_POL;
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+ bcm_pcie_writel(val, PCIE_BRIDGE_OPT1_REG);
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+
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+ /* setup the interrupts */
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+ val = bcm_pcie_readl(PCIE_BRIDGE_RC_INT_MASK_REG);
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+ val |= PCIE_RC_INT_A | PCIE_RC_INT_B | PCIE_RC_INT_C | PCIE_RC_INT_D;
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+ bcm_pcie_writel(val, PCIE_BRIDGE_RC_INT_MASK_REG);
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+
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+ val = bcm_pcie_readl(PCIE_BRIDGE_OPT2_REG);
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+ /* enable credit checking and error checking */
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+ val |= OPT2_TX_CREDIT_CHK_EN;
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+ val |= OPT2_UBUS_UR_DECODE_DIS;
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+
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+ /* set device bus/func for the pcie device */
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+ val |= (PCIE_BUS_DEVICE << OPT2_CFG_TYPE1_BUS_NO_SHIFT);
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+ val |= OPT2_CFG_TYPE1_BD_SEL;
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+ bcm_pcie_writel(val, PCIE_BRIDGE_OPT2_REG);
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+
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+ /* setup class code as bridge */
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+ val = bcm_pcie_readl(PCIE_IDVAL3_REG);
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+ val &= ~IDVAL3_CLASS_CODE_MASK;
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+ val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
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+ bcm_pcie_writel(val, PCIE_IDVAL3_REG);
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+
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+ /* disable bar1 size */
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+ val = bcm_pcie_readl(PCIE_CONFIG2_REG);
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+ val &= ~CONFIG2_BAR1_SIZE_MASK;
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+ bcm_pcie_writel(val, PCIE_CONFIG2_REG);
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+
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+ /* set bar0 to little endian */
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+ val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
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+ val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
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+ val |= BASEMASK_REMAP_EN;
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+ bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
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+
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+ val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
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+ bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
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+
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+ register_pci_controller(&bcm63xx_pcie_controller);
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+
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+ return 0;
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+}
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+
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static int __init bcm63xx_register_pci(void)
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{
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unsigned int mem_size;
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@@ -211,6 +321,8 @@ static int __init bcm63xx_register_pci(v
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int __init bcm63xx_pci_register(void)
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{
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switch (bcm63xx_get_cpu_id()) {
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+ case BCM6328_CPU_ID:
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+ return bcm63xx_register_pcie();
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case BCM6348_CPU_ID:
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case BCM6358_CPU_ID:
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case BCM6368_CPU_ID:
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--- a/arch/mips/pci/pci-bcm63xx.h
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+++ b/arch/mips/pci/pci-bcm63xx.h
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@@ -13,11 +13,16 @@
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*/
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#define CARDBUS_PCI_IDSEL 0x8
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+
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+#define PCIE_BUS_BRIDGE 0
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+#define PCIE_BUS_DEVICE 1
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+
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/*
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* defined in ops-bcm63xx.c
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*/
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extern struct pci_ops bcm63xx_pci_ops;
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extern struct pci_ops bcm63xx_cb_ops;
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+extern struct pci_ops bcm63xx_pcie_ops;
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/*
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* defined in pci-bcm63xx.c
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