mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-12-12 05:39:41 +02:00
dfffaea839
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@28721 3c298f89-4303-0410-b956-a3cf2f4a3e73
646 lines
17 KiB
Diff
646 lines
17 KiB
Diff
From 2bd534c30688bcb3f70f1816fbcff813fc746103 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sat, 27 Aug 2011 18:12:26 +0200
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Subject: [PATCH 13/24] MIPS: lantiq: adds FALC-ON spi driver
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The external bus unit (EBU) found on the FALC-ON SoC has spi emulation that is
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designed for serial flash access.
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Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/lantiq/falcon/devices.c | 12 +-
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arch/mips/lantiq/falcon/devices.h | 4 +
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arch/mips/lantiq/falcon/mach-easy98000.c | 27 ++
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drivers/spi/Kconfig | 4 +
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drivers/spi/Makefile | 1 +
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drivers/spi/spi-falcon.c | 477 ++++++++++++++++++++++++++++++
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6 files changed, 523 insertions(+), 2 deletions(-)
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create mode 100644 drivers/spi/spi-falcon.c
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--- a/arch/mips/lantiq/falcon/devices.c
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+++ b/arch/mips/lantiq/falcon/devices.c
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@@ -129,7 +129,7 @@ falcon_register_gpio_extra(void)
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/* i2c */
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static struct resource falcon_i2c_resources[] = {
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- MEM_RES("i2c", GPON_I2C_BASE,GPON_I2C_END),
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+ MEM_RES("i2c", LTQ_I2C_BASE_ADDR, LTQ_I2C_SIZE),
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IRQ_RES("i2c_lb", FALCON_IRQ_I2C_LBREQ),
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IRQ_RES("i2c_b", FALCON_IRQ_I2C_BREQ),
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IRQ_RES("i2c_err", FALCON_IRQ_I2C_I2C_ERR),
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@@ -140,10 +140,18 @@ void __init falcon_register_i2c(void)
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{
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platform_device_register_simple("i2c-falcon", 0,
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falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources));
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- sys1_hw_activate(ACTS_I2C_ACT);
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+ ltq_sysctl_activate(SYSCTL_SYS1, ACTS_I2C_ACT);
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}
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-void __init falcon_register_crypto(void)
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+/* spi flash */
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+static struct platform_device ltq_spi = {
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+ .name = "falcon_spi",
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+ .num_resources = 0,
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+};
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+
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+void __init
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+falcon_register_spi_flash(struct spi_board_info *data)
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{
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- platform_device_register_simple("ltq_falcon_deu", 0, NULL, 0);
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+ spi_register_board_info(data, 1);
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+ platform_device_register(<q_spi);
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}
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--- a/arch/mips/lantiq/falcon/devices.h
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+++ b/arch/mips/lantiq/falcon/devices.h
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@@ -11,11 +11,15 @@
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#ifndef _FALCON_DEVICES_H__
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#define _FALCON_DEVICES_H__
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+#include <linux/spi/spi.h>
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+#include <linux/spi/flash.h>
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+
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#include "../devices.h"
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extern void falcon_register_nand(void);
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extern void falcon_register_gpio(void);
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extern void falcon_register_gpio_extra(void);
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extern void falcon_register_i2c(void);
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+extern void falcon_register_spi_flash(struct spi_board_info *data);
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#endif
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--- a/arch/mips/lantiq/falcon/mach-easy98000.c
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+++ b/arch/mips/lantiq/falcon/mach-easy98000.c
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@@ -40,6 +40,21 @@ struct physmap_flash_data easy98000_nor_
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.parts = easy98000_nor_partitions,
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};
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+static struct flash_platform_data easy98000_spi_flash_platform_data = {
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+ .name = "sflash",
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+ .parts = easy98000_nor_partitions,
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+ .nr_parts = ARRAY_SIZE(easy98000_nor_partitions)
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+};
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+
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+static struct spi_board_info easy98000_spi_flash_data __initdata = {
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+ .modalias = "m25p80",
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+ .bus_num = 0,
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+ .chip_select = 0,
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+ .max_speed_hz = 10 * 1000 * 1000,
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+ .mode = SPI_MODE_3,
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+ .platform_data = &easy98000_spi_flash_platform_data
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+};
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+
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/* setup gpio based spi bus/device for access to the eeprom on the board */
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#define SPI_GPIO_MRST 102
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#define SPI_GPIO_MTSR 103
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@@ -93,6 +108,13 @@ easy98000_init(void)
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}
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static void __init
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+easy98000sf_init(void)
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+{
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+ easy98000_init_common();
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+ falcon_register_spi_flash(&easy98000_spi_flash_data);
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+}
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+
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+static void __init
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easy98000nand_init(void)
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{
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easy98000_init_common();
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@@ -104,6 +126,11 @@ MIPS_MACHINE(LANTIQ_MACH_EASY98000,
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"EASY98000 Eval Board",
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easy98000_init);
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+MIPS_MACHINE(LANTIQ_MACH_EASY98000SF,
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+ "EASY98000SF",
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+ "EASY98000 Eval Board (Serial Flash)",
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+ easy98000sf_init);
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+
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MIPS_MACHINE(LANTIQ_MACH_EASY98000NAND,
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"EASY98000NAND",
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"EASY98000 Eval Board (NAND Flash)",
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--- a/drivers/spi/Kconfig
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+++ b/drivers/spi/Kconfig
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@@ -189,6 +189,10 @@ config SPI_MPC52xx
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This drivers supports the MPC52xx SPI controller in master SPI
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mode.
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+config SPI_FALCON
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+ tristate "Falcon SPI controller support"
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+ depends on SOC_FALCON
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+
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config SPI_MPC52xx_PSC
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tristate "Freescale MPC52xx PSC SPI controller"
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depends on PPC_MPC52xx && EXPERIMENTAL
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--- a/drivers/spi/Makefile
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+++ b/drivers/spi/Makefile
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@@ -25,6 +25,7 @@ obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmi
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obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o
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spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o
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obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o
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+obj-$(CONFIG_SPI_FALCON) += spi-falcon.o
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obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o
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obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o
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obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o
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--- /dev/null
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+++ b/drivers/spi/spi-falcon.c
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@@ -0,0 +1,477 @@
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+/*
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License version 2 as published
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+ * by the Free Software Foundation.
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+ *
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+ * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/device.h>
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+#include <linux/platform_device.h>
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+#include <linux/spi/spi.h>
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+#include <linux/delay.h>
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+#include <linux/workqueue.h>
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+
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+#include <lantiq_soc.h>
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+
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+#define DRV_NAME "falcon_spi"
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+
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+#define FALCON_SPI_XFER_BEGIN (1 << 0)
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+#define FALCON_SPI_XFER_END (1 << 1)
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+
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+/* Bus Read Configuration Register0 */
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+#define LTQ_BUSRCON0 0x00000010
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+/* Bus Write Configuration Register0 */
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+#define LTQ_BUSWCON0 0x00000018
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+/* Serial Flash Configuration Register */
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+#define LTQ_SFCON 0x00000080
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+/* Serial Flash Time Register */
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+#define LTQ_SFTIME 0x00000084
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+/* Serial Flash Status Register */
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+#define LTQ_SFSTAT 0x00000088
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+/* Serial Flash Command Register */
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+#define LTQ_SFCMD 0x0000008C
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+/* Serial Flash Address Register */
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+#define LTQ_SFADDR 0x00000090
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+/* Serial Flash Data Register */
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+#define LTQ_SFDATA 0x00000094
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+/* Serial Flash I/O Control Register */
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+#define LTQ_SFIO 0x00000098
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+/* EBU Clock Control Register */
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+#define LTQ_EBUCC 0x000000C4
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+
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+/* Dummy Phase Length */
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+#define SFCMD_DUMLEN_OFFSET 16
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+#define SFCMD_DUMLEN_MASK 0x000F0000
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+/* Chip Select */
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+#define SFCMD_CS_OFFSET 24
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+#define SFCMD_CS_MASK 0x07000000
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+/* field offset */
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+#define SFCMD_ALEN_OFFSET 20
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+#define SFCMD_ALEN_MASK 0x00700000
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+/* SCK Rise-edge Position */
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+#define SFTIME_SCKR_POS_OFFSET 8
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+#define SFTIME_SCKR_POS_MASK 0x00000F00
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+/* SCK Period */
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+#define SFTIME_SCK_PER_OFFSET 0
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+#define SFTIME_SCK_PER_MASK 0x0000000F
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+/* SCK Fall-edge Position */
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+#define SFTIME_SCKF_POS_OFFSET 12
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+#define SFTIME_SCKF_POS_MASK 0x0000F000
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+/* Device Size */
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+#define SFCON_DEV_SIZE_A23_0 0x03000000
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+#define SFCON_DEV_SIZE_MASK 0x0F000000
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+/* Read Data Position */
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+#define SFTIME_RD_POS_MASK 0x000F0000
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+/* Data Output */
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+#define SFIO_UNUSED_WD_MASK 0x0000000F
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+/* Command Opcode mask */
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+#define SFCMD_OPC_MASK 0x000000FF
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+/* dlen bytes of data to write */
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+#define SFCMD_DIR_WRITE 0x00000100
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+/* Data Length offset */
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+#define SFCMD_DLEN_OFFSET 9
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+/* Command Error */
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+#define SFSTAT_CMD_ERR 0x20000000
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+/* Access Command Pending */
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+#define SFSTAT_CMD_PEND 0x00400000
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+/* Frequency set to 100MHz. */
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+#define EBUCC_EBUDIV_SELF100 0x00000001
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+/* Serial Flash */
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+#define BUSRCON0_AGEN_SERIAL_FLASH 0xF0000000
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+/* 8-bit multiplexed */
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+#define BUSRCON0_PORTW_8_BIT_MUX 0x00000000
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+/* Serial Flash */
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+#define BUSWCON0_AGEN_SERIAL_FLASH 0xF0000000
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+/* Chip Select after opcode */
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+#define SFCMD_KEEP_CS_KEEP_SELECTED 0x00008000
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+
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+struct falcon_spi {
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+ u32 sfcmd; /* for caching of opcode, direction, ... */
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+ struct spi_master *master;
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+};
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+
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+int
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+falcon_spi_xfer(struct spi_device *spi,
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+ struct spi_transfer *t,
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+ unsigned long flags)
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+{
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+ struct device *dev = &spi->dev;
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+ struct falcon_spi *priv = spi_master_get_devdata(spi->master);
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+ const u8 *txp = t->tx_buf;
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+ u8 *rxp = t->rx_buf;
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+ unsigned int bytelen = ((8 * t->len + 7) / 8);
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+ unsigned int len, alen, dumlen;
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+ u32 val;
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+ enum {
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+ state_init,
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+ state_command_prepare,
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+ state_write,
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+ state_read,
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+ state_disable_cs,
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+ state_end
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+ } state = state_init;
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+
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+ do {
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+ switch (state) {
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+ case state_init: /* detect phase of upper layer sequence */
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+ {
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+ /* initial write ? */
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+ if (flags & FALCON_SPI_XFER_BEGIN) {
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+ if (!txp) {
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+ dev_err(dev,
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+ "BEGIN without tx data!\n");
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+ return -1;
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+ }
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+ /*
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+ * Prepare the parts of the sfcmd register,
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+ * which should not
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+ * change during a sequence!
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+ * Only exception are the length fields,
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+ * especially alen and dumlen.
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+ */
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+
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+ priv->sfcmd = ((spi->chip_select
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+ << SFCMD_CS_OFFSET)
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+ & SFCMD_CS_MASK);
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+ priv->sfcmd |= SFCMD_KEEP_CS_KEEP_SELECTED;
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+ priv->sfcmd |= *txp;
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+ txp++;
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+ bytelen--;
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+ if (bytelen) {
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+ /* more data:
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+ * maybe address and/or dummy */
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+ state = state_command_prepare;
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+ break;
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+ } else {
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+ dev_dbg(dev, "write cmd %02X\n",
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+ priv->sfcmd & SFCMD_OPC_MASK);
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+ }
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+ }
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+ /* continued write ? */
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+ if (txp && bytelen) {
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+ state = state_write;
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+ break;
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+ }
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+ /* read data? */
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+ if (rxp && bytelen) {
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+ state = state_read;
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+ break;
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+ }
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+ /* end of sequence? */
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+ if (flags & FALCON_SPI_XFER_END)
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+ state = state_disable_cs;
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+ else
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+ state = state_end;
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+ break;
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+ }
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+ case state_command_prepare: /* collect tx data for
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+ address and dummy phase */
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+ {
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+ /* txp is valid, already checked */
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+ val = 0;
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+ alen = 0;
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+ dumlen = 0;
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+ while (bytelen > 0) {
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+ if (alen < 3) {
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+ val = (val<<8)|(*txp++);
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+ alen++;
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+ } else if ((dumlen < 15) && (*txp == 0)) {
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+ /*
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+ * assume dummy bytes are set to 0
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+ * from upper layer
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+ */
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+ dumlen++;
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+ txp++;
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+ } else
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+ break;
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+ bytelen--;
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+ }
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+ priv->sfcmd &= ~(SFCMD_ALEN_MASK | SFCMD_DUMLEN_MASK);
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+ priv->sfcmd |= (alen << SFCMD_ALEN_OFFSET) |
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+ (dumlen << SFCMD_DUMLEN_OFFSET);
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+ if (alen > 0)
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+ ltq_ebu_w32(val, LTQ_SFADDR);
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+
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+ dev_dbg(dev, "write cmd %02X, alen=%d "
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+ "(addr=%06X) dumlen=%d\n",
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+ priv->sfcmd & SFCMD_OPC_MASK,
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+ alen, val, dumlen);
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+
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+ if (bytelen > 0) {
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+ /* continue with write */
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+ state = state_write;
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+ } else if (flags & FALCON_SPI_XFER_END) {
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+ /* end of sequence? */
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+ state = state_disable_cs;
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+ } else {
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+ /* go to end and expect another
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+ * call (read or write) */
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+ state = state_end;
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+ }
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+ break;
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+ }
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+ case state_write:
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+ {
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+ /* txp still valid */
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+ priv->sfcmd |= SFCMD_DIR_WRITE;
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+ len = 0;
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+ val = 0;
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+ do {
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+ if (bytelen--)
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+ val |= (*txp++) << (8 * len++);
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+ if ((flags & FALCON_SPI_XFER_END)
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+ && (bytelen == 0)) {
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+ priv->sfcmd &=
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+ ~SFCMD_KEEP_CS_KEEP_SELECTED;
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+ }
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+ if ((len == 4) || (bytelen == 0)) {
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+ ltq_ebu_w32(val, LTQ_SFDATA);
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+ ltq_ebu_w32(priv->sfcmd
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+ | (len<<SFCMD_DLEN_OFFSET),
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+ LTQ_SFCMD);
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+ len = 0;
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+ val = 0;
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+ priv->sfcmd &= ~(SFCMD_ALEN_MASK
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+ | SFCMD_DUMLEN_MASK);
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+ }
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+ } while (bytelen);
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+ state = state_end;
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+ break;
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+ }
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+ case state_read:
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+ {
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+ /* read data */
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+ priv->sfcmd &= ~SFCMD_DIR_WRITE;
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+ do {
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+ if ((flags & FALCON_SPI_XFER_END)
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+ && (bytelen <= 4)) {
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+ priv->sfcmd &=
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+ ~SFCMD_KEEP_CS_KEEP_SELECTED;
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+ }
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+ len = (bytelen > 4) ? 4 : bytelen;
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+ bytelen -= len;
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+ ltq_ebu_w32(priv->sfcmd
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+ |(len<<SFCMD_DLEN_OFFSET), LTQ_SFCMD);
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+ priv->sfcmd &= ~(SFCMD_ALEN_MASK
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+ | SFCMD_DUMLEN_MASK);
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+ do {
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+ val = ltq_ebu_r32(LTQ_SFSTAT);
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+ if (val & SFSTAT_CMD_ERR) {
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+ /* reset error status */
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+ dev_err(dev, "SFSTAT: CMD_ERR "
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+ "(%x)\n", val);
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+ ltq_ebu_w32(SFSTAT_CMD_ERR,
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+ LTQ_SFSTAT);
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+ return -1;
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+ }
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+ } while (val & SFSTAT_CMD_PEND);
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+ val = ltq_ebu_r32(LTQ_SFDATA);
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+ do {
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+ *rxp = (val & 0xFF);
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+ rxp++;
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+ val >>= 8;
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+ len--;
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+ } while (len);
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+ } while (bytelen);
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+ state = state_end;
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+ break;
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+ }
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+ case state_disable_cs:
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+ {
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+ priv->sfcmd &= ~SFCMD_KEEP_CS_KEEP_SELECTED;
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+ ltq_ebu_w32(priv->sfcmd | (0 << SFCMD_DLEN_OFFSET),
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+ LTQ_SFCMD);
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+ val = ltq_ebu_r32(LTQ_SFSTAT);
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+ if (val & SFSTAT_CMD_ERR) {
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+ /* reset error status */
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+ dev_err(dev, "SFSTAT: CMD_ERR (%x)\n", val);
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+ ltq_ebu_w32(SFSTAT_CMD_ERR, LTQ_SFSTAT);
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+ return -1;
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+ }
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+ state = state_end;
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+ break;
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+ }
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+ case state_end:
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+ break;
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+ }
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+ } while (state != state_end);
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+
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+ return 0;
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+}
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+
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+static int
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+falcon_spi_setup(struct spi_device *spi)
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+{
|
|
+ struct device *dev = &spi->dev;
|
|
+ const u32 ebuclk = CLOCK_100M;
|
|
+ unsigned int i;
|
|
+ unsigned long flags;
|
|
+
|
|
+ dev_dbg(dev, "setup\n");
|
|
+
|
|
+ if (spi->master->bus_num > 0 || spi->chip_select > 0)
|
|
+ return -ENODEV;
|
|
+
|
|
+ spin_lock_irqsave(&ebu_lock, flags);
|
|
+
|
|
+ if (ebuclk < spi->max_speed_hz) {
|
|
+ /* set EBU clock to 100 MHz */
|
|
+ ltq_sys1_w32_mask(0, EBUCC_EBUDIV_SELF100, LTQ_EBUCC);
|
|
+ i = 1; /* divider */
|
|
+ } else {
|
|
+ /* set EBU clock to 50 MHz */
|
|
+ ltq_sys1_w32_mask(EBUCC_EBUDIV_SELF100, 0, LTQ_EBUCC);
|
|
+
|
|
+ /* search for suitable divider */
|
|
+ for (i = 1; i < 7; i++) {
|
|
+ if (ebuclk / i <= spi->max_speed_hz)
|
|
+ break;
|
|
+ }
|
|
+ }
|
|
+
|
|
+ /* setup period of serial clock */
|
|
+ ltq_ebu_w32_mask(SFTIME_SCKF_POS_MASK
|
|
+ | SFTIME_SCKR_POS_MASK
|
|
+ | SFTIME_SCK_PER_MASK,
|
|
+ (i << SFTIME_SCKR_POS_OFFSET)
|
|
+ | (i << (SFTIME_SCK_PER_OFFSET + 1)),
|
|
+ LTQ_SFTIME);
|
|
+
|
|
+ /* set some bits of unused_wd, to not trigger HOLD/WP
|
|
+ * signals on non QUAD flashes */
|
|
+ ltq_ebu_w32((SFIO_UNUSED_WD_MASK & (0x8 | 0x4)), LTQ_SFIO);
|
|
+
|
|
+ ltq_ebu_w32(BUSRCON0_AGEN_SERIAL_FLASH | BUSRCON0_PORTW_8_BIT_MUX,
|
|
+ LTQ_BUSRCON0);
|
|
+ ltq_ebu_w32(BUSWCON0_AGEN_SERIAL_FLASH, LTQ_BUSWCON0);
|
|
+ /* set address wrap around to maximum for 24-bit addresses */
|
|
+ ltq_ebu_w32_mask(SFCON_DEV_SIZE_MASK, SFCON_DEV_SIZE_A23_0, LTQ_SFCON);
|
|
+
|
|
+ spin_unlock_irqrestore(&ebu_lock, flags);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int
|
|
+falcon_spi_transfer(struct spi_device *spi, struct spi_message *m)
|
|
+{
|
|
+ struct falcon_spi *priv = spi_master_get_devdata(spi->master);
|
|
+ struct spi_transfer *t;
|
|
+ unsigned long spi_flags;
|
|
+ unsigned long flags;
|
|
+ int ret = 0;
|
|
+
|
|
+ priv->sfcmd = 0;
|
|
+ m->actual_length = 0;
|
|
+
|
|
+ spi_flags = FALCON_SPI_XFER_BEGIN;
|
|
+ list_for_each_entry(t, &m->transfers, transfer_list) {
|
|
+ if (list_is_last(&t->transfer_list, &m->transfers))
|
|
+ spi_flags |= FALCON_SPI_XFER_END;
|
|
+
|
|
+ spin_lock_irqsave(&ebu_lock, flags);
|
|
+ ret = falcon_spi_xfer(spi, t, spi_flags);
|
|
+ spin_unlock_irqrestore(&ebu_lock, flags);
|
|
+
|
|
+ if (ret)
|
|
+ break;
|
|
+
|
|
+ m->actual_length += t->len;
|
|
+
|
|
+ if (t->delay_usecs || t->cs_change)
|
|
+ BUG();
|
|
+
|
|
+ spi_flags = 0;
|
|
+ }
|
|
+
|
|
+ m->status = ret;
|
|
+ m->complete(m->context);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static void
|
|
+falcon_spi_cleanup(struct spi_device *spi)
|
|
+{
|
|
+ struct device *dev = &spi->dev;
|
|
+
|
|
+ dev_dbg(dev, "cleanup\n");
|
|
+}
|
|
+
|
|
+static int __devinit
|
|
+falcon_spi_probe(struct platform_device *pdev)
|
|
+{
|
|
+ struct device *dev = &pdev->dev;
|
|
+ struct falcon_spi *priv;
|
|
+ struct spi_master *master;
|
|
+ int ret;
|
|
+
|
|
+ dev_dbg(dev, "probing\n");
|
|
+
|
|
+ master = spi_alloc_master(&pdev->dev, sizeof(*priv));
|
|
+ if (!master) {
|
|
+ dev_err(dev, "no memory for spi_master\n");
|
|
+ return -ENOMEM;
|
|
+ }
|
|
+
|
|
+ priv = spi_master_get_devdata(master);
|
|
+ priv->master = master;
|
|
+
|
|
+ master->mode_bits = SPI_MODE_3;
|
|
+ master->num_chipselect = 1;
|
|
+ master->bus_num = 0;
|
|
+
|
|
+ master->setup = falcon_spi_setup;
|
|
+ master->transfer = falcon_spi_transfer;
|
|
+ master->cleanup = falcon_spi_cleanup;
|
|
+
|
|
+ platform_set_drvdata(pdev, priv);
|
|
+
|
|
+ ret = spi_register_master(master);
|
|
+ if (ret)
|
|
+ spi_master_put(master);
|
|
+
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static int __devexit
|
|
+falcon_spi_remove(struct platform_device *pdev)
|
|
+{
|
|
+ struct device *dev = &pdev->dev;
|
|
+ struct falcon_spi *priv = platform_get_drvdata(pdev);
|
|
+
|
|
+ dev_dbg(dev, "removed\n");
|
|
+
|
|
+ spi_unregister_master(priv->master);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static struct platform_driver falcon_spi_driver = {
|
|
+ .probe = falcon_spi_probe,
|
|
+ .remove = __devexit_p(falcon_spi_remove),
|
|
+ .driver = {
|
|
+ .name = DRV_NAME,
|
|
+ .owner = THIS_MODULE
|
|
+ }
|
|
+};
|
|
+
|
|
+static int __init
|
|
+falcon_spi_init(void)
|
|
+{
|
|
+ return platform_driver_register(&falcon_spi_driver);
|
|
+}
|
|
+
|
|
+static void __exit
|
|
+falcon_spi_exit(void)
|
|
+{
|
|
+ platform_driver_unregister(&falcon_spi_driver);
|
|
+}
|
|
+
|
|
+module_init(falcon_spi_init);
|
|
+module_exit(falcon_spi_exit);
|
|
+
|
|
+MODULE_LICENSE("GPL");
|
|
+MODULE_DESCRIPTION("Lantiq Falcon SPI controller driver");
|
|
--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
|
|
+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
|
|
@@ -48,6 +48,10 @@
|
|
|
|
#define LTQ_EBU_MODCON 0x000C
|
|
|
|
+/* I2C */
|
|
+#define LTQ_I2C_BASE_ADDR 0x1E200000
|
|
+#define LTQ_I2C_SIZE 0x00010000
|
|
+
|
|
/* GPIO */
|
|
#define LTQ_GPIO0_BASE_ADDR 0x1D810000
|
|
#define LTQ_GPIO0_SIZE 0x0080
|
|
@@ -92,6 +96,7 @@
|
|
|
|
/* Activation Status Register */
|
|
#define ACTS_ASC1_ACT 0x00000800
|
|
+#define ACTS_I2C_ACT 0x00004000
|
|
#define ACTS_P0 0x00010000
|
|
#define ACTS_P1 0x00010000
|
|
#define ACTS_P2 0x00020000
|