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4f2c17075b
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@34061 3c298f89-4303-0410-b956-a3cf2f4a3e73
29 lines
1.1 KiB
Diff
29 lines
1.1 KiB
Diff
From 00b0721cce51988b6dda27b21afb0e09c620bc21 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Sat, 27 Oct 2012 09:14:17 +0200
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Subject: [PATCH 107/113] MIPS: lantiq: add xrx200 ethernet clock
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/lantiq/xway/sysctrl.c | 4 ++++
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1 file changed, 4 insertions(+)
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diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
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index 2917b56..3925e66 100644
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--- a/arch/mips/lantiq/xway/sysctrl.c
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+++ b/arch/mips/lantiq/xway/sysctrl.c
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@@ -370,6 +370,10 @@ void __init ltq_soc_init(void)
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clkdev_add_pmu("1d900000.pcie", "pdi", 1, PMU1_PCIE_PDI);
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clkdev_add_pmu("1d900000.pcie", "ctl", 1, PMU1_PCIE_CTL);
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clkdev_add_pmu("1d900000.pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
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+ clkdev_add_pmu("1e108000.eth", NULL, 0,
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+ PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
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+ PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
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+ PMU_PPE_QSB | PMU_PPE_TOP);
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} else if (of_machine_is_compatible("lantiq,ar9")) {
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clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
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ltq_ar9_fpi_hz());
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--
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1.7.10.4
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