mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-12 19:39:18 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/branches/buildroot-ng/openwrt@3987 3c298f89-4303-0410-b956-a3cf2f4a3e73
700 lines
19 KiB
Diff
700 lines
19 KiB
Diff
diff -Nur linux-2.6.17/drivers/net/b44.c linux-2.6.17-owrt/drivers/net/b44.c
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--- linux-2.6.17/drivers/net/b44.c 2006-06-18 03:49:35.000000000 +0200
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+++ linux-2.6.17-owrt/drivers/net/b44.c 2006-06-18 16:24:14.000000000 +0200
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@@ -1,7 +1,9 @@
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-/* b44.c: Broadcom 4400 device driver.
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+/* b44.c: Broadcom 4400/47xx device driver.
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*
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* Copyright (C) 2002 David S. Miller (davem@redhat.com)
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- * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
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+ * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
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+ * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
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+ * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
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* Copyright (C) 2006 Broadcom Corporation.
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*
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* Distribute under GPL.
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@@ -32,6 +34,28 @@
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#define DRV_MODULE_VERSION "1.00"
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#define DRV_MODULE_RELDATE "Apr 7, 2006"
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+#ifdef CONFIG_BCM947XX
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+extern char *nvram_get(char *name);
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+static inline void e_aton(char *str, char *dest)
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+{
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+ int i = 0;
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+
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+ if (str == NULL) {
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+ memset(dest, 0, 6);
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+ return;
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+ }
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+
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+ for (;;) {
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+ dest[i++] = (char) simple_strtoul(str, NULL, 16);
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+ str += 2;
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+ if (!*str++ || i == 6)
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+ break;
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+ }
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+}
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+
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+static int b44_4713_instance;
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+#endif
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+
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#define B44_DEF_MSG_ENABLE \
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(NETIF_MSG_DRV | \
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NETIF_MSG_PROBE | \
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@@ -78,8 +102,8 @@
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static char version[] __devinitdata =
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DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
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-MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
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-MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
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+MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
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+MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver");
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MODULE_LICENSE("GPL");
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MODULE_VERSION(DRV_MODULE_VERSION);
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@@ -94,6 +118,10 @@
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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+#ifdef CONFIG_BCM947XX
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+ { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4713,
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+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
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+#endif
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{ } /* terminate list with empty entry */
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};
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@@ -132,17 +160,6 @@
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dma_desc_sync_size, dir);
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}
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-static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
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-{
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- return readl(bp->regs + reg);
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-}
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-
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-static inline void bw32(const struct b44 *bp,
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- unsigned long reg, unsigned long val)
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-{
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- writel(val, bp->regs + reg);
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-}
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-
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static int b44_wait_bit(struct b44 *bp, unsigned long reg,
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u32 bit, unsigned long timeout, const int clear)
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{
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@@ -269,6 +286,10 @@
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break;
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};
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#endif
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+#ifdef CONFIG_BCM947XX
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+ if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
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+ return b44_4713_instance++;
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+#endif
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return 0;
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}
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@@ -278,6 +299,30 @@
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== SBTMSLOW_CLOCK);
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}
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+#ifdef CONFIG_BCM947XX
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+static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
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+{
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+ u32 val;
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+
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+ bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
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+ (index << CAM_CTRL_INDEX_SHIFT)));
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+
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+ b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
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+
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+ val = br32(bp, B44_CAM_DATA_LO);
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+
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+ data[2] = (val >> 24) & 0xFF;
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+ data[3] = (val >> 16) & 0xFF;
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+ data[4] = (val >> 8) & 0xFF;
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+ data[5] = (val >> 0) & 0xFF;
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+
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+ val = br32(bp, B44_CAM_DATA_HI);
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+
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+ data[0] = (val >> 8) & 0xFF;
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+ data[1] = (val >> 0) & 0xFF;
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+}
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+#endif
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+
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static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
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{
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u32 val;
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@@ -314,14 +359,14 @@
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bw32(bp, B44_IMASK, bp->imask);
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}
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-static int b44_readphy(struct b44 *bp, int reg, u32 *val)
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+static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
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{
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int err;
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bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
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bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
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(MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
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- (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
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+ (phy_addr << MDIO_DATA_PMD_SHIFT) |
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(reg << MDIO_DATA_RA_SHIFT) |
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(MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
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err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
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@@ -330,18 +375,34 @@
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return err;
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}
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-static int b44_writephy(struct b44 *bp, int reg, u32 val)
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+static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
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{
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bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
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bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
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(MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
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- (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
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+ (phy_addr << MDIO_DATA_PMD_SHIFT) |
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(reg << MDIO_DATA_RA_SHIFT) |
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(MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
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(val & MDIO_DATA_DATA)));
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return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
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}
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+static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
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+{
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+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
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+ return 0;
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+
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+ return __b44_readphy(bp, bp->phy_addr, reg, val);
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+}
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+
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+static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
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+{
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+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
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+ return 0;
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+
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+ return __b44_writephy(bp, bp->phy_addr, reg, val);
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+}
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+
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/* miilib interface */
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/* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
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* due to code existing before miilib use was added to this driver.
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@@ -370,6 +431,8 @@
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u32 val;
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int err;
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+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
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+ return 0;
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err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
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if (err)
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return err;
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@@ -433,6 +496,22 @@
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u32 val;
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int err;
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+#ifdef CONFIG_BCM947XX
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+ /*
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+ * workaround for bad hardware design in Linksys WAP54G v1.0
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+ * see https://dev.openwrt.org/ticket/146
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+ * check and reset bit "isolate"
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+ */
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+ if ((bp->pdev->device == PCI_DEVICE_ID_BCM4713) &&
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+ (atoi(nvram_get("boardnum")) == 2) &&
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+ (__b44_readphy(bp, 0, MII_BMCR, &val) == 0) &&
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+ (val & BMCR_ISOLATE) &&
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+ (__b44_writephy(bp, 0, MII_BMCR, val & ~BMCR_ISOLATE) != 0)) {
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+ printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
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+ }
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+#endif
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+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
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+ return 0;
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if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
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goto out;
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if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
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@@ -528,6 +607,19 @@
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{
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u32 bmsr, aux;
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+ if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
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+ bp->flags |= B44_FLAG_100_BASE_T;
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+ bp->flags |= B44_FLAG_FULL_DUPLEX;
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+ if (!netif_carrier_ok(bp->dev)) {
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+ u32 val = br32(bp, B44_TX_CTRL);
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+ val |= TX_CTRL_DUPLEX;
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+ bw32(bp, B44_TX_CTRL, val);
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+ netif_carrier_on(bp->dev);
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+ b44_link_report(bp);
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+ }
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+ return;
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+ }
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+
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if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
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!b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
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(bmsr != 0xffff)) {
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@@ -1282,9 +1374,10 @@
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bw32(bp, B44_DMARX_CTRL, 0);
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bp->rx_prod = bp->rx_cons = 0;
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} else {
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- ssb_pci_setup(bp, (bp->core_unit == 0 ?
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- SBINTVEC_ENET0 :
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- SBINTVEC_ENET1));
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+ if (bp->pdev->device != PCI_DEVICE_ID_BCM4713)
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+ ssb_pci_setup(bp, (bp->core_unit == 0 ?
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+ SBINTVEC_ENET0 :
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+ SBINTVEC_ENET1));
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}
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ssb_core_reset(bp);
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@@ -1292,8 +1385,14 @@
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b44_clear_stats(bp);
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/* Make PHY accessible. */
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- bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
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+ if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
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+ bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
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+ (((100000000 + (B44_MDC_RATIO / 2)) / B44_MDC_RATIO)
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+ & MDIO_CTRL_MAXF_MASK)));
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+ else
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+ bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
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(0x0d & MDIO_CTRL_MAXF_MASK)));
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+
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br32(bp, B44_MDIO_CTRL);
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if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
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@@ -1837,18 +1936,297 @@
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.get_perm_addr = ethtool_op_get_perm_addr,
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};
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+static int b44_ethtool_ioctl (struct net_device *dev, void __user *useraddr)
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+{
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+ struct b44 *bp = dev->priv;
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+ struct pci_dev *pci_dev = bp->pdev;
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+ u32 ethcmd;
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+
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+ if (copy_from_user (ðcmd, useraddr, sizeof (ethcmd)))
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+ return -EFAULT;
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+
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+ switch (ethcmd) {
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+ case ETHTOOL_GDRVINFO: {
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+ struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
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+ strcpy (info.driver, DRV_MODULE_NAME);
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+ strcpy (info.version, DRV_MODULE_VERSION);
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+ memset(&info.fw_version, 0, sizeof(info.fw_version));
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+ strcpy (info.bus_info, pci_name(pci_dev));
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+ info.eedump_len = 0;
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+ info.regdump_len = 0;
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+ if (copy_to_user (useraddr, &info, sizeof (info)))
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+ return -EFAULT;
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+ return 0;
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+ }
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+
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+ case ETHTOOL_GSET: {
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+ struct ethtool_cmd cmd = { ETHTOOL_GSET };
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+
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+ if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
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+ return -EAGAIN;
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+ cmd.supported = (SUPPORTED_Autoneg);
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+ cmd.supported |= (SUPPORTED_100baseT_Half |
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+ SUPPORTED_100baseT_Full |
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+ SUPPORTED_10baseT_Half |
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+ SUPPORTED_10baseT_Full |
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+ SUPPORTED_MII);
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+
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+ cmd.advertising = 0;
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+ if (bp->flags & B44_FLAG_ADV_10HALF)
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+ cmd.advertising |= ADVERTISE_10HALF;
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+ if (bp->flags & B44_FLAG_ADV_10FULL)
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+ cmd.advertising |= ADVERTISE_10FULL;
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+ if (bp->flags & B44_FLAG_ADV_100HALF)
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+ cmd.advertising |= ADVERTISE_100HALF;
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+ if (bp->flags & B44_FLAG_ADV_100FULL)
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+ cmd.advertising |= ADVERTISE_100FULL;
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+ cmd.advertising |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
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+ cmd.speed = (bp->flags & B44_FLAG_100_BASE_T) ?
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+ SPEED_100 : SPEED_10;
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+ cmd.duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
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+ DUPLEX_FULL : DUPLEX_HALF;
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+ cmd.port = 0;
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+ cmd.phy_address = bp->phy_addr;
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+ cmd.transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
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+ XCVR_INTERNAL : XCVR_EXTERNAL;
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+ cmd.autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
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+ AUTONEG_DISABLE : AUTONEG_ENABLE;
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+ cmd.maxtxpkt = 0;
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+ cmd.maxrxpkt = 0;
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+ if (copy_to_user(useraddr, &cmd, sizeof(cmd)))
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+ return -EFAULT;
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+ return 0;
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+ }
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+ case ETHTOOL_SSET: {
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+ struct ethtool_cmd cmd;
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+
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+ if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
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+ return -EAGAIN;
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+
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+ if (copy_from_user(&cmd, useraddr, sizeof(cmd)))
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+ return -EFAULT;
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+
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+ /* We do not support gigabit. */
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+ if (cmd.autoneg == AUTONEG_ENABLE) {
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+ if (cmd.advertising &
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+ (ADVERTISED_1000baseT_Half |
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+ ADVERTISED_1000baseT_Full))
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+ return -EINVAL;
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+ } else if ((cmd.speed != SPEED_100 &&
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+ cmd.speed != SPEED_10) ||
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+ (cmd.duplex != DUPLEX_HALF &&
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+ cmd.duplex != DUPLEX_FULL)) {
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+ return -EINVAL;
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+ }
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+
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+ spin_lock_irq(&bp->lock);
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+
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+ if (cmd.autoneg == AUTONEG_ENABLE) {
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+ bp->flags &= ~B44_FLAG_FORCE_LINK;
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+ bp->flags &= ~(B44_FLAG_ADV_10HALF |
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+ B44_FLAG_ADV_10FULL |
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+ B44_FLAG_ADV_100HALF |
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+ B44_FLAG_ADV_100FULL);
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+ if (cmd.advertising & ADVERTISE_10HALF)
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+ bp->flags |= B44_FLAG_ADV_10HALF;
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+ if (cmd.advertising & ADVERTISE_10FULL)
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+ bp->flags |= B44_FLAG_ADV_10FULL;
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+ if (cmd.advertising & ADVERTISE_100HALF)
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+ bp->flags |= B44_FLAG_ADV_100HALF;
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+ if (cmd.advertising & ADVERTISE_100FULL)
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+ bp->flags |= B44_FLAG_ADV_100FULL;
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+ } else {
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+ bp->flags |= B44_FLAG_FORCE_LINK;
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+ if (cmd.speed == SPEED_100)
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+ bp->flags |= B44_FLAG_100_BASE_T;
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+ if (cmd.duplex == DUPLEX_FULL)
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+ bp->flags |= B44_FLAG_FULL_DUPLEX;
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+ }
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+
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+ b44_setup_phy(bp);
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+
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+ spin_unlock_irq(&bp->lock);
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+
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+ return 0;
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+ }
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+
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+ case ETHTOOL_GMSGLVL: {
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+ struct ethtool_value edata = { ETHTOOL_GMSGLVL };
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+ edata.data = bp->msg_enable;
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+ if (copy_to_user(useraddr, &edata, sizeof(edata)))
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+ return -EFAULT;
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+ return 0;
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+ }
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+ case ETHTOOL_SMSGLVL: {
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+ struct ethtool_value edata;
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+ if (copy_from_user(&edata, useraddr, sizeof(edata)))
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+ return -EFAULT;
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+ bp->msg_enable = edata.data;
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+ return 0;
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+ }
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+ case ETHTOOL_NWAY_RST: {
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+ u32 bmcr;
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+ int r;
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+
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+ spin_lock_irq(&bp->lock);
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+ b44_readphy(bp, MII_BMCR, &bmcr);
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+ b44_readphy(bp, MII_BMCR, &bmcr);
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+ r = -EINVAL;
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+ if (bmcr & BMCR_ANENABLE) {
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+ b44_writephy(bp, MII_BMCR,
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+ bmcr | BMCR_ANRESTART);
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+ r = 0;
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+ }
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+ spin_unlock_irq(&bp->lock);
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+
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+ return r;
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+ }
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+ case ETHTOOL_GLINK: {
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+ struct ethtool_value edata = { ETHTOOL_GLINK };
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+ edata.data = netif_carrier_ok(bp->dev) ? 1 : 0;
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+ if (copy_to_user(useraddr, &edata, sizeof(edata)))
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+ return -EFAULT;
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+ return 0;
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+ }
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+ case ETHTOOL_GRINGPARAM: {
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+ struct ethtool_ringparam ering = { ETHTOOL_GRINGPARAM };
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+
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+ ering.rx_max_pending = B44_RX_RING_SIZE - 1;
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+ ering.rx_pending = bp->rx_pending;
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+
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+ /* XXX ethtool lacks a tx_max_pending, oops... */
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+
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+ if (copy_to_user(useraddr, &ering, sizeof(ering)))
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+ return -EFAULT;
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+ return 0;
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+ }
|
|
+ case ETHTOOL_SRINGPARAM: {
|
|
+ struct ethtool_ringparam ering;
|
|
+
|
|
+ if (copy_from_user(&ering, useraddr, sizeof(ering)))
|
|
+ return -EFAULT;
|
|
+
|
|
+ if ((ering.rx_pending > B44_RX_RING_SIZE - 1) ||
|
|
+ (ering.rx_mini_pending != 0) ||
|
|
+ (ering.rx_jumbo_pending != 0) ||
|
|
+ (ering.tx_pending > B44_TX_RING_SIZE - 1))
|
|
+ return -EINVAL;
|
|
+
|
|
+ spin_lock_irq(&bp->lock);
|
|
+
|
|
+ bp->rx_pending = ering.rx_pending;
|
|
+ bp->tx_pending = ering.tx_pending;
|
|
+
|
|
+ b44_halt(bp);
|
|
+ b44_init_rings(bp);
|
|
+ b44_init_hw(bp);
|
|
+ netif_wake_queue(bp->dev);
|
|
+ spin_unlock_irq(&bp->lock);
|
|
+
|
|
+ b44_enable_ints(bp);
|
|
+
|
|
+ return 0;
|
|
+ }
|
|
+ case ETHTOOL_GPAUSEPARAM: {
|
|
+ struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM };
|
|
+
|
|
+ epause.autoneg =
|
|
+ (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
|
|
+ epause.rx_pause =
|
|
+ (bp->flags & B44_FLAG_RX_PAUSE) != 0;
|
|
+ epause.tx_pause =
|
|
+ (bp->flags & B44_FLAG_TX_PAUSE) != 0;
|
|
+ if (copy_to_user(useraddr, &epause, sizeof(epause)))
|
|
+ return -EFAULT;
|
|
+ return 0;
|
|
+ }
|
|
+ case ETHTOOL_SPAUSEPARAM: {
|
|
+ struct ethtool_pauseparam epause;
|
|
+
|
|
+ if (copy_from_user(&epause, useraddr, sizeof(epause)))
|
|
+ return -EFAULT;
|
|
+
|
|
+ spin_lock_irq(&bp->lock);
|
|
+ if (epause.autoneg)
|
|
+ bp->flags |= B44_FLAG_PAUSE_AUTO;
|
|
+ else
|
|
+ bp->flags &= ~B44_FLAG_PAUSE_AUTO;
|
|
+ if (epause.rx_pause)
|
|
+ bp->flags |= B44_FLAG_RX_PAUSE;
|
|
+ else
|
|
+ bp->flags &= ~B44_FLAG_RX_PAUSE;
|
|
+ if (epause.tx_pause)
|
|
+ bp->flags |= B44_FLAG_TX_PAUSE;
|
|
+ else
|
|
+ bp->flags &= ~B44_FLAG_TX_PAUSE;
|
|
+ if (bp->flags & B44_FLAG_PAUSE_AUTO) {
|
|
+ b44_halt(bp);
|
|
+ b44_init_rings(bp);
|
|
+ b44_init_hw(bp);
|
|
+ } else {
|
|
+ __b44_set_flow_ctrl(bp, bp->flags);
|
|
+ }
|
|
+ spin_unlock_irq(&bp->lock);
|
|
+
|
|
+ b44_enable_ints(bp);
|
|
+
|
|
+ return 0;
|
|
+ }
|
|
+ };
|
|
+
|
|
+ return -EOPNOTSUPP;
|
|
+}
|
|
+
|
|
static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
|
|
{
|
|
struct mii_ioctl_data *data = if_mii(ifr);
|
|
struct b44 *bp = netdev_priv(dev);
|
|
int err = -EINVAL;
|
|
|
|
- if (!netif_running(dev))
|
|
+ if (bp->pdev->device != PCI_DEVICE_ID_BCM4713) {
|
|
+ if (!netif_running(dev))
|
|
+ goto out;
|
|
+
|
|
+ spin_lock_irq(&bp->lock);
|
|
+ err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
|
|
+ spin_unlock_irq(&bp->lock);
|
|
goto out;
|
|
+ }
|
|
|
|
- spin_lock_irq(&bp->lock);
|
|
- err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
|
|
- spin_unlock_irq(&bp->lock);
|
|
+ switch (cmd) {
|
|
+ case SIOCETHTOOL:
|
|
+ return b44_ethtool_ioctl(dev, (void __user*) ifr->ifr_data);
|
|
+
|
|
+ case SIOCGMIIPHY:
|
|
+ data->phy_id = bp->phy_addr;
|
|
+
|
|
+ /* fallthru */
|
|
+ case SIOCGMIIREG: {
|
|
+ u32 mii_regval;
|
|
+ spin_lock_irq(&bp->lock);
|
|
+ err = __b44_readphy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
|
|
+ spin_unlock_irq(&bp->lock);
|
|
+
|
|
+ data->val_out = mii_regval;
|
|
+
|
|
+ return err;
|
|
+ }
|
|
+
|
|
+ case SIOCSMIIREG:
|
|
+ if (!capable(CAP_NET_ADMIN))
|
|
+ return -EPERM;
|
|
+
|
|
+ spin_lock_irq(&bp->lock);
|
|
+ err = __b44_writephy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
|
|
+ spin_unlock_irq(&bp->lock);
|
|
+
|
|
+ return err;
|
|
+
|
|
+ default:
|
|
+ break;
|
|
+ };
|
|
+ return -EOPNOTSUPP;
|
|
+
|
|
out:
|
|
return err;
|
|
}
|
|
@@ -1868,27 +2246,60 @@
|
|
static int __devinit b44_get_invariants(struct b44 *bp)
|
|
{
|
|
u8 eeprom[128];
|
|
- int err;
|
|
+ u8 buf[32];
|
|
+ int err = 0;
|
|
+ unsigned long flags;
|
|
+
|
|
+#ifdef CONFIG_BCM947XX
|
|
+ if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) {
|
|
+ /*
|
|
+ * BCM47xx boards don't have a EEPROM. The MAC is stored in
|
|
+ * a NVRAM area somewhere in the flash memory.
|
|
+ */
|
|
+ sprintf(buf, "et%dmacaddr", b44_4713_instance);
|
|
+ if (nvram_get(buf)) {
|
|
+ e_aton(nvram_get(buf), bp->dev->dev_addr);
|
|
+ } else {
|
|
+ /*
|
|
+ * Getting the MAC out of NVRAM failed. To make it work
|
|
+ * here, we simply rely on the bootloader to write the
|
|
+ * MAC into the CAM.
|
|
+ */
|
|
+ spin_lock_irqsave(&bp->lock, flags);
|
|
+ __b44_cam_read(bp, bp->dev->dev_addr, 0);
|
|
+ spin_unlock_irqrestore(&bp->lock, flags);
|
|
+ }
|
|
|
|
- err = b44_read_eeprom(bp, &eeprom[0]);
|
|
- if (err)
|
|
- goto out;
|
|
+ /*
|
|
+ * BCM47xx boards don't have a PHY. Usually there is a switch
|
|
+ * chip with multiple PHYs connected to the PHY port.
|
|
+ */
|
|
+ bp->phy_addr = B44_PHY_ADDR_NO_PHY;
|
|
+ bp->dma_offset = 0;
|
|
+ } else
|
|
+#endif
|
|
+ {
|
|
+ err = b44_read_eeprom(bp, &eeprom[0]);
|
|
+ if (err)
|
|
+ goto out;
|
|
|
|
- bp->dev->dev_addr[0] = eeprom[79];
|
|
- bp->dev->dev_addr[1] = eeprom[78];
|
|
- bp->dev->dev_addr[2] = eeprom[81];
|
|
- bp->dev->dev_addr[3] = eeprom[80];
|
|
- bp->dev->dev_addr[4] = eeprom[83];
|
|
- bp->dev->dev_addr[5] = eeprom[82];
|
|
+ bp->dev->dev_addr[0] = eeprom[79];
|
|
+ bp->dev->dev_addr[1] = eeprom[78];
|
|
+ bp->dev->dev_addr[2] = eeprom[81];
|
|
+ bp->dev->dev_addr[3] = eeprom[80];
|
|
+ bp->dev->dev_addr[4] = eeprom[83];
|
|
+ bp->dev->dev_addr[5] = eeprom[82];
|
|
|
|
- if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
|
|
- printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
|
|
- return -EINVAL;
|
|
- }
|
|
+ if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
|
|
+ printk(KERN_ERR PFX "Invalid MAC address found in EEPROM\n");
|
|
+ return -EINVAL;
|
|
+ }
|
|
|
|
- memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
|
|
+ memcpy(bp->dev->perm_addr, bp->dev->dev_addr, bp->dev->addr_len);
|
|
|
|
- bp->phy_addr = eeprom[90] & 0x1f;
|
|
+ bp->phy_addr = eeprom[90] & 0x1f;
|
|
+ bp->dma_offset = SB_PCI_DMA;
|
|
+ }
|
|
|
|
/* With this, plus the rx_header prepended to the data by the
|
|
* hardware, we'll land the ethernet header on a 2-byte boundary.
|
|
@@ -1898,7 +2309,6 @@
|
|
bp->imask = IMASK_DEF;
|
|
|
|
bp->core_unit = ssb_core_unit(bp);
|
|
- bp->dma_offset = SB_PCI_DMA;
|
|
|
|
/* XXX - really required?
|
|
bp->flags |= B44_FLAG_BUGGY_TXPTR;
|
|
@@ -2048,11 +2458,17 @@
|
|
*/
|
|
b44_chip_reset(bp);
|
|
|
|
- printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
|
|
+ printk(KERN_INFO "%s: Broadcom %s 10/100BaseT Ethernet ", dev->name,
|
|
+ (pdev->device == PCI_DEVICE_ID_BCM4713) ? "47xx" : "4400");
|
|
for (i = 0; i < 6; i++)
|
|
printk("%2.2x%c", dev->dev_addr[i],
|
|
i == 5 ? '\n' : ':');
|
|
|
|
+ /* Initialize phy */
|
|
+ spin_lock_irq(&bp->lock);
|
|
+ b44_chip_reset(bp);
|
|
+ spin_unlock_irq(&bp->lock);
|
|
+
|
|
return 0;
|
|
|
|
err_out_iounmap:
|
|
diff -Nur linux-2.6.17/drivers/net/b44.h linux-2.6.17-owrt/drivers/net/b44.h
|
|
--- linux-2.6.17/drivers/net/b44.h 2006-06-18 03:49:35.000000000 +0200
|
|
+++ linux-2.6.17-owrt/drivers/net/b44.h 2006-06-18 16:01:10.000000000 +0200
|
|
@@ -292,6 +292,10 @@
|
|
#define SSB_PCI_MASK1 0xfc000000
|
|
#define SSB_PCI_MASK2 0xc0000000
|
|
|
|
+#define br32(bp, REG) readl((void *)bp->regs + (REG))
|
|
+#define bw32(bp, REG,VAL) writel((VAL), (void *)bp->regs + (REG))
|
|
+#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
|
|
+
|
|
/* 4400 PHY registers */
|
|
#define B44_MII_AUXCTRL 24 /* Auxiliary Control */
|
|
#define MII_AUXCTRL_DUPLEX 0x0001 /* Full Duplex */
|
|
@@ -345,6 +349,8 @@
|
|
};
|
|
|
|
#define B44_MCAST_TABLE_SIZE 32
|
|
+#define B44_PHY_ADDR_NO_PHY 30
|
|
+#define B44_MDC_RATIO 5000000
|
|
|
|
#define B44_STAT_REG_DECLARE \
|
|
_B44(tx_good_octets) \
|
|
@@ -420,6 +426,7 @@
|
|
|
|
u32 dma_offset;
|
|
u32 flags;
|
|
+#define B44_FLAG_INIT_COMPLETE 0x00000001
|
|
#define B44_FLAG_BUGGY_TXPTR 0x00000002
|
|
#define B44_FLAG_REORDER_BUG 0x00000004
|
|
#define B44_FLAG_PAUSE_AUTO 0x00008000
|