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769a390d81
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@31130 3c298f89-4303-0410-b956-a3cf2f4a3e73
141 lines
4.5 KiB
Diff
141 lines
4.5 KiB
Diff
From 81f9e7d6aa1dde65483387ba9e9823ef44f90435 Mon Sep 17 00:00:00 2001
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From: Florian Fainelli <florian@openwrt.org>
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Date: Wed, 25 Jan 2012 17:40:03 +0100
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Subject: [PATCH 10/63] MIPS: BCM63XX: define internal registers offsets of the SPI controller
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BCM6338, BCM6348, BCM6358 and BCM6368 basically use the same SPI controller
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though the internal registers are shuffled, which still allows a common
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driver to drive that IP block.
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Signed-off-by: Florian Fainelli <florian@openwrt.org>
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---
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 119 +++++++++++++++++++++
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1 files changed, 119 insertions(+), 0 deletions(-)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -973,4 +973,123 @@
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#define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14)
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#define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18)
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+/*************************************************************************
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+ * _REG relative to RSET_SPI
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+ *************************************************************************/
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+
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+/* BCM 6338 SPI core */
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+#define SPI_6338_CMD 0x00 /* 16-bits register */
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+#define SPI_6338_INT_STATUS 0x02
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+#define SPI_6338_INT_MASK_ST 0x03
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+#define SPI_6338_INT_MASK 0x04
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+#define SPI_6338_ST 0x05
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+#define SPI_6338_CLK_CFG 0x06
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+#define SPI_6338_FILL_BYTE 0x07
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+#define SPI_6338_MSG_TAIL 0x09
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+#define SPI_6338_RX_TAIL 0x0b
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+#define SPI_6338_MSG_CTL 0x40
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+#define SPI_6338_MSG_DATA 0x41
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+#define SPI_6338_MSG_DATA_SIZE 0x3f
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+#define SPI_6338_RX_DATA 0x80
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+#define SPI_6338_RX_DATA_SIZE 0x3f
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+
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+/* BCM 6348 SPI core */
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+#define SPI_6348_CMD 0x00 /* 16-bits register */
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+#define SPI_6348_INT_STATUS 0x02
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+#define SPI_6348_INT_MASK_ST 0x03
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+#define SPI_6348_INT_MASK 0x04
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+#define SPI_6348_ST 0x05
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+#define SPI_6348_CLK_CFG 0x06
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+#define SPI_6348_FILL_BYTE 0x07
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+#define SPI_6348_MSG_TAIL 0x09
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+#define SPI_6348_RX_TAIL 0x0b
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+#define SPI_6348_MSG_CTL 0x40
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+#define SPI_6348_MSG_DATA 0x41
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+#define SPI_6348_MSG_DATA_SIZE 0x3f
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+#define SPI_6348_RX_DATA 0x80
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+#define SPI_6348_RX_DATA_SIZE 0x3f
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+
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+/* BCM 6358 SPI core */
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+#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
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+#define SPI_6358_MSG_DATA 0x02
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+#define SPI_6358_MSG_DATA_SIZE 0x21e
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+#define SPI_6358_RX_DATA 0x400
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+#define SPI_6358_RX_DATA_SIZE 0x220
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+#define SPI_6358_CMD 0x700 /* 16-bits register */
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+#define SPI_6358_INT_STATUS 0x702
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+#define SPI_6358_INT_MASK_ST 0x703
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+#define SPI_6358_INT_MASK 0x704
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+#define SPI_6358_ST 0x705
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+#define SPI_6358_CLK_CFG 0x706
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+#define SPI_6358_FILL_BYTE 0x707
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+#define SPI_6358_MSG_TAIL 0x709
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+#define SPI_6358_RX_TAIL 0x70B
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+
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+/* BCM 6358 SPI core */
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+#define SPI_6368_MSG_CTL 0x00 /* 16-bits register */
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+#define SPI_6368_MSG_DATA 0x02
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+#define SPI_6368_MSG_DATA_SIZE 0x21e
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+#define SPI_6368_RX_DATA 0x400
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+#define SPI_6368_RX_DATA_SIZE 0x220
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+#define SPI_6368_CMD 0x700 /* 16-bits register */
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+#define SPI_6368_INT_STATUS 0x702
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+#define SPI_6368_INT_MASK_ST 0x703
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+#define SPI_6368_INT_MASK 0x704
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+#define SPI_6368_ST 0x705
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+#define SPI_6368_CLK_CFG 0x706
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+#define SPI_6368_FILL_BYTE 0x707
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+#define SPI_6368_MSG_TAIL 0x709
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+#define SPI_6368_RX_TAIL 0x70B
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+
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+/* Shared SPI definitions */
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+
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+/* Message configuration */
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+#define SPI_FD_RW 0x00
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+#define SPI_HD_W 0x01
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+#define SPI_HD_R 0x02
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+#define SPI_BYTE_CNT_SHIFT 0
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+#define SPI_MSG_TYPE_SHIFT 14
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+
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+/* Command */
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+#define SPI_CMD_NOOP 0x00
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+#define SPI_CMD_SOFT_RESET 0x01
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+#define SPI_CMD_HARD_RESET 0x02
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+#define SPI_CMD_START_IMMEDIATE 0x03
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+#define SPI_CMD_COMMAND_SHIFT 0
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+#define SPI_CMD_COMMAND_MASK 0x000f
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+#define SPI_CMD_DEVICE_ID_SHIFT 4
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+#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
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+#define SPI_CMD_ONE_BYTE_SHIFT 11
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+#define SPI_CMD_ONE_WIRE_SHIFT 12
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+#define SPI_DEV_ID_0 0
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+#define SPI_DEV_ID_1 1
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+#define SPI_DEV_ID_2 2
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+#define SPI_DEV_ID_3 3
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+
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+/* Interrupt mask */
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+#define SPI_INTR_CMD_DONE 0x01
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+#define SPI_INTR_RX_OVERFLOW 0x02
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+#define SPI_INTR_TX_UNDERFLOW 0x04
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+#define SPI_INTR_TX_OVERFLOW 0x08
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+#define SPI_INTR_RX_UNDERFLOW 0x10
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+#define SPI_INTR_CLEAR_ALL 0x1f
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+
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+/* Status */
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+#define SPI_RX_EMPTY 0x02
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+#define SPI_CMD_BUSY 0x04
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+#define SPI_SERIAL_BUSY 0x08
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+
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+/* Clock configuration */
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+#define SPI_CLK_20MHZ 0x00
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+#define SPI_CLK_0_391MHZ 0x01
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+#define SPI_CLK_0_781MHZ 0x02 /* default */
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+#define SPI_CLK_1_563MHZ 0x03
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+#define SPI_CLK_3_125MHZ 0x04
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+#define SPI_CLK_6_250MHZ 0x05
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+#define SPI_CLK_12_50MHZ 0x06
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+#define SPI_CLK_MASK 0x07
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+#define SPI_SSOFFTIME_MASK 0x38
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+#define SPI_SSOFFTIME_SHIFT 3
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+#define SPI_BYTE_SWAP 0x80
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+
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#endif /* BCM63XX_REGS_H_ */
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