mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-12 18:08:38 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@30406 3c298f89-4303-0410-b956-a3cf2f4a3e73
508 lines
12 KiB
C
508 lines
12 KiB
C
/*
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* SPI controller driver for the Mikrotik RB4xx boards
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*
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* Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
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*
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* This file was based on the patches for Linux 2.6.27.39 published by
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* MikroTik for their RouterBoard 4xx series devices.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/workqueue.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <asm/mach-ath79/ath79.h>
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#define DRV_NAME "rb4xx-spi"
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#define DRV_DESC "Mikrotik RB4xx SPI controller driver"
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#define DRV_VERSION "0.1.0"
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#define SPI_CTRL_FASTEST 0x40
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#define SPI_FLASH_HZ 33333334
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#define SPI_CPLD_HZ 33333334
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#define CPLD_CMD_READ_FAST 0x0b
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#undef RB4XX_SPI_DEBUG
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struct rb4xx_spi {
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void __iomem *base;
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struct spi_master *master;
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unsigned spi_ctrl_flash;
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unsigned spi_ctrl_fread;
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struct clk *ahb_clk;
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unsigned long ahb_freq;
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spinlock_t lock;
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struct list_head queue;
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int busy:1;
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int cs_wait;
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};
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static unsigned spi_clk_low = AR71XX_SPI_IOC_CS1;
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#ifdef RB4XX_SPI_DEBUG
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static inline void do_spi_delay(void)
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{
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ndelay(20000);
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}
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#else
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static inline void do_spi_delay(void) { }
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#endif
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static inline void do_spi_init(struct spi_device *spi)
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{
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unsigned cs = AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1;
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if (!(spi->mode & SPI_CS_HIGH))
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cs ^= (spi->chip_select == 2) ? AR71XX_SPI_IOC_CS1 :
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AR71XX_SPI_IOC_CS0;
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spi_clk_low = cs;
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}
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static inline void do_spi_finish(void __iomem *base)
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{
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do_spi_delay();
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__raw_writel(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1,
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base + AR71XX_SPI_REG_IOC);
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}
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static inline void do_spi_clk(void __iomem *base, int bit)
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{
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unsigned bval = spi_clk_low | ((bit & 1) ? AR71XX_SPI_IOC_DO : 0);
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do_spi_delay();
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__raw_writel(bval, base + AR71XX_SPI_REG_IOC);
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do_spi_delay();
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__raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC);
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}
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static void do_spi_byte(void __iomem *base, unsigned char byte)
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{
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do_spi_clk(base, byte >> 7);
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do_spi_clk(base, byte >> 6);
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do_spi_clk(base, byte >> 5);
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do_spi_clk(base, byte >> 4);
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do_spi_clk(base, byte >> 3);
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do_spi_clk(base, byte >> 2);
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do_spi_clk(base, byte >> 1);
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do_spi_clk(base, byte);
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pr_debug("spi_byte sent 0x%02x got 0x%02x\n",
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(unsigned)byte,
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(unsigned char)__raw_readl(base + AR71XX_SPI_REG_RDS));
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}
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static inline void do_spi_clk_fast(void __iomem *base, unsigned bit1,
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unsigned bit2)
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{
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unsigned bval = (spi_clk_low |
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((bit1 & 1) ? AR71XX_SPI_IOC_DO : 0) |
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((bit2 & 1) ? AR71XX_SPI_IOC_CS2 : 0));
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do_spi_delay();
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__raw_writel(bval, base + AR71XX_SPI_REG_IOC);
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do_spi_delay();
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__raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC);
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}
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static void do_spi_byte_fast(void __iomem *base, unsigned char byte)
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{
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do_spi_clk_fast(base, byte >> 7, byte >> 6);
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do_spi_clk_fast(base, byte >> 5, byte >> 4);
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do_spi_clk_fast(base, byte >> 3, byte >> 2);
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do_spi_clk_fast(base, byte >> 1, byte >> 0);
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pr_debug("spi_byte_fast sent 0x%02x got 0x%02x\n",
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(unsigned)byte,
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(unsigned char) __raw_readl(base + AR71XX_SPI_REG_RDS));
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}
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static int rb4xx_spi_txrx(void __iomem *base, struct spi_transfer *t)
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{
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const unsigned char *rxv_ptr = NULL;
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const unsigned char *tx_ptr = t->tx_buf;
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unsigned char *rx_ptr = t->rx_buf;
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unsigned i;
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pr_debug("spi_txrx len %u tx %u rx %u\n",
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t->len,
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(t->tx_buf ? 1 : 0),
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(t->rx_buf ? 1 : 0));
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if (t->verify) {
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rxv_ptr = tx_ptr;
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tx_ptr = NULL;
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}
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for (i = 0; i < t->len; ++i) {
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unsigned char sdata = tx_ptr ? tx_ptr[i] : 0;
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if (t->fast_write)
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do_spi_byte_fast(base, sdata);
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else
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do_spi_byte(base, sdata);
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if (rx_ptr) {
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rx_ptr[i] = __raw_readl(base + AR71XX_SPI_REG_RDS) & 0xff;
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} else if (rxv_ptr) {
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unsigned char c = __raw_readl(base + AR71XX_SPI_REG_RDS);
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if (rxv_ptr[i] != c)
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return i;
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}
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}
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return i;
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}
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static int rb4xx_spi_read_fast(struct rb4xx_spi *rbspi,
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struct spi_message *m)
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{
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struct spi_transfer *t;
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const unsigned char *tx_ptr;
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unsigned addr;
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void __iomem *base = rbspi->base;
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/* check for exactly two transfers */
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if (list_empty(&m->transfers) ||
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list_is_last(m->transfers.next, &m->transfers) ||
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!list_is_last(m->transfers.next->next, &m->transfers)) {
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return -1;
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}
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/* first transfer contains command and address */
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t = list_entry(m->transfers.next,
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struct spi_transfer, transfer_list);
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if (t->len != 5 || t->tx_buf == NULL)
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return -1;
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tx_ptr = t->tx_buf;
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if (tx_ptr[0] != CPLD_CMD_READ_FAST)
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return -1;
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addr = tx_ptr[1];
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addr = tx_ptr[2] | (addr << 8);
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addr = tx_ptr[3] | (addr << 8);
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addr += (unsigned) base;
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m->actual_length += t->len;
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/* second transfer contains data itself */
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t = list_entry(m->transfers.next->next,
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struct spi_transfer, transfer_list);
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if (t->tx_buf && !t->verify)
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return -1;
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__raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
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__raw_writel(rbspi->spi_ctrl_fread, base + AR71XX_SPI_REG_CTRL);
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__raw_writel(0, base + AR71XX_SPI_REG_FS);
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if (t->rx_buf) {
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memcpy(t->rx_buf, (const void *)addr, t->len);
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} else if (t->tx_buf) {
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unsigned char buf[t->len];
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memcpy(buf, (const void *)addr, t->len);
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if (memcmp(t->tx_buf, buf, t->len) != 0)
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m->status = -EMSGSIZE;
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}
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m->actual_length += t->len;
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if (rbspi->spi_ctrl_flash != rbspi->spi_ctrl_fread) {
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__raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
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__raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL);
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__raw_writel(0, base + AR71XX_SPI_REG_FS);
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}
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return 0;
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}
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static int rb4xx_spi_msg(struct rb4xx_spi *rbspi, struct spi_message *m)
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{
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struct spi_transfer *t = NULL;
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void __iomem *base = rbspi->base;
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m->status = 0;
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if (list_empty(&m->transfers))
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return -1;
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if (m->fast_read)
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if (rb4xx_spi_read_fast(rbspi, m) == 0)
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return -1;
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__raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
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__raw_writel(SPI_CTRL_FASTEST, base + AR71XX_SPI_REG_CTRL);
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do_spi_init(m->spi);
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list_for_each_entry(t, &m->transfers, transfer_list) {
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int len;
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len = rb4xx_spi_txrx(base, t);
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if (len != t->len) {
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m->status = -EMSGSIZE;
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break;
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}
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m->actual_length += len;
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if (t->cs_change) {
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if (list_is_last(&t->transfer_list, &m->transfers)) {
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/* wait for continuation */
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return m->spi->chip_select;
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}
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do_spi_finish(base);
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ndelay(100);
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}
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}
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do_spi_finish(base);
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__raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL);
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__raw_writel(0, base + AR71XX_SPI_REG_FS);
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return -1;
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}
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static void rb4xx_spi_process_queue_locked(struct rb4xx_spi *rbspi,
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unsigned long *flags)
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{
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int cs = rbspi->cs_wait;
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rbspi->busy = 1;
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while (!list_empty(&rbspi->queue)) {
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struct spi_message *m;
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list_for_each_entry(m, &rbspi->queue, queue)
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if (cs < 0 || cs == m->spi->chip_select)
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break;
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if (&m->queue == &rbspi->queue)
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break;
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list_del_init(&m->queue);
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spin_unlock_irqrestore(&rbspi->lock, *flags);
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cs = rb4xx_spi_msg(rbspi, m);
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m->complete(m->context);
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spin_lock_irqsave(&rbspi->lock, *flags);
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}
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rbspi->cs_wait = cs;
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rbspi->busy = 0;
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if (cs >= 0) {
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/* TODO: add timer to unlock cs after 1s inactivity */
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}
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}
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static int rb4xx_spi_transfer(struct spi_device *spi,
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struct spi_message *m)
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{
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struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
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unsigned long flags;
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m->actual_length = 0;
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m->status = -EINPROGRESS;
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spin_lock_irqsave(&rbspi->lock, flags);
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list_add_tail(&m->queue, &rbspi->queue);
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if (rbspi->busy ||
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(rbspi->cs_wait >= 0 && rbspi->cs_wait != m->spi->chip_select)) {
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/* job will be done later */
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spin_unlock_irqrestore(&rbspi->lock, flags);
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return 0;
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}
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/* process job in current context */
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rb4xx_spi_process_queue_locked(rbspi, &flags);
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spin_unlock_irqrestore(&rbspi->lock, flags);
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return 0;
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}
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static int rb4xx_spi_setup(struct spi_device *spi)
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{
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struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
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unsigned long flags;
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if (spi->mode & ~(SPI_CS_HIGH)) {
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dev_err(&spi->dev, "mode %x not supported\n",
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(unsigned) spi->mode);
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return -EINVAL;
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}
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if (spi->bits_per_word != 8 && spi->bits_per_word != 0) {
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dev_err(&spi->dev, "bits_per_word %u not supported\n",
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(unsigned) spi->bits_per_word);
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return -EINVAL;
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}
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spin_lock_irqsave(&rbspi->lock, flags);
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if (rbspi->cs_wait == spi->chip_select && !rbspi->busy) {
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rbspi->cs_wait = -1;
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rb4xx_spi_process_queue_locked(rbspi, &flags);
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}
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spin_unlock_irqrestore(&rbspi->lock, flags);
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return 0;
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}
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static unsigned get_spi_ctrl(struct rb4xx_spi *rbspi, unsigned hz_max,
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const char *name)
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{
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unsigned div;
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div = (rbspi->ahb_freq - 1) / (2 * hz_max);
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/*
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* CPU has a bug at (div == 0) - first bit read is random
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*/
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if (div == 0)
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++div;
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if (name) {
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unsigned ahb_khz = (rbspi->ahb_freq + 500) / 1000;
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unsigned div_real = 2 * (div + 1);
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pr_debug("rb4xx: %s SPI clock %u kHz (AHB %u kHz / %u)\n",
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name,
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ahb_khz / div_real,
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ahb_khz, div_real);
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}
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return SPI_CTRL_FASTEST + div;
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}
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static int rb4xx_spi_probe(struct platform_device *pdev)
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{
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struct spi_master *master;
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struct rb4xx_spi *rbspi;
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struct resource *r;
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int err = 0;
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master = spi_alloc_master(&pdev->dev, sizeof(*rbspi));
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if (master == NULL) {
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dev_err(&pdev->dev, "no memory for spi_master\n");
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err = -ENOMEM;
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goto err_out;
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}
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master->bus_num = 0;
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master->num_chipselect = 3;
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master->setup = rb4xx_spi_setup;
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master->transfer = rb4xx_spi_transfer;
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rbspi = spi_master_get_devdata(master);
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rbspi->ahb_clk = clk_get(&pdev->dev, "ahb");
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if (IS_ERR(rbspi->ahb_clk)) {
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err = PTR_ERR(rbspi->ahb_clk);
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goto err_put_master;
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}
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err = clk_enable(rbspi->ahb_clk);
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if (err)
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goto err_clk_put;
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rbspi->ahb_freq = clk_get_rate(rbspi->ahb_clk);
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if (!rbspi->ahb_freq) {
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err = -EINVAL;
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goto err_clk_disable;
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}
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platform_set_drvdata(pdev, rbspi);
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (r == NULL) {
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err = -ENOENT;
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goto err_clk_disable;
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}
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rbspi->base = ioremap(r->start, r->end - r->start + 1);
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if (!rbspi->base) {
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err = -ENXIO;
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goto err_clk_disable;
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}
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rbspi->master = master;
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rbspi->spi_ctrl_flash = get_spi_ctrl(rbspi, SPI_FLASH_HZ, "FLASH");
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rbspi->spi_ctrl_fread = get_spi_ctrl(rbspi, SPI_CPLD_HZ, "CPLD");
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rbspi->cs_wait = -1;
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spin_lock_init(&rbspi->lock);
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INIT_LIST_HEAD(&rbspi->queue);
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err = spi_register_master(master);
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if (err) {
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dev_err(&pdev->dev, "failed to register SPI master\n");
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goto err_iounmap;
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}
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return 0;
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err_iounmap:
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iounmap(rbspi->base);
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err_clk_disable:
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clk_disable(rbspi->ahb_clk);
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err_clk_put:
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clk_put(rbspi->ahb_clk);
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err_put_master:
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platform_set_drvdata(pdev, NULL);
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spi_master_put(master);
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err_out:
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return err;
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}
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static int rb4xx_spi_remove(struct platform_device *pdev)
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{
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struct rb4xx_spi *rbspi = platform_get_drvdata(pdev);
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iounmap(rbspi->base);
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clk_disable(rbspi->ahb_clk);
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clk_put(rbspi->ahb_clk);
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platform_set_drvdata(pdev, NULL);
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spi_master_put(rbspi->master);
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return 0;
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}
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static struct platform_driver rb4xx_spi_drv = {
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.probe = rb4xx_spi_probe,
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.remove = rb4xx_spi_remove,
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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},
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};
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static int __init rb4xx_spi_init(void)
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{
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return platform_driver_register(&rb4xx_spi_drv);
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}
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subsys_initcall(rb4xx_spi_init);
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static void __exit rb4xx_spi_exit(void)
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{
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platform_driver_unregister(&rb4xx_spi_drv);
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}
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module_exit(rb4xx_spi_exit);
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MODULE_DESCRIPTION(DRV_DESC);
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MODULE_VERSION(DRV_VERSION);
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MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
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MODULE_LICENSE("GPL v2");
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