mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-09-12 15:11:29 +03:00
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@16547 3c298f89-4303-0410-b956-a3cf2f4a3e73
514 lines
14 KiB
Diff
514 lines
14 KiB
Diff
From 2bef1f8ce148cce9e782f75f9537767c1d8c0eea Mon Sep 17 00:00:00 2001
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From: Kurt Mahan <kmahan@freescale.com>
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Date: Wed, 31 Oct 2007 16:58:27 -0600
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Subject: [PATCH] Core Coldfire/MCF5445x arch/mm changes.
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LTIBName: mcfv4e-arch-mm-mods-1
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Signed-off-by: Kurt Mahan <kmahan@freescale.com>
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---
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arch/m68k/mm/Makefile | 1 +
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arch/m68k/mm/cache.c | 41 ++++++++
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arch/m68k/mm/cf-mmu.c | 251 +++++++++++++++++++++++++++++++++++++++++++++++++
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arch/m68k/mm/hwtest.c | 2 +
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arch/m68k/mm/init.c | 3 +-
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arch/m68k/mm/kmap.c | 13 +++
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arch/m68k/mm/memory.c | 66 +++++++++++++-
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7 files changed, 373 insertions(+), 4 deletions(-)
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create mode 100644 arch/m68k/mm/cf-mmu.c
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--- a/arch/m68k/mm/Makefile
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+++ b/arch/m68k/mm/Makefile
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@@ -6,3 +6,4 @@ obj-y := cache.o init.o fault.o hwtest.
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obj-$(CONFIG_MMU_MOTOROLA) += kmap.o memory.o motorola.o
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obj-$(CONFIG_MMU_SUN3) += sun3kmap.o sun3mmu.o
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+obj-$(CONFIG_MMU_CFV4E) += cf-mmu.o kmap.o memory.o
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--- a/arch/m68k/mm/cache.c
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+++ b/arch/m68k/mm/cache.c
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@@ -10,7 +10,11 @@
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#include <asm/pgalloc.h>
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#include <asm/traps.h>
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+#ifdef CONFIG_COLDFIRE
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+#include <asm/cfcache.h>
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+#endif /* CONFIG_COLDFIRE */
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+#ifndef CONFIG_COLDFIRE
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static unsigned long virt_to_phys_slow(unsigned long vaddr)
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{
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if (CPU_IS_060) {
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@@ -69,11 +73,45 @@ static unsigned long virt_to_phys_slow(u
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}
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return 0;
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}
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+#endif /* CONFIG_COLDFIRE */
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+
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/* Push n pages at kernel virtual address and clear the icache */
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/* RZ: use cpush %bc instead of cpush %dc, cinv %ic */
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void flush_icache_range(unsigned long address, unsigned long endaddr)
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{
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+#ifdef CONFIG_COLDFIRE
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+ unsigned long set;
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+ unsigned long start_set;
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+ unsigned long end_set;
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+
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+ start_set = address & _ICACHE_SET_MASK;
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+ end_set = endaddr & _ICACHE_SET_MASK;
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+
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+ if (start_set > end_set) {
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+ /* from the begining to the lowest address */
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+ for (set = 0; set <= end_set; set += (0x10 - 3))
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+ asm volatile ("cpushl %%ic,(%0)\n"
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+ "\taddq%.l #1,%0\n"
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+ "\tcpushl %%ic,(%0)\n"
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+ "\taddq%.l #1,%0\n"
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+ "\tcpushl %%ic,(%0)\n"
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+ "\taddq%.l #1,%0\n"
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+ "\tcpushl %%ic,(%0)" : : "a" (set));
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+
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+ /* next loop will finish the cache ie pass the hole */
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+ end_set = LAST_ICACHE_ADDR;
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+ }
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+ for (set = start_set; set <= end_set; set += (0x10 - 3))
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+ asm volatile ("cpushl %%ic,(%0)\n"
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+ "\taddq%.l #1,%0\n"
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+ "\tcpushl %%ic,(%0)\n"
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+ "\taddq%.l #1,%0\n"
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+ "\tcpushl %%ic,(%0)\n"
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+ "\taddq%.l #1,%0\n"
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+ "\tcpushl %%ic,(%0)" : : "a" (set));
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+
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+#else /* !CONFIG_COLDFIRE */
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if (CPU_IS_040_OR_060) {
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address &= PAGE_MASK;
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@@ -94,9 +132,11 @@ void flush_icache_range(unsigned long ad
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: "=&d" (tmp)
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: "di" (FLUSH_I));
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}
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+#endif /* CONFIG_COLDFIRE */
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}
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EXPORT_SYMBOL(flush_icache_range);
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+#ifndef CONFIG_COLDFIRE
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void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
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unsigned long addr, int len)
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{
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@@ -115,4 +155,5 @@ void flush_icache_user_range(struct vm_a
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: "di" (FLUSH_I));
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}
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}
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+#endif /* CONFIG_COLDFIRE */
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--- /dev/null
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+++ b/arch/m68k/mm/cf-mmu.c
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@@ -0,0 +1,251 @@
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+/*
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+ * linux/arch/m68k/mm/cf-mmu.c
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+ *
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+ * Based upon linux/arch/m68k/mm/sun3mmu.c
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+ * Based upon linux/arch/ppc/mm/mmu_context.c
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+ *
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+ * Implementations of mm routines specific to the Coldfire MMU.
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+ *
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+ * Copyright (c) 2008 Freescale Semiconductor, Inc.
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+ */
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+
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+#include <linux/signal.h>
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+#include <linux/sched.h>
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+#include <linux/mm.h>
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+#include <linux/swap.h>
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+#include <linux/kernel.h>
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+#include <linux/string.h>
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+#include <linux/types.h>
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+#include <linux/init.h>
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+#ifdef CONFIG_BLK_DEV_RAM
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+#include <linux/blkdev.h>
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+#endif
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+#include <linux/bootmem.h>
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+
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+#include <asm/setup.h>
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+#include <asm/uaccess.h>
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+#include <asm/page.h>
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+#include <asm/pgtable.h>
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+#include <asm/system.h>
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+#include <asm/machdep.h>
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+#include <asm/io.h>
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+#include <asm/mmu_context.h>
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+#include <asm/cf_pgalloc.h>
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+
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+#include <asm/coldfire.h>
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+#include <asm/tlbflush.h>
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+
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+mm_context_t next_mmu_context;
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+unsigned long context_map[LAST_CONTEXT / BITS_PER_LONG + 1];
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+
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+atomic_t nr_free_contexts;
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+struct mm_struct *context_mm[LAST_CONTEXT+1];
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+void steal_context(void);
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+
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+
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+const char bad_pmd_string[] = "Bad pmd in pte_alloc: %08lx\n";
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+
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+extern unsigned long empty_bad_page_table;
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+extern unsigned long empty_bad_page;
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+extern unsigned long num_pages;
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+
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+extern char __init_begin, __init_end;
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+
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+void free_initmem(void)
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+{
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+ unsigned long addr;
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+ unsigned long start = (unsigned long)&__init_begin;
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+ unsigned long end = (unsigned long)&__init_end;
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+
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+ printk(KERN_INFO "free_initmem: __init_begin = 0x%lx __init_end = 0x%lx\n", start, end);
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+
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+ addr = (unsigned long)&__init_begin;
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+ for (; addr < (unsigned long)&__init_end; addr += PAGE_SIZE) {
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+ /* not currently used */
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+ virt_to_page(addr)->flags &= ~(1 << PG_reserved);
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+ init_page_count(virt_to_page(addr));
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+ free_page(addr);
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+ totalram_pages++;
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+ }
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+}
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+
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+/* Coldfire paging_init derived from sun3 */
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+void __init paging_init(void)
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+{
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+ pgd_t * pg_dir;
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+ pte_t * pg_table;
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+ int i;
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+ unsigned long address;
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+ unsigned long next_pgtable;
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+ unsigned long bootmem_end;
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+ unsigned long zones_size[MAX_NR_ZONES];
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+ unsigned long size;
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+ enum zone_type zone;
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+
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+ empty_zero_page = (void *)alloc_bootmem_pages(PAGE_SIZE);
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+ memset((void *)empty_zero_page, 0, PAGE_SIZE);
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+
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+ pg_dir = swapper_pg_dir;
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+ memset(swapper_pg_dir, 0, sizeof (swapper_pg_dir));
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+
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+ size = num_pages * sizeof(pte_t);
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+ size = (size + PAGE_SIZE) & ~(PAGE_SIZE-1);
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+ next_pgtable = (unsigned long)alloc_bootmem_pages(size);
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+
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+ bootmem_end = (next_pgtable + size + PAGE_SIZE) & PAGE_MASK;
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+ pg_dir += PAGE_OFFSET >> PGDIR_SHIFT;
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+
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+ address = PAGE_OFFSET;
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+ while (address < (unsigned long)high_memory)
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+ {
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+ pg_table = (pte_t *)next_pgtable;
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+ next_pgtable += PTRS_PER_PTE * sizeof (pte_t);
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+ pgd_val(*pg_dir) = (unsigned long) pg_table;
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+ pg_dir++;
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+
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+ /* now change pg_table to kernel virtual addresses */
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+ for (i=0; i<PTRS_PER_PTE; ++i, ++pg_table)
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+ {
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+ pte_t pte = pfn_pte(virt_to_pfn(address), PAGE_INIT);
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+ if (address >= (unsigned long)high_memory)
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+ pte_val (pte) = 0;
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+
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+ set_pte (pg_table, pte);
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+ address += PAGE_SIZE;
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+ }
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+ }
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+
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+ current->mm = NULL;
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+
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+ /* clear zones */
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+ for (zone = 0; zone < MAX_NR_ZONES; zone++)
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+ zones_size[zone] = 0x0;
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+
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+ /* allocate the bottom 32M (0x40x 0x41x) to DMA - head.S marks them NO CACHE */
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+ /* JKM - this should be changed to allocate from the TOP (0x4f,0x4e) but the
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+ * allocator is being a bit challenging */
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+ zones_size[ZONE_DMA] = (32*1024*1024) >> PAGE_SHIFT;
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+
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+ /* allocate the rest to NORMAL - head.S marks them CACHE */
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+ zones_size[ZONE_NORMAL] = (((unsigned long)high_memory - PAGE_OFFSET) >> PAGE_SHIFT) - zones_size[0];
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+
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+ free_area_init(zones_size);
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+}
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+
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+
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+int cf_tlb_miss(struct pt_regs *regs, int write, int dtlb, int extension_word)
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+{
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+ struct mm_struct *mm;
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+ pgd_t *pgd;
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+ pmd_t *pmd;
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+ pte_t *pte;
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+ unsigned long mmuar;
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+ int asid;
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+ int flags;
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+
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+ local_save_flags(flags);
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+ local_irq_disable();
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+
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+ mmuar = ( dtlb ) ? regs->mmuar
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+ : regs->pc + (extension_word * sizeof(long));
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+
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+ mm = (!user_mode(regs) && (mmuar >= PAGE_OFFSET)) ? &init_mm
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+ : current->mm;
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+ if (!mm) {
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+ local_irq_restore(flags);
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+ return (-1);
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+ }
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+
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+ pgd = pgd_offset(mm, mmuar);
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+ if (pgd_none(*pgd)) {
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+ local_irq_restore(flags);
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+ return (-1);
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+ }
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+
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+ pmd = pmd_offset(pgd, mmuar);
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+ if (pmd_none(*pmd)) {
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+ local_irq_restore(flags);
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+ return (-1);
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+ }
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+
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+ pte = (mmuar >= PAGE_OFFSET) ? pte_offset_kernel(pmd, mmuar)
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+ : pte_offset_map(pmd, mmuar);
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+ if (pte_none(*pte) || !pte_present(*pte)) {
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+ local_irq_restore(flags);
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+ return (-1);
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+ }
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+
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+ if (write) {
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+ if (!pte_write(*pte)) {
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+ local_irq_restore(flags);
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+ return (-1);
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+ }
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+ set_pte(pte, pte_mkdirty(*pte));
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+ }
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+
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+ set_pte(pte, pte_mkyoung(*pte));
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+ asid = mm->context & 0xff;
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+ if (!pte_dirty(*pte) && mmuar<=PAGE_OFFSET)
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+ set_pte(pte, pte_wrprotect(*pte));
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+
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+ *MMUTR = (mmuar & PAGE_MASK) | (asid << CF_ASID_MMU_SHIFT)
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+ | (((int)(pte->pte) & (int)CF_PAGE_MMUTR_MASK ) >> CF_PAGE_MMUTR_SHIFT)
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+ | MMUTR_V;
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+
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+ *MMUDR = (pte_val(*pte) & PAGE_MASK)
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+ | ((pte->pte) & CF_PAGE_MMUDR_MASK)
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+ | MMUDR_SZ8K | MMUDR_X;
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+
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+ if ( dtlb )
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+ *MMUOR = MMUOR_ACC | MMUOR_UAA;
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+ else
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+ *MMUOR = MMUOR_ITLB | MMUOR_ACC | MMUOR_UAA;
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+
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+ asm ("nop");
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+ /*printk("cf_tlb_miss: va=%lx, pa=%lx\n", (mmuar & PAGE_MASK),
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+ (pte_val(*pte) & PAGE_MASK));*/
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+ local_irq_restore(flags);
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+ return (0);
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+}
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+
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+
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+/* The following was taken from arch/ppc/mmu_context.c
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+ *
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+ * Initialize the context management stuff.
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+ */
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+void __init mmu_context_init(void)
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+{
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+ /*
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+ * Some processors have too few contexts to reserve one for
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+ * init_mm, and require using context 0 for a normal task.
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+ * Other processors reserve the use of context zero for the kernel.
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+ * This code assumes FIRST_CONTEXT < 32.
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+ */
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+ context_map[0] = (1 << FIRST_CONTEXT) - 1;
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+ next_mmu_context = FIRST_CONTEXT;
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+ atomic_set(&nr_free_contexts, LAST_CONTEXT - FIRST_CONTEXT + 1);
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+}
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+
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+/*
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+ * Steal a context from a task that has one at the moment.
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+ * This is only used on 8xx and 4xx and we presently assume that
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+ * they don't do SMP. If they do then thicfpgalloc.hs will have to check
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+ * whether the MM we steal is in use.
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+ * We also assume that this is only used on systems that don't
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+ * use an MMU hash table - this is true for 8xx and 4xx.
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+ * This isn't an LRU system, it just frees up each context in
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+ * turn (sort-of pseudo-random replacement :). This would be the
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+ * place to implement an LRU scheme if anyone was motivated to do it.
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+ * -- paulus
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+ */
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+void steal_context(void)
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+{
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+ struct mm_struct *mm;
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+ /* free up context `next_mmu_context' */
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+ /* if we shouldn't free context 0, don't... */
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+ if (next_mmu_context < FIRST_CONTEXT)
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+ next_mmu_context = FIRST_CONTEXT;
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+ mm = context_mm[next_mmu_context];
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+ flush_tlb_mm(mm);
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+ destroy_context(mm);
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+}
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--- a/arch/m68k/mm/hwtest.c
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+++ b/arch/m68k/mm/hwtest.c
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@@ -25,6 +25,7 @@
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#include <linux/module.h>
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+#ifndef CONFIG_COLDFIRE
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int hwreg_present( volatile void *regp )
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{
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int ret = 0;
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@@ -82,4 +83,5 @@ int hwreg_write( volatile void *regp, un
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return( ret );
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}
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EXPORT_SYMBOL(hwreg_write);
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+#endif
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--- a/arch/m68k/mm/init.c
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+++ b/arch/m68k/mm/init.c
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@@ -122,7 +122,6 @@ void __init mem_init(void)
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if (MACH_IS_ATARI)
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atari_stram_mem_init_hook();
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#endif
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-
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/* this will put all memory onto the freelists */
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totalram_pages = num_physpages = 0;
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for_each_online_pgdat(pgdat) {
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@@ -146,7 +145,7 @@ void __init mem_init(void)
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}
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}
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-#ifndef CONFIG_SUN3
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+#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE)
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/* insert pointer tables allocated so far into the tablelist */
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init_pointer_table((unsigned long)kernel_pg_dir);
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for (i = 0; i < PTRS_PER_PGD; i++) {
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--- a/arch/m68k/mm/kmap.c
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+++ b/arch/m68k/mm/kmap.c
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@@ -24,7 +24,11 @@
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#undef DEBUG
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+#ifndef CONFIG_COLDFIRE
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#define PTRTREESIZE (256*1024)
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+#else
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+#define PTRTREESIZE PAGE_SIZE
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+#endif
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/*
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* For 040/060 we can use the virtual memory area like other architectures,
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@@ -50,7 +54,11 @@ static inline void free_io_area(void *ad
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#else
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+#ifdef CONFIG_COLDFIRE
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+#define IO_SIZE PAGE_SIZE
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+#else
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#define IO_SIZE (256*1024)
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+#endif
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static struct vm_struct *iolist;
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@@ -170,7 +178,12 @@ void __iomem *__ioremap(unsigned long ph
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break;
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}
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} else {
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+#ifndef CONFIG_COLDFIRE
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physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY);
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+#else
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+ physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY | \
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+ _PAGE_READWRITE);
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+#endif
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switch (cacheflag) {
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case IOMAP_NOCACHE_SER:
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case IOMAP_NOCACHE_NONSER:
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--- a/arch/m68k/mm/memory.c
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+++ b/arch/m68k/mm/memory.c
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@@ -203,7 +203,38 @@ static inline void pushcl040(unsigned lo
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void cache_clear (unsigned long paddr, int len)
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{
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- if (CPU_IS_040_OR_060) {
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+ if (CPU_IS_CFV4E) {
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+ unsigned long set;
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+ unsigned long start_set;
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+ unsigned long end_set;
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+
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+ start_set = paddr & _ICACHE_SET_MASK;
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+ end_set = (paddr+len-1) & _ICACHE_SET_MASK;
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+
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+ if (start_set > end_set) {
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+ /* from the begining to the lowest address */
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+ for (set = 0; set <= end_set; set += (0x10 - 3))
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+ asm volatile("cpushl %%bc,(%0)\n"
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|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%bc,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%bc,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%bc,(%0)" : : "a" (set));
|
|
+
|
|
+ /* next loop will finish the cache ie pass the hole */
|
|
+ end_set = LAST_ICACHE_ADDR;
|
|
+ }
|
|
+ for (set = start_set; set <= end_set; set += (0x10 - 3))
|
|
+ asm volatile("cpushl %%bc,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%bc,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%bc,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%bc,(%0)" : : "a" (set));
|
|
+
|
|
+ } else if (CPU_IS_040_OR_060) {
|
|
int tmp;
|
|
|
|
/*
|
|
@@ -250,7 +281,38 @@ EXPORT_SYMBOL(cache_clear);
|
|
|
|
void cache_push (unsigned long paddr, int len)
|
|
{
|
|
- if (CPU_IS_040_OR_060) {
|
|
+ if (CPU_IS_CFV4E) {
|
|
+ unsigned long set;
|
|
+ unsigned long start_set;
|
|
+ unsigned long end_set;
|
|
+
|
|
+ start_set = paddr & _ICACHE_SET_MASK;
|
|
+ end_set = (paddr+len-1) & _ICACHE_SET_MASK;
|
|
+
|
|
+ if (start_set > end_set) {
|
|
+ /* from the begining to the lowest address */
|
|
+ for (set = 0; set <= end_set; set += (0x10 - 3))
|
|
+ asm volatile("cpushl %%bc,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%bc,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%bc,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%bc,(%0)" : : "a" (set));
|
|
+
|
|
+ /* next loop will finish the cache ie pass the hole */
|
|
+ end_set = LAST_ICACHE_ADDR;
|
|
+ }
|
|
+ for (set = start_set; set <= end_set; set += (0x10 - 3))
|
|
+ asm volatile("cpushl %%bc,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%bc,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%bc,(%0)\n"
|
|
+ "\taddq%.l #1,%0\n"
|
|
+ "\tcpushl %%bc,(%0)" : : "a" (set));
|
|
+
|
|
+ } else if (CPU_IS_040_OR_060) {
|
|
int tmp = PAGE_SIZE;
|
|
|
|
/*
|