mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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22b99f32a1
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@29867 3c298f89-4303-0410-b956-a3cf2f4a3e73
1266 lines
28 KiB
C
1266 lines
28 KiB
C
/*
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* Atheros AR71xx built-in ethernet mac driver
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*
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* Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* Based on Atheros' AG7100 driver
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include "ag71xx.h"
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#define AG71XX_DEFAULT_MSG_ENABLE \
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(NETIF_MSG_DRV \
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| NETIF_MSG_PROBE \
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| NETIF_MSG_LINK \
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| NETIF_MSG_TIMER \
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| NETIF_MSG_IFDOWN \
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| NETIF_MSG_IFUP \
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| NETIF_MSG_RX_ERR \
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| NETIF_MSG_TX_ERR)
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static int ag71xx_msg_level = -1;
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module_param_named(msg_level, ag71xx_msg_level, int, 0);
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MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
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static void ag71xx_dump_dma_regs(struct ag71xx *ag)
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{
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DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
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ag->dev->name,
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ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
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ag71xx_rr(ag, AG71XX_REG_TX_DESC),
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ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
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DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
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ag->dev->name,
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ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
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ag71xx_rr(ag, AG71XX_REG_RX_DESC),
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ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
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}
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static void ag71xx_dump_regs(struct ag71xx *ag)
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{
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DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
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ag->dev->name,
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ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
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ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
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ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
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ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
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ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
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DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
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ag->dev->name,
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ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
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ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
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ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
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DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
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ag->dev->name,
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ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
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ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
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ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
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DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
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ag->dev->name,
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ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
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ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
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ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
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}
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static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
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{
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DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
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ag->dev->name, label, intr,
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(intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
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(intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
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(intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
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(intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
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(intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
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(intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
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}
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static void ag71xx_ring_free(struct ag71xx_ring *ring)
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{
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kfree(ring->buf);
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if (ring->descs_cpu)
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dma_free_coherent(NULL, ring->size * ring->desc_size,
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ring->descs_cpu, ring->descs_dma);
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}
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static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
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{
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int err;
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int i;
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ring->desc_size = sizeof(struct ag71xx_desc);
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if (ring->desc_size % cache_line_size()) {
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DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
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ring, ring->desc_size,
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roundup(ring->desc_size, cache_line_size()));
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ring->desc_size = roundup(ring->desc_size, cache_line_size());
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}
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ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
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&ring->descs_dma, GFP_ATOMIC);
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if (!ring->descs_cpu) {
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err = -ENOMEM;
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goto err;
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}
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ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
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if (!ring->buf) {
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err = -ENOMEM;
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goto err;
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}
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for (i = 0; i < ring->size; i++) {
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int idx = i * ring->desc_size;
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ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
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DBG("ag71xx: ring %p, desc %d at %p\n",
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ring, i, ring->buf[i].desc);
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}
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return 0;
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err:
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return err;
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}
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static void ag71xx_ring_tx_clean(struct ag71xx *ag)
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{
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struct ag71xx_ring *ring = &ag->tx_ring;
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struct net_device *dev = ag->dev;
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while (ring->curr != ring->dirty) {
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u32 i = ring->dirty % ring->size;
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if (!ag71xx_desc_empty(ring->buf[i].desc)) {
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ring->buf[i].desc->ctrl = 0;
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dev->stats.tx_errors++;
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}
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if (ring->buf[i].skb)
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dev_kfree_skb_any(ring->buf[i].skb);
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ring->buf[i].skb = NULL;
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ring->dirty++;
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}
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/* flush descriptors */
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wmb();
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}
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static void ag71xx_ring_tx_init(struct ag71xx *ag)
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{
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struct ag71xx_ring *ring = &ag->tx_ring;
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int i;
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for (i = 0; i < ring->size; i++) {
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ring->buf[i].desc->next = (u32) (ring->descs_dma +
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ring->desc_size * ((i + 1) % ring->size));
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ring->buf[i].desc->ctrl = DESC_EMPTY;
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ring->buf[i].skb = NULL;
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}
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/* flush descriptors */
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wmb();
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ring->curr = 0;
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ring->dirty = 0;
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}
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static void ag71xx_ring_rx_clean(struct ag71xx *ag)
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{
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struct ag71xx_ring *ring = &ag->rx_ring;
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int i;
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if (!ring->buf)
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return;
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for (i = 0; i < ring->size; i++)
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if (ring->buf[i].skb) {
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dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
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AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
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kfree_skb(ring->buf[i].skb);
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}
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}
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static int ag71xx_rx_reserve(struct ag71xx *ag)
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{
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int reserve = 0;
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if (ag71xx_get_pdata(ag)->is_ar724x) {
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if (!ag71xx_has_ar8216(ag))
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reserve = 2;
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if (ag->phy_dev)
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reserve += 4 - (ag->phy_dev->pkt_align % 4);
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reserve %= 4;
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}
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return reserve + AG71XX_RX_PKT_RESERVE;
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}
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static int ag71xx_ring_rx_init(struct ag71xx *ag)
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{
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struct ag71xx_ring *ring = &ag->rx_ring;
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unsigned int reserve = ag71xx_rx_reserve(ag);
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unsigned int i;
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int ret;
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ret = 0;
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for (i = 0; i < ring->size; i++) {
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ring->buf[i].desc->next = (u32) (ring->descs_dma +
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ring->desc_size * ((i + 1) % ring->size));
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DBG("ag71xx: RX desc at %p, next is %08x\n",
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ring->buf[i].desc,
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ring->buf[i].desc->next);
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}
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for (i = 0; i < ring->size; i++) {
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struct sk_buff *skb;
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dma_addr_t dma_addr;
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skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
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if (!skb) {
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ret = -ENOMEM;
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break;
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}
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skb->dev = ag->dev;
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skb_reserve(skb, reserve);
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dma_addr = dma_map_single(&ag->dev->dev, skb->data,
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AG71XX_RX_PKT_SIZE,
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DMA_FROM_DEVICE);
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ring->buf[i].skb = skb;
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ring->buf[i].dma_addr = dma_addr;
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ring->buf[i].desc->data = (u32) dma_addr;
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ring->buf[i].desc->ctrl = DESC_EMPTY;
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}
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/* flush descriptors */
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wmb();
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ring->curr = 0;
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ring->dirty = 0;
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return ret;
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}
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static int ag71xx_ring_rx_refill(struct ag71xx *ag)
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{
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struct ag71xx_ring *ring = &ag->rx_ring;
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unsigned int reserve = ag71xx_rx_reserve(ag);
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unsigned int count;
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count = 0;
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for (; ring->curr - ring->dirty > 0; ring->dirty++) {
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unsigned int i;
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i = ring->dirty % ring->size;
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if (ring->buf[i].skb == NULL) {
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dma_addr_t dma_addr;
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struct sk_buff *skb;
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skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
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if (skb == NULL)
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break;
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skb_reserve(skb, reserve);
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skb->dev = ag->dev;
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dma_addr = dma_map_single(&ag->dev->dev, skb->data,
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AG71XX_RX_PKT_SIZE,
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DMA_FROM_DEVICE);
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ring->buf[i].skb = skb;
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ring->buf[i].dma_addr = dma_addr;
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ring->buf[i].desc->data = (u32) dma_addr;
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}
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ring->buf[i].desc->ctrl = DESC_EMPTY;
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count++;
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}
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/* flush descriptors */
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wmb();
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DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
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return count;
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}
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static int ag71xx_rings_init(struct ag71xx *ag)
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{
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int ret;
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ret = ag71xx_ring_alloc(&ag->tx_ring);
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if (ret)
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return ret;
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ag71xx_ring_tx_init(ag);
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ret = ag71xx_ring_alloc(&ag->rx_ring);
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if (ret)
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return ret;
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ret = ag71xx_ring_rx_init(ag);
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return ret;
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}
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static void ag71xx_rings_cleanup(struct ag71xx *ag)
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{
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ag71xx_ring_rx_clean(ag);
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ag71xx_ring_free(&ag->rx_ring);
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ag71xx_ring_tx_clean(ag);
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ag71xx_ring_free(&ag->tx_ring);
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}
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static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
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{
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switch (ag->speed) {
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case SPEED_1000:
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return "1000";
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case SPEED_100:
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return "100";
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case SPEED_10:
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return "10";
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}
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return "?";
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}
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static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
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{
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u32 t;
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t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
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| (((u32) mac[3]) << 8) | ((u32) mac[2]);
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ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
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t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
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ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
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}
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static void ag71xx_dma_reset(struct ag71xx *ag)
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{
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u32 val;
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int i;
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ag71xx_dump_dma_regs(ag);
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/* stop RX and TX */
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ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
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ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
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/*
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* give the hardware some time to really stop all rx/tx activity
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* clearing the descriptors too early causes random memory corruption
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*/
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mdelay(1);
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/* clear descriptor addresses */
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ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
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ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
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/* clear pending RX/TX interrupts */
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for (i = 0; i < 256; i++) {
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ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
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ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
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}
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/* clear pending errors */
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ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
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ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
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val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
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if (val)
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printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
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ag->dev->name, val);
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val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
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/* mask out reserved bits */
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val &= ~0xff000000;
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if (val)
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printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
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ag->dev->name, val);
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ag71xx_dump_dma_regs(ag);
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}
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#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
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MAC_CFG1_SRX | MAC_CFG1_STX)
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#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
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#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
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FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
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FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
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FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
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FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
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FIFO_CFG4_VT)
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#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
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FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
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FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
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FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
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FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
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FIFO_CFG5_17 | FIFO_CFG5_SF)
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static void ag71xx_hw_stop(struct ag71xx *ag)
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{
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/* disable all interrupts and stop the rx/tx engine */
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ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
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ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
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ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
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}
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static void ag71xx_hw_setup(struct ag71xx *ag)
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{
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struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
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|
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/* setup MAC configuration registers */
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ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
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ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
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MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
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|
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/* setup max frame length */
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ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
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|
|
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/* setup FIFO configuration registers */
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
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if (pdata->is_ar724x) {
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
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} else {
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
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}
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
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ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
|
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}
|
|
|
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static void ag71xx_hw_init(struct ag71xx *ag)
|
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{
|
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struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
|
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u32 reset_mask = pdata->reset_bit;
|
|
|
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ag71xx_hw_stop(ag);
|
|
|
|
if (pdata->is_ar724x) {
|
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u32 reset_phy = reset_mask;
|
|
|
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reset_phy &= RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY;
|
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reset_mask &= ~(RESET_MODULE_GE0_PHY | RESET_MODULE_GE1_PHY);
|
|
|
|
ar71xx_device_stop(reset_phy);
|
|
mdelay(50);
|
|
ar71xx_device_start(reset_phy);
|
|
mdelay(200);
|
|
}
|
|
|
|
ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
|
|
udelay(20);
|
|
|
|
ar71xx_device_stop(reset_mask);
|
|
mdelay(100);
|
|
ar71xx_device_start(reset_mask);
|
|
mdelay(200);
|
|
|
|
ag71xx_hw_setup(ag);
|
|
|
|
ag71xx_dma_reset(ag);
|
|
}
|
|
|
|
static void ag71xx_fast_reset(struct ag71xx *ag)
|
|
{
|
|
struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
|
|
struct net_device *dev = ag->dev;
|
|
u32 reset_mask = pdata->reset_bit;
|
|
u32 rx_ds, tx_ds;
|
|
u32 mii_reg;
|
|
|
|
reset_mask &= RESET_MODULE_GE0_MAC | RESET_MODULE_GE1_MAC;
|
|
|
|
mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
|
|
rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
|
|
tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
|
|
|
|
ar71xx_device_stop(reset_mask);
|
|
udelay(10);
|
|
ar71xx_device_start(reset_mask);
|
|
udelay(10);
|
|
|
|
ag71xx_dma_reset(ag);
|
|
ag71xx_hw_setup(ag);
|
|
|
|
ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
|
|
ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
|
|
ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
|
|
|
|
ag71xx_hw_set_macaddr(ag, dev->dev_addr);
|
|
}
|
|
|
|
static void ag71xx_hw_start(struct ag71xx *ag)
|
|
{
|
|
/* start RX engine */
|
|
ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
|
|
|
|
/* enable interrupts */
|
|
ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
|
|
}
|
|
|
|
void ag71xx_link_adjust(struct ag71xx *ag)
|
|
{
|
|
struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
|
|
u32 cfg2;
|
|
u32 ifctl;
|
|
u32 fifo5;
|
|
|
|
if (!ag->link) {
|
|
ag71xx_hw_stop(ag);
|
|
netif_carrier_off(ag->dev);
|
|
if (netif_msg_link(ag))
|
|
printk(KERN_INFO "%s: link down\n", ag->dev->name);
|
|
return;
|
|
}
|
|
|
|
if (pdata->is_ar724x)
|
|
ag71xx_fast_reset(ag);
|
|
|
|
cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
|
|
cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
|
|
cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
|
|
|
|
ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
|
|
ifctl &= ~(MAC_IFCTL_SPEED);
|
|
|
|
fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
|
|
fifo5 &= ~FIFO_CFG5_BM;
|
|
|
|
switch (ag->speed) {
|
|
case SPEED_1000:
|
|
cfg2 |= MAC_CFG2_IF_1000;
|
|
fifo5 |= FIFO_CFG5_BM;
|
|
break;
|
|
case SPEED_100:
|
|
cfg2 |= MAC_CFG2_IF_10_100;
|
|
ifctl |= MAC_IFCTL_SPEED;
|
|
break;
|
|
case SPEED_10:
|
|
cfg2 |= MAC_CFG2_IF_10_100;
|
|
break;
|
|
default:
|
|
BUG();
|
|
return;
|
|
}
|
|
|
|
if (pdata->is_ar91xx)
|
|
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
|
|
else if (pdata->is_ar724x)
|
|
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
|
|
else
|
|
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
|
|
|
|
if (pdata->set_speed)
|
|
pdata->set_speed(ag->speed);
|
|
|
|
ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
|
|
ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
|
|
ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
|
|
ag71xx_hw_start(ag);
|
|
|
|
netif_carrier_on(ag->dev);
|
|
if (netif_msg_link(ag))
|
|
printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
|
|
ag->dev->name,
|
|
ag71xx_speed_str(ag),
|
|
(DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
|
|
|
|
DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
|
|
ag->dev->name,
|
|
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
|
|
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
|
|
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
|
|
|
|
DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
|
|
ag->dev->name,
|
|
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
|
|
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
|
|
ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
|
|
|
|
DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
|
|
ag->dev->name,
|
|
ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
|
|
ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
|
|
ag71xx_mii_ctrl_rr(ag));
|
|
}
|
|
|
|
static int ag71xx_open(struct net_device *dev)
|
|
{
|
|
struct ag71xx *ag = netdev_priv(dev);
|
|
int ret;
|
|
|
|
ret = ag71xx_rings_init(ag);
|
|
if (ret)
|
|
goto err;
|
|
|
|
napi_enable(&ag->napi);
|
|
|
|
netif_carrier_off(dev);
|
|
ag71xx_phy_start(ag);
|
|
|
|
ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
|
|
ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
|
|
|
|
ag71xx_hw_set_macaddr(ag, dev->dev_addr);
|
|
|
|
netif_start_queue(dev);
|
|
|
|
return 0;
|
|
|
|
err:
|
|
ag71xx_rings_cleanup(ag);
|
|
return ret;
|
|
}
|
|
|
|
static int ag71xx_stop(struct net_device *dev)
|
|
{
|
|
struct ag71xx *ag = netdev_priv(dev);
|
|
unsigned long flags;
|
|
|
|
netif_carrier_off(dev);
|
|
ag71xx_phy_stop(ag);
|
|
|
|
spin_lock_irqsave(&ag->lock, flags);
|
|
|
|
netif_stop_queue(dev);
|
|
|
|
ag71xx_hw_stop(ag);
|
|
ag71xx_dma_reset(ag);
|
|
|
|
napi_disable(&ag->napi);
|
|
del_timer_sync(&ag->oom_timer);
|
|
|
|
spin_unlock_irqrestore(&ag->lock, flags);
|
|
|
|
ag71xx_rings_cleanup(ag);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
|
|
struct net_device *dev)
|
|
{
|
|
struct ag71xx *ag = netdev_priv(dev);
|
|
struct ag71xx_ring *ring = &ag->tx_ring;
|
|
struct ag71xx_desc *desc;
|
|
dma_addr_t dma_addr;
|
|
int i;
|
|
|
|
i = ring->curr % ring->size;
|
|
desc = ring->buf[i].desc;
|
|
|
|
if (!ag71xx_desc_empty(desc))
|
|
goto err_drop;
|
|
|
|
if (ag71xx_has_ar8216(ag))
|
|
ag71xx_add_ar8216_header(ag, skb);
|
|
|
|
if (skb->len <= 0) {
|
|
DBG("%s: packet len is too small\n", ag->dev->name);
|
|
goto err_drop;
|
|
}
|
|
|
|
dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
|
|
DMA_TO_DEVICE);
|
|
|
|
ring->buf[i].skb = skb;
|
|
ring->buf[i].timestamp = jiffies;
|
|
|
|
/* setup descriptor fields */
|
|
desc->data = (u32) dma_addr;
|
|
desc->ctrl = (skb->len & DESC_PKTLEN_M);
|
|
|
|
/* flush descriptor */
|
|
wmb();
|
|
|
|
ring->curr++;
|
|
if (ring->curr == (ring->dirty + ring->size)) {
|
|
DBG("%s: tx queue full\n", ag->dev->name);
|
|
netif_stop_queue(dev);
|
|
}
|
|
|
|
DBG("%s: packet injected into TX queue\n", ag->dev->name);
|
|
|
|
/* enable TX engine */
|
|
ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
|
|
|
|
return NETDEV_TX_OK;
|
|
|
|
err_drop:
|
|
dev->stats.tx_dropped++;
|
|
|
|
dev_kfree_skb(skb);
|
|
return NETDEV_TX_OK;
|
|
}
|
|
|
|
static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
|
|
{
|
|
struct ag71xx *ag = netdev_priv(dev);
|
|
int ret;
|
|
|
|
switch (cmd) {
|
|
case SIOCETHTOOL:
|
|
if (ag->phy_dev == NULL)
|
|
break;
|
|
|
|
spin_lock_irq(&ag->lock);
|
|
ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
|
|
spin_unlock_irq(&ag->lock);
|
|
return ret;
|
|
|
|
case SIOCSIFHWADDR:
|
|
if (copy_from_user
|
|
(dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
|
|
return -EFAULT;
|
|
return 0;
|
|
|
|
case SIOCGIFHWADDR:
|
|
if (copy_to_user
|
|
(ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
|
|
return -EFAULT;
|
|
return 0;
|
|
|
|
case SIOCGMIIPHY:
|
|
case SIOCGMIIREG:
|
|
case SIOCSMIIREG:
|
|
if (ag->phy_dev == NULL)
|
|
break;
|
|
|
|
return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
static void ag71xx_oom_timer_handler(unsigned long data)
|
|
{
|
|
struct net_device *dev = (struct net_device *) data;
|
|
struct ag71xx *ag = netdev_priv(dev);
|
|
|
|
napi_schedule(&ag->napi);
|
|
}
|
|
|
|
static void ag71xx_tx_timeout(struct net_device *dev)
|
|
{
|
|
struct ag71xx *ag = netdev_priv(dev);
|
|
|
|
if (netif_msg_tx_err(ag))
|
|
printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
|
|
|
|
schedule_work(&ag->restart_work);
|
|
}
|
|
|
|
static void ag71xx_restart_work_func(struct work_struct *work)
|
|
{
|
|
struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
|
|
|
|
if (ag71xx_get_pdata(ag)->is_ar724x) {
|
|
ag->link = 0;
|
|
ag71xx_link_adjust(ag);
|
|
return;
|
|
}
|
|
|
|
ag71xx_stop(ag->dev);
|
|
ag71xx_open(ag->dev);
|
|
}
|
|
|
|
static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
|
|
{
|
|
u32 rx_sm, tx_sm, rx_fd;
|
|
|
|
if (likely(time_before(jiffies, timestamp + HZ/10)))
|
|
return false;
|
|
|
|
if (!netif_carrier_ok(ag->dev))
|
|
return false;
|
|
|
|
rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
|
|
if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
|
|
return true;
|
|
|
|
tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
|
|
rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
|
|
if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
|
|
((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
static int ag71xx_tx_packets(struct ag71xx *ag)
|
|
{
|
|
struct ag71xx_ring *ring = &ag->tx_ring;
|
|
struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
|
|
int sent;
|
|
|
|
DBG("%s: processing TX ring\n", ag->dev->name);
|
|
|
|
sent = 0;
|
|
while (ring->dirty != ring->curr) {
|
|
unsigned int i = ring->dirty % ring->size;
|
|
struct ag71xx_desc *desc = ring->buf[i].desc;
|
|
struct sk_buff *skb = ring->buf[i].skb;
|
|
|
|
if (!ag71xx_desc_empty(desc)) {
|
|
if (pdata->is_ar7240 &&
|
|
ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
|
|
schedule_work(&ag->restart_work);
|
|
break;
|
|
}
|
|
|
|
ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
|
|
|
|
ag->dev->stats.tx_bytes += skb->len;
|
|
ag->dev->stats.tx_packets++;
|
|
|
|
dev_kfree_skb_any(skb);
|
|
ring->buf[i].skb = NULL;
|
|
|
|
ring->dirty++;
|
|
sent++;
|
|
}
|
|
|
|
DBG("%s: %d packets sent out\n", ag->dev->name, sent);
|
|
|
|
if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
|
|
netif_wake_queue(ag->dev);
|
|
|
|
return sent;
|
|
}
|
|
|
|
static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
|
|
{
|
|
struct net_device *dev = ag->dev;
|
|
struct ag71xx_ring *ring = &ag->rx_ring;
|
|
int done = 0;
|
|
|
|
DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
|
|
dev->name, limit, ring->curr, ring->dirty);
|
|
|
|
while (done < limit) {
|
|
unsigned int i = ring->curr % ring->size;
|
|
struct ag71xx_desc *desc = ring->buf[i].desc;
|
|
struct sk_buff *skb;
|
|
int pktlen;
|
|
int err = 0;
|
|
|
|
if (ag71xx_desc_empty(desc))
|
|
break;
|
|
|
|
if ((ring->dirty + ring->size) == ring->curr) {
|
|
ag71xx_assert(0);
|
|
break;
|
|
}
|
|
|
|
ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
|
|
|
|
skb = ring->buf[i].skb;
|
|
pktlen = ag71xx_desc_pktlen(desc);
|
|
pktlen -= ETH_FCS_LEN;
|
|
|
|
dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
|
|
AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
|
|
|
|
dev->last_rx = jiffies;
|
|
dev->stats.rx_packets++;
|
|
dev->stats.rx_bytes += pktlen;
|
|
|
|
skb_put(skb, pktlen);
|
|
if (ag71xx_has_ar8216(ag))
|
|
err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
|
|
|
|
if (err) {
|
|
dev->stats.rx_dropped++;
|
|
kfree_skb(skb);
|
|
} else {
|
|
skb->dev = dev;
|
|
skb->ip_summed = CHECKSUM_NONE;
|
|
if (ag->phy_dev) {
|
|
ag->phy_dev->netif_receive_skb(skb);
|
|
} else {
|
|
skb->protocol = eth_type_trans(skb, dev);
|
|
netif_receive_skb(skb);
|
|
}
|
|
}
|
|
|
|
ring->buf[i].skb = NULL;
|
|
done++;
|
|
|
|
ring->curr++;
|
|
}
|
|
|
|
ag71xx_ring_rx_refill(ag);
|
|
|
|
DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
|
|
dev->name, ring->curr, ring->dirty, done);
|
|
|
|
return done;
|
|
}
|
|
|
|
static int ag71xx_poll(struct napi_struct *napi, int limit)
|
|
{
|
|
struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
|
|
struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
|
|
struct net_device *dev = ag->dev;
|
|
struct ag71xx_ring *rx_ring;
|
|
unsigned long flags;
|
|
u32 status;
|
|
int tx_done;
|
|
int rx_done;
|
|
|
|
pdata->ddr_flush();
|
|
tx_done = ag71xx_tx_packets(ag);
|
|
|
|
DBG("%s: processing RX ring\n", dev->name);
|
|
rx_done = ag71xx_rx_packets(ag, limit);
|
|
|
|
ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
|
|
|
|
rx_ring = &ag->rx_ring;
|
|
if (rx_ring->buf[rx_ring->dirty % rx_ring->size].skb == NULL)
|
|
goto oom;
|
|
|
|
status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
|
|
if (unlikely(status & RX_STATUS_OF)) {
|
|
ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
|
|
dev->stats.rx_fifo_errors++;
|
|
|
|
/* restart RX */
|
|
ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
|
|
}
|
|
|
|
if (rx_done < limit) {
|
|
if (status & RX_STATUS_PR)
|
|
goto more;
|
|
|
|
status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
|
|
if (status & TX_STATUS_PS)
|
|
goto more;
|
|
|
|
DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
|
|
dev->name, rx_done, tx_done, limit);
|
|
|
|
napi_complete(napi);
|
|
|
|
/* enable interrupts */
|
|
spin_lock_irqsave(&ag->lock, flags);
|
|
ag71xx_int_enable(ag, AG71XX_INT_POLL);
|
|
spin_unlock_irqrestore(&ag->lock, flags);
|
|
return rx_done;
|
|
}
|
|
|
|
more:
|
|
DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
|
|
dev->name, rx_done, tx_done, limit);
|
|
return rx_done;
|
|
|
|
oom:
|
|
if (netif_msg_rx_err(ag))
|
|
printk(KERN_DEBUG "%s: out of memory\n", dev->name);
|
|
|
|
mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
|
|
napi_complete(napi);
|
|
return 0;
|
|
}
|
|
|
|
static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
|
|
{
|
|
struct net_device *dev = dev_id;
|
|
struct ag71xx *ag = netdev_priv(dev);
|
|
u32 status;
|
|
|
|
status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
|
|
ag71xx_dump_intr(ag, "raw", status);
|
|
|
|
if (unlikely(!status))
|
|
return IRQ_NONE;
|
|
|
|
if (unlikely(status & AG71XX_INT_ERR)) {
|
|
if (status & AG71XX_INT_TX_BE) {
|
|
ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
|
|
dev_err(&dev->dev, "TX BUS error\n");
|
|
}
|
|
if (status & AG71XX_INT_RX_BE) {
|
|
ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
|
|
dev_err(&dev->dev, "RX BUS error\n");
|
|
}
|
|
}
|
|
|
|
if (likely(status & AG71XX_INT_POLL)) {
|
|
ag71xx_int_disable(ag, AG71XX_INT_POLL);
|
|
DBG("%s: enable polling mode\n", dev->name);
|
|
napi_schedule(&ag->napi);
|
|
}
|
|
|
|
ag71xx_debugfs_update_int_stats(ag, status);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void ag71xx_set_multicast_list(struct net_device *dev)
|
|
{
|
|
/* TODO */
|
|
}
|
|
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
/*
|
|
* Polling 'interrupt' - used by things like netconsole to send skbs
|
|
* without having to re-enable interrupts. It's not called while
|
|
* the interrupt routine is executing.
|
|
*/
|
|
static void ag71xx_netpoll(struct net_device *dev)
|
|
{
|
|
disable_irq(dev->irq);
|
|
ag71xx_interrupt(dev->irq, dev);
|
|
enable_irq(dev->irq);
|
|
}
|
|
#endif
|
|
|
|
static const struct net_device_ops ag71xx_netdev_ops = {
|
|
.ndo_open = ag71xx_open,
|
|
.ndo_stop = ag71xx_stop,
|
|
.ndo_start_xmit = ag71xx_hard_start_xmit,
|
|
.ndo_set_multicast_list = ag71xx_set_multicast_list,
|
|
.ndo_do_ioctl = ag71xx_do_ioctl,
|
|
.ndo_tx_timeout = ag71xx_tx_timeout,
|
|
.ndo_change_mtu = eth_change_mtu,
|
|
.ndo_set_mac_address = eth_mac_addr,
|
|
.ndo_validate_addr = eth_validate_addr,
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
.ndo_poll_controller = ag71xx_netpoll,
|
|
#endif
|
|
};
|
|
|
|
static int __devinit ag71xx_probe(struct platform_device *pdev)
|
|
{
|
|
struct net_device *dev;
|
|
struct resource *res;
|
|
struct ag71xx *ag;
|
|
struct ag71xx_platform_data *pdata;
|
|
int err;
|
|
|
|
pdata = pdev->dev.platform_data;
|
|
if (!pdata) {
|
|
dev_err(&pdev->dev, "no platform data specified\n");
|
|
err = -ENXIO;
|
|
goto err_out;
|
|
}
|
|
|
|
if (pdata->mii_bus_dev == NULL) {
|
|
dev_err(&pdev->dev, "no MII bus device specified\n");
|
|
err = -EINVAL;
|
|
goto err_out;
|
|
}
|
|
|
|
dev = alloc_etherdev(sizeof(*ag));
|
|
if (!dev) {
|
|
dev_err(&pdev->dev, "alloc_etherdev failed\n");
|
|
err = -ENOMEM;
|
|
goto err_out;
|
|
}
|
|
|
|
SET_NETDEV_DEV(dev, &pdev->dev);
|
|
|
|
ag = netdev_priv(dev);
|
|
ag->pdev = pdev;
|
|
ag->dev = dev;
|
|
ag->msg_enable = netif_msg_init(ag71xx_msg_level,
|
|
AG71XX_DEFAULT_MSG_ENABLE);
|
|
spin_lock_init(&ag->lock);
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "no mac_base resource found\n");
|
|
err = -ENXIO;
|
|
goto err_out;
|
|
}
|
|
|
|
ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
|
|
if (!ag->mac_base) {
|
|
dev_err(&pdev->dev, "unable to ioremap mac_base\n");
|
|
err = -ENOMEM;
|
|
goto err_free_dev;
|
|
}
|
|
|
|
dev->irq = platform_get_irq(pdev, 0);
|
|
err = request_irq(dev->irq, ag71xx_interrupt,
|
|
IRQF_DISABLED,
|
|
dev->name, dev);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
|
|
goto err_unmap_base;
|
|
}
|
|
|
|
dev->base_addr = (unsigned long)ag->mac_base;
|
|
dev->netdev_ops = &ag71xx_netdev_ops;
|
|
dev->ethtool_ops = &ag71xx_ethtool_ops;
|
|
|
|
INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
|
|
|
|
init_timer(&ag->oom_timer);
|
|
ag->oom_timer.data = (unsigned long) dev;
|
|
ag->oom_timer.function = ag71xx_oom_timer_handler;
|
|
|
|
ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
|
|
ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
|
|
|
|
ag->stop_desc = dma_alloc_coherent(NULL,
|
|
sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
|
|
|
|
if (!ag->stop_desc)
|
|
goto err_free_irq;
|
|
|
|
ag->stop_desc->data = 0;
|
|
ag->stop_desc->ctrl = 0;
|
|
ag->stop_desc->next = (u32) ag->stop_desc_dma;
|
|
|
|
memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
|
|
|
|
netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
|
|
|
|
err = register_netdev(dev);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "unable to register net device\n");
|
|
goto err_free_desc;
|
|
}
|
|
|
|
printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
|
|
dev->name, dev->base_addr, dev->irq);
|
|
|
|
ag71xx_dump_regs(ag);
|
|
|
|
ag71xx_hw_init(ag);
|
|
|
|
ag71xx_dump_regs(ag);
|
|
|
|
err = ag71xx_phy_connect(ag);
|
|
if (err)
|
|
goto err_unregister_netdev;
|
|
|
|
err = ag71xx_debugfs_init(ag);
|
|
if (err)
|
|
goto err_phy_disconnect;
|
|
|
|
platform_set_drvdata(pdev, dev);
|
|
|
|
return 0;
|
|
|
|
err_phy_disconnect:
|
|
ag71xx_phy_disconnect(ag);
|
|
err_unregister_netdev:
|
|
unregister_netdev(dev);
|
|
err_free_desc:
|
|
dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
|
|
ag->stop_desc_dma);
|
|
err_free_irq:
|
|
free_irq(dev->irq, dev);
|
|
err_unmap_base:
|
|
iounmap(ag->mac_base);
|
|
err_free_dev:
|
|
kfree(dev);
|
|
err_out:
|
|
platform_set_drvdata(pdev, NULL);
|
|
return err;
|
|
}
|
|
|
|
static int __devexit ag71xx_remove(struct platform_device *pdev)
|
|
{
|
|
struct net_device *dev = platform_get_drvdata(pdev);
|
|
|
|
if (dev) {
|
|
struct ag71xx *ag = netdev_priv(dev);
|
|
|
|
ag71xx_debugfs_exit(ag);
|
|
ag71xx_phy_disconnect(ag);
|
|
unregister_netdev(dev);
|
|
free_irq(dev->irq, dev);
|
|
iounmap(ag->mac_base);
|
|
kfree(dev);
|
|
platform_set_drvdata(pdev, NULL);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver ag71xx_driver = {
|
|
.probe = ag71xx_probe,
|
|
.remove = __exit_p(ag71xx_remove),
|
|
.driver = {
|
|
.name = AG71XX_DRV_NAME,
|
|
}
|
|
};
|
|
|
|
static int __init ag71xx_module_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = ag71xx_debugfs_root_init();
|
|
if (ret)
|
|
goto err_out;
|
|
|
|
ret = ag71xx_mdio_driver_init();
|
|
if (ret)
|
|
goto err_debugfs_exit;
|
|
|
|
ret = platform_driver_register(&ag71xx_driver);
|
|
if (ret)
|
|
goto err_mdio_exit;
|
|
|
|
return 0;
|
|
|
|
err_mdio_exit:
|
|
ag71xx_mdio_driver_exit();
|
|
err_debugfs_exit:
|
|
ag71xx_debugfs_root_exit();
|
|
err_out:
|
|
return ret;
|
|
}
|
|
|
|
static void __exit ag71xx_module_exit(void)
|
|
{
|
|
platform_driver_unregister(&ag71xx_driver);
|
|
ag71xx_mdio_driver_exit();
|
|
ag71xx_debugfs_root_exit();
|
|
}
|
|
|
|
module_init(ag71xx_module_init);
|
|
module_exit(ag71xx_module_exit);
|
|
|
|
MODULE_VERSION(AG71XX_DRV_VERSION);
|
|
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
|
|
MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
|