mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
synced 2024-11-25 07:18:06 +02:00
e3ad321217
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@21736 3c298f89-4303-0410-b956-a3cf2f4a3e73
509 lines
12 KiB
C
509 lines
12 KiB
C
/*
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* NAND flash driver for the MikroTik RouterBoard 4xx series
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*
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* Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
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*
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* This file was based on the driver for Linux 2.6.22 published by
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* MikroTik for their RouterBoard 4xx series devices.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <asm/mach-ar71xx/ar71xx.h>
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#define DRV_NAME "rb4xx-nand"
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#define DRV_VERSION "0.1.10"
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#define DRV_DESC "NAND flash driver for RouterBoard 4xx series"
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#define USE_FAST_READ 1
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#define USE_FAST_WRITE 1
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#undef RB4XX_NAND_DEBUG
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#ifdef RB4XX_NAND_DEBUG
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#define DBG(fmt, arg...) printk(KERN_DEBUG DRV_NAME ": " fmt, ## arg)
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#else
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#define DBG(fmt, arg...) do {} while (0)
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#endif
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#define RB4XX_NAND_GPIO_RDY 5
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#define RB4XX_FLASH_HZ 33333334
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#define RB4XX_NAND_HZ 33333334
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#define SPI_CTRL_FASTEST 0x40
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#define SPI_CTRL_SAFE 0x43 /* 25 MHz for AHB 200 MHz */
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#define SBIT_IOC_BASE SPI_IOC_CS1
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#define SBIT_IOC_DO_SHIFT 0
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#define SBIT_IOC_DO (1u << SBIT_IOC_DO_SHIFT)
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#define SBIT_IOC_DO2_SHIFT 18
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#define SBIT_IOC_DO2 (1u << SBIT_IOC_DO2_SHIFT)
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#define CPLD_CMD_WRITE_MULT 0x08 /* send cmd, n x send data, read data */
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#define CPLD_CMD_WRITE_CFG 0x09 /* send cmd, n x send cfg */
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#define CPLD_CMD_READ_MULT 0x0a /* send cmd, send idle, n x read data */
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#define CPLD_CMD_READ_FAST 0x0b /* send cmd, 4 x idle, n x read data */
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#define CFG_BIT_nCE 0x80
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#define CFG_BIT_CLE 0x40
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#define CFG_BIT_ALE 0x20
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#define CFG_BIT_FAN 0x10
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#define CFG_BIT_nLED4 0x08
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#define CFG_BIT_nLED3 0x04
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#define CFG_BIT_nLED2 0x02
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#define CFG_BIT_nLED1 0x01
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#define CFG_BIT_nLEDS \
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(CFG_BIT_nLED1 | CFG_BIT_nLED2 | CFG_BIT_nLED3 | CFG_BIT_nLED4)
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struct rb4xx_nand_info {
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struct nand_chip chip;
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struct mtd_info mtd;
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};
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/*
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* We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
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* will not be able to find the kernel that we load.
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*/
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static struct nand_ecclayout rb4xx_nand_ecclayout = {
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.eccbytes = 6,
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.eccpos = { 8, 9, 10, 13, 14, 15 },
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.oobavail = 9,
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.oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
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};
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static struct mtd_partition rb4xx_nand_partitions[] = {
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{
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.name = "booter",
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.offset = 0,
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.size = (256 * 1024),
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.mask_flags = MTD_WRITEABLE,
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},
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{
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.name = "kernel",
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.offset = (256 * 1024),
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.size = (4 * 1024 * 1024) - (256 * 1024),
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},
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{
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.name = "rootfs",
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.offset = MTDPART_OFS_NXTBLK,
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.size = MTDPART_SIZ_FULL,
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},
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};
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#if USE_FAST_READ
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#define SPI_NDATA_BASE 0x00800000
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static unsigned spi_ctrl_fread = SPI_CTRL_SAFE;
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static unsigned spi_ctrl_flash = SPI_CTRL_SAFE;
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extern unsigned mips_hpt_frequency;
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#endif
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static inline unsigned rb4xx_spi_rreg(unsigned r)
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{
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return __raw_readl((void * __iomem)(KSEG1ADDR(AR71XX_SPI_BASE) + r));
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}
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static inline void rb4xx_spi_wreg(unsigned r, unsigned v)
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{
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__raw_writel(v, (void * __iomem)(KSEG1ADDR(AR71XX_SPI_BASE) + r));
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}
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static inline void do_spi_clk(int bit)
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{
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unsigned bval = SBIT_IOC_BASE | (bit & 1);
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rb4xx_spi_wreg(SPI_REG_IOC, bval);
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rb4xx_spi_wreg(SPI_REG_IOC, bval | SPI_IOC_CLK);
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}
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static void do_spi_byte(uint8_t byte)
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{
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do_spi_clk(byte >> 7);
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do_spi_clk(byte >> 6);
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do_spi_clk(byte >> 5);
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do_spi_clk(byte >> 4);
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do_spi_clk(byte >> 3);
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do_spi_clk(byte >> 2);
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do_spi_clk(byte >> 1);
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do_spi_clk(byte);
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DBG("spi_byte sent 0x%02x got 0x%x\n",
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byte, rb4xx_spi_rreg(SPI_REG_RDS));
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}
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#if USE_FAST_WRITE
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static inline void do_spi_clk_fast(int bit1, int bit2)
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{
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unsigned bval = (SBIT_IOC_BASE |
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((bit1 << SBIT_IOC_DO_SHIFT) & SBIT_IOC_DO) |
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((bit2 << SBIT_IOC_DO2_SHIFT) & SBIT_IOC_DO2));
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rb4xx_spi_wreg(SPI_REG_IOC, bval);
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rb4xx_spi_wreg(SPI_REG_IOC, bval | SPI_IOC_CLK);
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}
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static inline void do_spi_byte_fast(uint8_t byte)
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{
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do_spi_clk_fast(byte >> 7, byte >> 6);
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do_spi_clk_fast(byte >> 5, byte >> 4);
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do_spi_clk_fast(byte >> 3, byte >> 2);
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do_spi_clk_fast(byte >> 1, byte >> 0);
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DBG("spi_byte_fast sent 0x%02x got 0x%x\n",
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byte, rb4xx_spi_rreg(SPI_REG_RDS));
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}
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#else
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static inline void do_spi_byte_fast(uint8_t byte)
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{
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do_spi_byte(byte);
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}
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#endif /* USE_FAST_WRITE */
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static int do_spi_cmd(unsigned cmd, unsigned sendCnt, const uint8_t *sendData,
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unsigned recvCnt, uint8_t *recvData,
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const uint8_t *verifyData, int fastWrite)
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{
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unsigned i;
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DBG("SPI cmd 0x%x send %u recv %u\n", cmd, sendCnt, recvCnt);
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rb4xx_spi_wreg(SPI_REG_FS, SPI_FS_GPIO);
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rb4xx_spi_wreg(SPI_REG_CTRL, SPI_CTRL_FASTEST);
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do_spi_byte(cmd);
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#if 0
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if (cmd == CPLD_CMD_READ_FAST) {
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do_spi_byte(0x80);
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do_spi_byte(0);
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do_spi_byte(0);
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}
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#endif
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for (i = 0; i < sendCnt; ++i) {
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if (fastWrite)
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do_spi_byte_fast(sendData[i]);
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else
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do_spi_byte(sendData[i]);
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}
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for (i = 0; i < recvCnt; ++i) {
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if (fastWrite)
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do_spi_byte_fast(0);
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else
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do_spi_byte(0);
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if (recvData) {
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recvData[i] = rb4xx_spi_rreg(SPI_REG_RDS) & 0xff;
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} else if (verifyData) {
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if (verifyData[i] != (rb4xx_spi_rreg(SPI_REG_RDS)
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& 0xff))
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break;
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}
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}
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rb4xx_spi_wreg(SPI_REG_IOC, SBIT_IOC_BASE | SPI_IOC_CS0);
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rb4xx_spi_wreg(SPI_REG_CTRL, spi_ctrl_flash);
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rb4xx_spi_wreg(SPI_REG_FS, 0);
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return i == recvCnt;
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}
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static int got_write = 1;
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static void rb4xx_nand_write_data(const uint8_t *byte, unsigned cnt)
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{
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do_spi_cmd(CPLD_CMD_WRITE_MULT, cnt, byte, 1, NULL, NULL, 1);
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got_write = 1;
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}
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static void rb4xx_nand_write_byte(uint8_t byte)
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{
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rb4xx_nand_write_data(&byte, 1);
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}
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#if USE_FAST_READ
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static uint8_t *rb4xx_nand_read_getaddr(unsigned cnt)
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{
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static unsigned nboffset = 0x100000;
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unsigned addr;
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if (got_write) {
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nboffset = (nboffset + 31) & ~31;
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if (nboffset >= 0x100000) /* 1MB */
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nboffset = 0;
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got_write = 0;
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rb4xx_spi_wreg(SPI_REG_FS, SPI_FS_GPIO);
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rb4xx_spi_wreg(SPI_REG_CTRL, spi_ctrl_fread);
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rb4xx_spi_wreg(SPI_REG_FS, 0);
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}
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addr = KSEG1ADDR(AR71XX_SPI_BASE + SPI_NDATA_BASE) + nboffset;
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DBG("rb4xx_nand_read_getaddr 0x%x cnt 0x%x\n", addr, cnt);
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nboffset += cnt;
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return (uint8_t *)addr;
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}
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static void rb4xx_nand_read_data(uint8_t *buf, unsigned cnt)
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{
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unsigned size32 = cnt & ~31;
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unsigned remain = cnt & 31;
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if (size32) {
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uint8_t *addr = rb4xx_nand_read_getaddr(size32);
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memcpy(buf, (void *)addr, size32);
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}
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if (remain) {
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do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, remain,
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buf + size32, NULL, 0);
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}
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}
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static int rb4xx_nand_verify_data(const uint8_t *buf, unsigned cnt)
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{
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unsigned size32 = cnt & ~31;
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unsigned remain = cnt & 31;
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if (size32) {
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uint8_t *addr = rb4xx_nand_read_getaddr(size32);
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if (memcmp(buf, (void *)addr, size32) != 0)
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return 0;
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}
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if (remain) {
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return do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, remain,
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NULL, buf + size32, 0);
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}
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return 1;
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}
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#else /* USE_FAST_READ */
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static void rb4xx_nand_read_data(uint8_t *buf, unsigned cnt)
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{
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do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, cnt, buf, NULL, 0);
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}
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static int rb4xx_nand_verify_data(const uint8_t *buf, unsigned cnt)
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{
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return do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, cnt, NULL, buf, 0);
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}
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#endif /* USE_FAST_READ */
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static void rb4xx_nand_write_cfg(uint8_t byte)
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{
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do_spi_cmd(CPLD_CMD_WRITE_CFG, 1, &byte, 0, NULL, NULL, 0);
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got_write = 1;
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}
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static int rb4xx_nand_dev_ready(struct mtd_info *mtd)
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{
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return gpio_get_value(RB4XX_NAND_GPIO_RDY);
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}
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static void rb4xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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if (ctrl & NAND_CTRL_CHANGE) {
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uint8_t cfg = CFG_BIT_nLEDS;
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cfg |= (ctrl & NAND_CLE) ? CFG_BIT_CLE : 0;
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cfg |= (ctrl & NAND_ALE) ? CFG_BIT_ALE : 0;
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cfg |= (ctrl & NAND_NCE) ? 0 : CFG_BIT_nCE;
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rb4xx_nand_write_cfg(cfg);
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}
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if (cmd != NAND_CMD_NONE)
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rb4xx_nand_write_byte(cmd);
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}
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static uint8_t rb4xx_nand_read_byte(struct mtd_info *mtd)
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{
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uint8_t byte = 0;
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rb4xx_nand_read_data(&byte, 1);
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return byte;
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}
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static void rb4xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
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int len)
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{
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rb4xx_nand_write_data(buf, len);
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}
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static void rb4xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf,
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int len)
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{
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rb4xx_nand_read_data(buf, len);
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}
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static int rb4xx_nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf,
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int len)
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{
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if (!rb4xx_nand_verify_data(buf, len))
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return -EFAULT;
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return 0;
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}
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static unsigned get_spi_ctrl(unsigned hz_max, const char *name)
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{
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unsigned div;
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div = (ar71xx_ahb_freq - 1) / (2 * hz_max);
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/*
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* CPU has a bug at (div == 0) - first bit read is random
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*/
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if (div == 0)
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++div;
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if (name) {
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unsigned ahb_khz = (ar71xx_ahb_freq + 500) / 1000;
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unsigned div_real = 2 * (div + 1);
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printk(KERN_INFO "%s SPI clock %u kHz (AHB %u kHz / %u)\n",
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name,
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ahb_khz / div_real,
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ahb_khz, div_real);
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}
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return SPI_CTRL_FASTEST + div;
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}
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static int __init rb4xx_nand_probe(struct platform_device *pdev)
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{
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struct rb4xx_nand_info *info;
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int ret;
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printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n");
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ret = gpio_request(RB4XX_NAND_GPIO_RDY, "NAND RDY");
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if (ret) {
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printk(KERN_ERR "rb4xx-nand: gpio request failed\n");
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return ret;
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}
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ret = gpio_direction_input(RB4XX_NAND_GPIO_RDY);
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if (ret) {
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printk(KERN_ERR "rb4xx-nand: unable to set input mode "
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"on gpio%d\n", RB4XX_NAND_GPIO_RDY);
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goto err_free_gpio;
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}
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info = kzalloc(sizeof(*info), GFP_KERNEL);
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if (!info) {
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printk(KERN_ERR "rb4xx-nand: no memory for private data\n");
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ret = -ENOMEM;
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goto err_free_gpio;
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}
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#if USE_FAST_READ
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spi_ctrl_fread = get_spi_ctrl(RB4XX_NAND_HZ, "NAND");
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#endif
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spi_ctrl_flash = get_spi_ctrl(RB4XX_FLASH_HZ, "FLASH");
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rb4xx_nand_write_cfg(CFG_BIT_nLEDS | CFG_BIT_nCE);
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info->chip.priv = &info;
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info->mtd.priv = &info->chip;
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info->mtd.owner = THIS_MODULE;
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info->chip.cmd_ctrl = rb4xx_nand_cmd_ctrl;
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info->chip.dev_ready = rb4xx_nand_dev_ready;
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info->chip.read_byte = rb4xx_nand_read_byte;
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info->chip.write_buf = rb4xx_nand_write_buf;
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info->chip.read_buf = rb4xx_nand_read_buf;
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info->chip.verify_buf = rb4xx_nand_verify_buf;
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info->chip.chip_delay = 25;
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info->chip.ecc.mode = NAND_ECC_SOFT;
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info->chip.options |= NAND_NO_AUTOINCR;
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platform_set_drvdata(pdev, info);
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ret = nand_scan_ident(&info->mtd, 1);
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if (ret) {
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ret = -ENXIO;
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goto err_free_info;
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}
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if (info->mtd.writesize == 512)
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info->chip.ecc.layout = &rb4xx_nand_ecclayout;
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ret = nand_scan_tail(&info->mtd);
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if (ret) {
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return -ENXIO;
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goto err_set_drvdata;
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}
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#ifdef CONFIG_MTD_PARTITIONS
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ret = add_mtd_partitions(&info->mtd, rb4xx_nand_partitions,
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ARRAY_SIZE(rb4xx_nand_partitions));
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#else
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ret = add_mtd_device(&info->mtd);
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#endif
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if (ret)
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goto err_release_nand;
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return 0;
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err_release_nand:
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nand_release(&info->mtd);
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err_set_drvdata:
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platform_set_drvdata(pdev, NULL);
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err_free_info:
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kfree(info);
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err_free_gpio:
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gpio_free(RB4XX_NAND_GPIO_RDY);
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return ret;
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}
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static int __devexit rb4xx_nand_remove(struct platform_device *pdev)
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{
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struct rb4xx_nand_info *info = platform_get_drvdata(pdev);
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nand_release(&info->mtd);
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platform_set_drvdata(pdev, NULL);
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kfree(info);
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return 0;
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}
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|
|
|
static struct platform_driver rb4xx_nand_driver = {
|
|
.probe = rb4xx_nand_probe,
|
|
.remove = __devexit_p(rb4xx_nand_remove),
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.owner = THIS_MODULE,
|
|
},
|
|
};
|
|
|
|
static int __init rb4xx_nand_init(void)
|
|
{
|
|
return platform_driver_register(&rb4xx_nand_driver);
|
|
}
|
|
|
|
static void __exit rb4xx_nand_exit(void)
|
|
{
|
|
platform_driver_unregister(&rb4xx_nand_driver);
|
|
}
|
|
|
|
module_init(rb4xx_nand_init);
|
|
module_exit(rb4xx_nand_exit);
|
|
|
|
MODULE_DESCRIPTION(DRV_DESC);
|
|
MODULE_VERSION(DRV_VERSION);
|
|
MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
|
|
MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
|
|
MODULE_LICENSE("GPL v2");
|