mirror of
git://projects.qi-hardware.com/openwrt-xburst.git
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1a29ef8e97
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@19815 3c298f89-4303-0410-b956-a3cf2f4a3e73
211 lines
6.2 KiB
C
211 lines
6.2 KiB
C
/*
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* arch/ubicom32/include/asm/pci.h
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* Definitions of PCI operations for Ubicom32 architecture.
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*
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* (C) Copyright 2009, Ubicom, Inc.
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*
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* This file is part of the Ubicom32 Linux Kernel Port.
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*
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* The Ubicom32 Linux Kernel Port is free software: you can redistribute
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* it and/or modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, either version 2 of the
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* License, or (at your option) any later version.
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*
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* The Ubicom32 Linux Kernel Port is distributed in the hope that it
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* will be useful, but WITHOUT ANY WARRANTY; without even the implied
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* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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* the GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with the Ubicom32 Linux Kernel Port. If not,
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* see <http://www.gnu.org/licenses/>.
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*
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* Ubicom32 implementation derived from (with many thanks):
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* arch/m68knommu
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* arch/blackfin
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* arch/parisc
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*/
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#ifndef _ASM_UBICOM32_PCI_H
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#define _ASM_UBICOM32_PCI_H
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#include <asm/io.h>
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/* The PCI address space does equal the physical memory
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* address space. The networking and block device layers use
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* this boolean for bounce buffer decisions.
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*/
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#define PCI_DMA_BUS_IS_PHYS (1)
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/*
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* Perform a master read/write to the PCI bus.
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* These functions return a PCI_RESP_xxx code.
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*/
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extern u8 pci_read_u32(u8 pci_cmd, u32 address, u32 *data);
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extern u8 pci_write_u32(u8 pci_cmd, u32 address, u32 data);
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extern u8 pci_read_u16(u8 pci_cmd, u32 address, u16 *data);
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extern u8 pci_write_u16(u8 pci_cmd, u32 address, u16 data);
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extern u8 pci_read_u8(u8 pci_cmd, u32 address, u8 *data);
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extern u8 pci_write_u8(u8 pci_cmd, u32 address, u8 data);
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#define PCIBIOS_MIN_IO 0x100
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#define PCIBIOS_MIN_MEM 0x10000000
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#define pcibios_assign_all_busses() 0
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#define pcibios_scan_all_fns(a, b) 0
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extern void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
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struct resource *res);
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extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
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struct pci_bus_region *region);
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struct pci_sys_data;
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struct pci_bus;
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struct hw_pci {
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struct list_head buses;
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int nr_controllers;
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int (*setup)(int nr, struct pci_sys_data *);
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struct pci_bus *(*scan)(int nr, struct pci_sys_data *);
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void (*preinit)(void);
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void (*postinit)(void);
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u8 (*swizzle)(struct pci_dev *dev, u8 *pin);
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int (*map_irq)(struct pci_dev *dev, u8 slot, u8 pin);
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};
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/*
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* Per-controller structure
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*/
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struct pci_sys_data {
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struct list_head node;
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int busnr; /* primary bus number */
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u64 mem_offset; /* bus->cpu memory mapping offset */
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unsigned long io_offset; /* bus->cpu IO mapping offset */
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struct pci_bus *bus; /* PCI bus */
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struct resource *resource[3]; /* Primary PCI bus resources */
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/* Bridge swizzling */
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u8 (*swizzle)(struct pci_dev *, u8 *);
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/* IRQ mapping */
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int (*map_irq)(struct pci_dev *, u8, u8);
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struct hw_pci *hw;
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};
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static inline struct resource *
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pcibios_select_root(struct pci_dev *pdev, struct resource *res)
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{
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struct resource *root = NULL;
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if (res->flags & IORESOURCE_IO)
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root = &ioport_resource;
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if (res->flags & IORESOURCE_MEM)
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root = &iomem_resource;
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return root;
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}
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static inline void pcibios_set_master(struct pci_dev *dev)
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{
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/* No special bus mastering setup handling */
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}
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#define HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE 1
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#define HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY 1
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#ifdef CONFIG_PCI
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static inline void * pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
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dma_addr_t *dma_handle)
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{
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void *vaddr = kmalloc(size, GFP_KERNEL);
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if(vaddr != NULL) {
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*dma_handle = virt_to_phys(vaddr);
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}
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return vaddr;
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}
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static inline int pci_dma_supported(struct pci_dev *hwdev, dma_addr_t mask)
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{
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return 1;
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}
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static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
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void *cpu_addr, dma_addr_t dma_handle)
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{
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kfree(cpu_addr);
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return;
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}
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static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
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size_t size, int direction)
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{
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return virt_to_phys(ptr);
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}
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static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
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size_t size, int direction)
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{
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return;
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}
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static inline dma_addr_t
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pci_map_page(struct pci_dev *hwdev, struct page *page,
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unsigned long offset, size_t size, int direction)
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{
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return pci_map_single(hwdev, page_address(page) + offset, size, (int)direction);
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}
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static inline void
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pci_unmap_page(struct pci_dev *hwdev, dma_addr_t dma_address,
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size_t size, int direction)
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{
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pci_unmap_single(hwdev, dma_address, size, direction);
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}
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static inline int
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pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
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int nents, int direction)
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{
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return nents;
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}
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static inline void
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pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
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int nents, int direction)
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{
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}
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static inline void
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pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sg,
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int nelems, int direction)
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{
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}
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static inline void
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pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sg,
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int nelems, int direction)
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{
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}
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static inline void
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pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t dma_handle,
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size_t size, int direction)
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{
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}
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static inline void
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pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t dma_handle,
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size_t size, int direction)
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{
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}
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static inline int
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pci_dma_mapping_error(struct pci_dev *hwdev, dma_addr_t dma_addr)
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{
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return dma_addr == 0;
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}
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extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
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extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
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#endif
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#endif /* _ASM_UBICOM32_PCI_H */
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