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141 lines
3.1 KiB
C
141 lines
3.1 KiB
C
/*
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* linux/arch/mips/jz4740/irq.c
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*
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* JZ4740 interrupt routines.
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*
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* Copyright (c) 2006-2007 Ingenic Semiconductor Inc.
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* Author: <lhhuang@ingenic.cn>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <asm/mach-jz4740/irq.h>
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#include <linux/irq.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <asm/mipsregs.h>
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#include <asm/irq_cpu.h>
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static void __iomem *jz_intc_base;
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static uint32_t jz_intc_wakeup;
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static uint32_t jz_intc_saved;
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#define JZ_REG_BASE_INTC 0x10001000
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#define JZ_REG_INTC_STATUS 0x00
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#define JZ_REG_INTC_MASK 0x04
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#define JZ_REG_INTC_SET_MASK 0x08
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#define JZ_REG_INTC_CLEAR_MASK 0x0c
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#define JZ_REG_INTC_PENDING 0x10
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#define IRQ_BIT(x) BIT((x) - JZ_IRQ_BASE)
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static void intc_irq_unmask(unsigned int irq)
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{
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writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
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}
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static void intc_irq_mask(unsigned int irq)
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{
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writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK);
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}
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static void intc_irq_ack(unsigned int irq)
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{
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writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_PENDING);
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}
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static void intc_irq_end(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
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intc_irq_unmask(irq);
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}
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}
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static int intc_irq_set_wake(unsigned int irq, unsigned int on)
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{
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if (on)
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jz_intc_wakeup |= IRQ_BIT(irq);
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else
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jz_intc_wakeup &= ~IRQ_BIT(irq);
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return 0;
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}
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static struct irq_chip intc_irq_type = {
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.name = "INTC",
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.mask = intc_irq_mask,
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.unmask = intc_irq_unmask,
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.ack = intc_irq_ack,
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.end = intc_irq_end,
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.set_wake = intc_irq_set_wake,
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};
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static irqreturn_t jz4740_cascade(int irq, void *data)
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{
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uint32_t irq_reg;
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irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
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if (irq_reg) {
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generic_handle_irq(ffs(irq_reg) - 1 + JZ_IRQ_BASE);
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return IRQ_HANDLED;
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}
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return 0;
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}
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static struct irqaction jz4740_cascade_action = {
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.handler = jz4740_cascade,
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.name = "JZ4740 cascade interrupt"
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};
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void __init arch_init_irq(void)
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{
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int i;
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mips_cpu_irq_init();
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jz_intc_base = ioremap(JZ_REG_BASE_INTC, 0x14);
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for (i = JZ_IRQ_BASE; i < JZ_IRQ_BASE + 32; i++) {
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intc_irq_mask(i);
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set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
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}
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setup_irq(2, &jz4740_cascade_action);
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}
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asmlinkage void plat_irq_dispatch(void)
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{
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unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
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if (pending & STATUSF_IP2)
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jz4740_cascade(2, NULL);
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else if(pending & STATUSF_IP3)
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do_IRQ(3);
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else
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spurious_interrupt();
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}
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/* TODO: Use sysdev */
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void jz4740_intc_suspend(void)
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{
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jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK);
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printk("intc wakeup: %d\n", jz_intc_wakeup);
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writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK);
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}
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void jz4740_intc_resume(void)
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{
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writel(~jz_intc_saved, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
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}
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